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user?s manual all information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by renesas electronics corp. without notice. please review the latest information published by renesas electronics corp. through various m eans, including the renesas electronics corp. website (http://www.renesas.com). 78k0r/lx3 user?s manual: hardware rev.5.01 jun 2011 16 16-bit single-chip microcontrollers www.renesas.com
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notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, et c., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cm os device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an in ternal input level may be generated due to noise, etc., causing malfunction. cmos devices behave different ly than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resist or if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static elec tricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequat e. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semi conductor devices must be stored and transported in an anti-static container, static shielding bag or conducti ve material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touc hed with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turn ed on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o setti ngs or contents of registers. a device is not initialized un til the reset signal is received. a re set operation must be executed immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the po wer supply off, as a rule, switch o ff the external power supply and then the internal power supply. use of the reverse powe r on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related sp ecifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that re sults from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elem ents. input of signals during th e power off state must be judged separately for each device and according to re lated specifications governing the device.
how to use this manual readers this manual is intended for user engineer s who wish to understand the functions of the 78k0r/lx3 microcontrollers and design and develop application systems and programs for these devices. the target products are as follows. ? 78k0r/lf3: pd78f1500a, 78f1501a, 78f150 2a, 78f1510a, 78f1512a ? 78k0r/lg3: pd78f1503a, 78f1504a, 78f150 5a, 78f1513a, 78f1515a ? 78k0r/lh3: pd78f1506a, 78f1507a, 78f150 8a, 78f1516a, 78f1518a purpose this manual is intended to give users an u nderstanding of the functions described in the organization below. organization the manual for the 78k0r/lx3 microcontrollers is separated into two parts: this manual and the instructions edition (common to the 78k0r microcontroller series). 78k0r/lx3 preliminary user?s manual (this manual) 78k0r microcontrollers user?s manual instructions ? pin functions ? internal block functions ? interrupts ? other on-chip peripheral functions ? electrical specifications ? cpu functions ? instruction set ? explanation of each instruction how to read this manual it is assumed that the readers of this m anual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? to gain a general understanding of functions: read this manual in the order of the contents . the mark ?? shows major revised points. the revised points can be easily searched by copying an ?? in the pdf file and specifying it in the ?find what.? field. ? how to interpret the register format: for a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the ra78k0r, and is defined as an sfr variable using the #pragma sfr directive in the cc78k0r. ? to know details of the 78k0r series instructions: refer to the separate document 78k0r microcontrollers instructions user?s manual (r01us0029e) .
conventions data significance: higher digits on the left and lower digits on the right active low representations: (overscore over pin and signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representations: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this publ ication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. 78k0r/lx3 user?s manual hardware this manual 78k0r microcontrollers instructions user?s manual r01us0029e documents related to development tools (software) (user?s manuals) document name document no. operation u18549e cc78k0r ver. 2.00 c compiler language u18548e operation u18547e ra78k0r ver. 1.20 assembler package language u18546e operation u18601e sm+ system simulator user open interface u18212e pm+ ver. 6.30 u18416e id78k0r-qb ver. 3.20 integrated debugger operation u17839e documents related to development tools (hardware) (user?s manuals) document name document no. qb-78k0rlx3 in-circuit emulator u19336e qb-mini2 on-chip debug emulator with programming function u18371e documents related to flash memo ry programming (u ser?s manuals) document name document no. pg-fp5 flash memory programmer r20ut0008e qb-programmer programmi ng gui operation u18527e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing.
other documents document name document no. renesas microcomputer general catalog r01cs0001e semiconductor selection guide ? products and packages ? x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device mount manual? website (http://www.renesas.com/prod/package/manual/index.html). caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. all trademarks and registered trademarks ar e the property of their respective owners. eeprom is a trademark of rene sas electronics corporation. windows is a registered trademark or trademark of microsof t corporation in the united states and/or other countries. superflash is a registered trademark of silicon storage technology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc.
contents chapter 1 outline........................................................................................................... .................... 1 1.1 features.................................................................................................................. ......................... 1 1.2 ordering information...................................................................................................... ................ 3 1.3 pin configuration (top view) .............................................................................................. .......... 4 1.3.1 78k 0r/lf3 ............................................................................................................... ......................... 4 1.3.2 78k 0r/lg3 ............................................................................................................... ........................ 7 1.3.3 78k 0r/lh3............................................................................................................... ....................... 10 1.4 block diagram ............................................................................................................. ................. 13 1.4.1 78k 0r/lf3 ............................................................................................................... ....................... 13 1.4.2 78k 0r/lg3 ............................................................................................................... ...................... 15 1.4.3 78k 0r/lh3............................................................................................................... ....................... 17 1.5 outline of functions...................................................................................................... ............... 19 chapter 2 pin functions .................................................................................................... ........... 23 2.1 pin function list ......................................................................................................... ................. 23 2.1.1 78k 0r/lf3 ............................................................................................................... ....................... 24 2.1.2 78k 0r/lg3 ............................................................................................................... ...................... 30 2.1.3 78k 0r/lh3............................................................................................................... ....................... 36 2.2 description of pin func tions .............................................................................................. ........ 43 2.2.1 p00 to p02 .............................................................................................................. ........................ 43 2.2.2 p10 to p17 .............................................................................................................. ........................ 44 2.2.3 p20 to p27 .............................................................................................................. ........................ 46 2.2.4 p30 to p34 .............................................................................................................. ........................ 47 2.2.5 p 40, p41 ................................................................................................................ ......................... 48 2.2.6 p50 to p57 .............................................................................................................. ........................ 49 2.2.7 p 60, p61 ................................................................................................................ ......................... 50 2.2.8 p70 to p77 .............................................................................................................. ........................ 51 2.2.9 p80 to p87 .............................................................................................................. ........................ 52 2.2.10 p90 to p97 ............................................................................................................. ....................... 53 2.2.11 p100 to p102 ........................................................................................................... ..................... 54 2.2.12 p1 10, p 111 ............................................................................................................. ...................... 54 2.2.13 p120 to p124 ........................................................................................................... ..................... 55 2.2.14 p130................................................................................................................... ........................... 56 2.2.15 p140 to p147 ........................................................................................................... ..................... 56 2.2.16 p150 to p152, p157 ..................................................................................................... ................. 57 2.2.17 com0 to com7........................................................................................................... .................. 57 2.2.18 segxx .................................................................................................................. ......................... 57 2.2.19 vlc0 to vlc3 ........................................................................................................... .................... 57 2.2.20 vrefout/avrefp ( pd78f150xa only) .................................................................................. 58 2.2.21 avref ( pd78f151xa only) ....................................................................................................... 58 2.2.22 reset .................................................................................................................. ........................ 58 2.2.23 regc................................................................................................................... ......................... 58 2.2.24 flmd0 .................................................................................................................. ........................ 58 2.2.25 avdd0, avdd1, avdd, evdd1 , avss, evdd, evss, vdd, vss ............................................. 59 2.3 pin i/o circuits and recomme nded connection of unu sed pins ........................................... 60 2.3.1 78k 0r/lf3 ............................................................................................................... ....................... 60
2.3.2 78k 0r/lg3 ............................................................................................................... ...................... 63 2.3.3 78k 0r/lh3............................................................................................................... ....................... 66 chapter 3 cpu architecture ................................................................................................. ..... 74 3.1 memory space .............................................................................................................. ................ 74 3.1.1 internal progr am memory space ........................................................................................... .......... 79 3.1.2 mi rror ar ea............................................................................................................. .......................... 81 3.1.3 internal dat a memory space.............................................................................................. .............. 83 3.1.4 special function register (sfr) area .................................................................................... ........... 84 3.1.5 extended special function register (2nd sfr: 2nd special func tion register) area ...................... 84 3.1.6 data me mory addr essing .................................................................................................. .............. 85 3.2 processor registers....................................................................................................... .............. 88 3.2.1 contro l regist ers ....................................................................................................... ....................... 88 3.2.2 general-pur pose registers............................................................................................... ................ 90 3.2.3 es and cs regist ers..................................................................................................... ................... 92 3.2.4 special functi on register s (sfrs) ....................................................................................... ............. 93 3.2.5 extended specia l function registers (2nd sfrs: 2nd special function register s) .......................... 99 3.3 instruction address addressi ng............................................................................................ ... 108 3.3.1 relati ve addre ssing..................................................................................................... .................. 108 3.3.2 immedi ate addres sing .................................................................................................... ............... 108 3.3.3 table indi rect addr essing ............................................................................................... ............... 109 3.3.4 register di rect addr essing.............................................................................................. ............... 110 3.4 addressing for processing data addresses ........................................................................... 111 3.4.1 impli ed addre ssing ...................................................................................................... .................. 111 3.4.2 regist er addre ssing ..................................................................................................... ................. 111 3.4.3 direct addre ssing ....................................................................................................... ................... 112 3.4.4 short di rect addr essing ................................................................................................. ................ 113 3.4.5 sfr addressi ng .......................................................................................................... .................. 114 3.4.6 register i ndirect addr essi ng............................................................................................ .............. 115 3.4.7 based addre ssing........................................................................................................ .................. 116 3.4.8 based in dexed addr essing ................................................................................................ ............ 119 3.4.9 stack addre ssing........................................................................................................ ................... 120 chapter 4 port functions ................................................................................................... ...... 121 4.1 port functions ............................................................................................................ ................ 121 4.2 port configuration..................................................... ................................................... .............. 129 4.2.1 po rt 0.................................................................................................................. ........................... 130 4.2.2 po rt 1.................................................................................................................. ........................... 133 4.2.3 po rt 2.................................................................................................................. ........................... 138 4.2.4 po rt 3.................................................................................................................. ........................... 142 4.2.5 po rt 4.................................................................................................................. ........................... 144 4.2.6 po rt 5.................................................................................................................. ........................... 146 4.2.7 po rt 6.................................................................................................................. ........................... 150 4.2.8 po rt 7.................................................................................................................. ........................... 151 4.2.9 po rt 8.................................................................................................................. ........................... 156 4.2.10 po rt 9................................................................................................................. .......................... 162 4.2.11 po rt 10................................................................................................................ ......................... 165 4.2.12 po rt 11................................................................................................................ ......................... 167 4.2.13 po rt 12................................................................................................................ ......................... 168
4.2.14 po rt 13................................................................................................................ ......................... 172 4.2.15 po rt 14................................................................................................................ ......................... 173 4.2.16 po rt 15................................................................................................................ ......................... 176 4.3 registers controlling port function ....................... ................................................................ . 180 4.4 port function operations .................................................................................................. ........ 197 4.4.1 writi ng to i/o port ..................................................................................................... ..................... 197 4.4.2 reading from i/o port................................................................................................... ................. 197 4.4.3 operatio ns on i/o port.................................................................................................. ................. 197 4.4.4 connecting to external device with different power potent ial (2.5 v, 3 v)...................................... 198 4.5 settings of port mode register and output latch when using alternate function........... 200 4.6 cautions on 1-bit manipulation instruction for port register n (p n) .................................... 205 chapter 5 clock generator .................................................................................................. .. 206 5.1 functions of clock generator.............................................................................................. ..... 206 5.2 configuration of clock gene rator .......................................................................................... .. 207 5.3 registers controlling clock generator................... ................................................................. 2 09 5.4 system clock oscillator ................................................................................................... ......... 222 5.4.1 x1 oscill ator........................................................................................................... ........................ 222 5.4.2 xt1 oscilla tor .......................................................................................................... ...................... 222 5.4.3 internal hi gh-speed os cillator .......................................................................................... .............. 226 5.4.4 internal lo w-speed os cillator........................................................................................... ............... 226 5.4.5 pr escaler ............................................................................................................... ........................ 226 5.5 clock generator operation ................................................................................................. ...... 227 5.6 controlling clock......................................................................................................... ............... 232 5.6.1 example of controlli ng high-speed syst em clock .......................................................................... . 232 5.6.2 example of controlling intern al high-speed osc illation cl ock.......................................................... 23 5 5.6.3 example of cont rolling subsyst em clock.................................................................................. ...... 237 5.6.4 example of controlling intern al low-speed osci llation cl ock ........................................................... 23 9 5.6.5 cpu clock stat us transiti on diagr am..................................................................................... ......... 240 5.6.6 condition before changing cpu clock and processi ng after changing cpu cl ock ........................ 247 5.6.7 time required for switchover of cpu clock and main system cl ock .............................................. 249 5.6.8 conditions before clock osc illation is stopp ed .......................................................................... ..... 250 chapter 6 timer array unit................................................................................................ ...... 251 6.1 functions of timer array unit............................................................................................. ...... 253 6.1.1 functions of eac h channel when it oper ates indepe ndently .......................................................... 253 6.1.2 functions of each channel when it operates with another channe l ............................................... 254 6.1.3 lin-bus supporting function (cha nnel 7 of timer a rray unit 0 only) ................................................ 254 6.2 configuration of timer array unit .................... ..................................................................... ... 255 6.3 registers controlling timer array unit................... ................................................................. 261 6.4 channel output (topq pin) control ................. ........................................................................ 289 6.4.1 topq pin output ci rcuit config uration................................................................................... .......... 289 6.4.2 topq pin output setting ................................................................................................. .............. 290 6.4.3 cautions on cha nnel output operation .................................................................................... .... 291 6.4.4 collective mani pulation of topq bits .................................................................................... ......... 294 6.4.5 timer interrupt and topq pi n output at oper ation st art............................................................... 295 6.5 channel input control.................................................. ................................................... ........... 296 6.5.1 edge dete ction ci rcuit .................................................................................................. .................. 296 6.6 basic function of timer array unit .................. ...................................................................... .. 297
6.6.1 overview of single-operation f unction and combination operation f unction ................................... 297 6.6.2 basic rules of comb ination operat ion func tion ........................................................................... .... 297 6.6.3 applicable range of basic rules of comb ination operati on functi on ................................................ 298 6.7 operation of timer array unit as independent channel ........................................................ 299 6.7.1 operation as interv al timer/squar e wave output .......................................................................... .. 299 6.7.2 operation as ex ternal event count er ..................................................................................... ........ 306 6.7.3 operation as frequency divi der .......................................................................................... ........... 310 6.7.4 operation as input pulse interval measur ement ........................................................................... . 315 6.7.5 operation as in put signal high-/low-le vel width me asurem ent....................................................... 319 6.8 operation of plural channels of timer array un it .................................................................. 323 6.8.1 operation as pwm f unction ............................................................................................... ........... 323 6.8.2 operation as one-s hot pulse output function............................................................................. .... 330 6.8.3 operation as mult iple pwm output func tion ............................................................................... ... 337 chapter 7 real-time counter................................................................................................ ... 345 7.1 functions of real-time c ounter............................................................................................ ... 345 7.2 configuration of real-time c ounter ........................................................................................ 345 7.3 registers controlling real-time counter.................. .............................................................. 347 7.4 real-time counter operation ............................................................................................... .... 362 7.4.1 starting operation of real-tim e coun ter ................................................................................. ......... 362 7.4.2 shifting to stop m ode after starti ng operat ion.......................................................................... ... 363 7.4.3 reading/writi ng real-tim e count er....................................................................................... ........... 364 7.4.4 setting alarm of real-tim e count er ...................................................................................... ........... 366 7.4.5 1 hz output of real-tim e counter ........................................................................................ ............ 367 7.4.6 32.768 khz output of real-tim e coun ter .................................................................................. ....... 367 7.4.7 512 hz or 16.384 khz ou tput of real -time c ounter ........................................................................ . 368 7.4.8 example of watch error co rrection of real-t ime coun ter ................................................................. 3 69 chapter 8 watchdog timer ................................................................................................... .... 374 8.1 functions of watchdog timer............................................................................................... .... 374 8.2 configuration of watchdog time r ........................................................................................... . 375 8.3 register controlling watchdog timer...................................................................................... 3 76 8.4 operation of watchdog timer............................................................................................... .... 377 8.4.1 controlling operat ion of watc hdog timer ................................................................................. ....... 377 8.4.2 setting overflow ti me of watc hdog ti mer................................................................................. ....... 378 8.4.3 setting window open pe riod of watc hdog ti mer ............................................................................ . 379 8.4.4 setting watchdog ti mer interval interrupt ............................................................................... ........ 380 chapter 9 clock output/buzzer output controller ................................................. 381 9.1 functions of clock output/buzze r output controller .................... ........................................ 381 9.2 configuration of clock output /buzzer output controller...................................................... 382 9.3 registers controlling clock ou tput/buzzer output controller ............................................. 382 9.4 operations of clock output/b uzzer output controller .................. ........................................ 384 9.4.1 operation as output pin ................................................................................................. ................ 384 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) .................................................................. 385 10.1 function of a/d converter................................................................................................ ....... 385 10.2 configuration of a/d converter ........................................................................................... ... 388
10.3 registers used in a/d converter.......................................................................................... .. 390 10.4 a/d converter operations ............................................. .................................................... ...... 403 10.4.1 basic operations of a/d c onverter ...................................................................................... ......... 403 10.4.2 input voltage and conversion results ................................................................................... ........ 405 10.4.3 a/d converte r operati on modes.......................................................................................... ......... 406 10.5 how to read a/d converter characteristics tabl e............................................................... 412 10.6 cautions for a/d converter ............................................................................................... ...... 414 chapter 11 d/a converter ( pd78f150xa only) .................................................................... 418 11.1 function of d/a converter................................................................................................ ....... 418 11.2 configuration of d/a converter ........................................................................................... ... 418 11.3 registers used in d/a converter.......................................................................................... .. 420 11.4 operation of d/a converter............................................................................................... ...... 423 11.4.1 operation in norma l mode............................................................................................... ............ 423 11.4.2 operation in real-time out put mode ..................................................................................... ........ 423 11.5 cautions for d/a converter ............................................................................................... ...... 424 chapter 12 operational amplifier ( pd78f150xa only).................................................... 425 12.1 function of operational amplifier .................. ...................................................................... .. 425 12.2 configuration of operational amplifier.................................................................................. 4 25 12.3 amplifier registers used in operational amplif ier............................................................... 427 12.4 operational amplifier operat ions......................................................................................... .. 433 12.4.1 single amp mode........................................................................................................ ................ 433 chapter 13 voltage reference ( pd78f150xa only)........................................................... 434 13.1 function of voltage refe rence ............................................................................................ ... 434 13.2 configuration of voltage re ference ....................................................................................... 434 13.3 amplifier registers used in voltage reference .................................................................... 435 13.4 voltage reference operations ..................................... ........................................................ ... 437 13.4.1 reference vo ltage out put m ode .......................................................................................... ........ 437 13.5 cautions for voltage reference................................ ........................................................... ... 437 chapter 14 serial array unit.............................................................................................. .... 438 14.1 functions of serial array unit........................................................................................... ...... 439 14.1.1 3-wire serial i/o (csi 00, csi01, cs i10, cs i20) ......................................................................... . 439 14.1.2 uart (uart0, ua rt1, uart2, uart 3) .................................................................................. 439 14.1.3 simplified i 2 c (iic10, iic20) ......................................................................................................... 440 14.2 configuration of serial array unit ............... ........................................................................ ... 441 14.3 registers controlling serial array unit................. ................................................................. 446 14.4 operation stop mode ...................................................................................................... ......... 469 14.4.1 stoppin g the operati on by units........................................................................................ ........... 469 14.4.2 stoppin g the operation by chann els ..................................................................................... ....... 470 14.5 operation of 3-wire serial i/o (csi00, csi 01, csi10, csi20) communication ................... 472 14.5.1 master transmission .................................................................................................... ................ 473 14.5.2 master recept ion....................................................................................................... ................... 482 14.5.3 master trans mission/rec eption .......................................................................................... .......... 488 14.5.4 slave transmi ssion ..................................................................................................... ................. 496 14.5.5 slave reception ........................................................................................................ ................... 505 14.5.6 slave trans mission/rec eption ........................................................................................... ........... 511
14.5.7 calculating tr ansfer clock frequency................................................................................... ......... 520 14.6 operation of uart (uart0, uart1, uart2, uart3) communication ............................. 522 14.6.1 uart transmi ssion ...................................................................................................... ............... 523 14.6.2 uart recept ion......................................................................................................... .................. 533 14.6.3 lin transmi ssion....................................................................................................... ................... 540 14.6.4 lin reception.......................................................................................................... ..................... 543 14.6.5 calculat ing baud rate .................................................................................................. ................ 548 14.7 operation of simplified i 2 c (iic10, iic20) communication ................................................... 552 14.7.1 address fi eld transmi ssion ............................................................................................. ............. 553 14.7.2 data transmi ssion...................................................................................................... .................. 558 14.7.3 data reception ......................................................................................................... .................... 561 14.7.4 stop conditi on gener ation.............................................................................................. .............. 565 14.7.5 calculati ng transfe r rate .............................................................................................. ................ 566 14.8 processing procedure in case of error ................ ................................................................. 569 14.9 relationship between register settings and pins ............................................................... 571 chapter 15 serial interface iica .......................................................................................... . 578 15.1 functions of serial interface iica................ ....................................................................... .... 578 15.2 configuration of serial inte rface iica ................................................................................... . 581 15.3 registers controlling serial interface iica........... ................................................................. 58 4 15.4 i 2 c bus mode functions........................................................................................................... 596 15.4.1 pin c onfigurat ion ...................................................................................................... ................... 596 15.4.2 setting transfer clock by us ing iicwl and iicwh regist ers ........................................................ 597 15.5 i 2 c bus definitions and control methods .............................................................................. 598 15.5.1 start conditi ons ....................................................................................................... .................... 598 15.5.2 a ddresses .............................................................................................................. ..................... 599 15.5.3 transfer direct ion specif ication....................................................................................... ............. 599 15.5.4 ackno wledge (a ck) ...................................................................................................... .............. 600 15.5.5 stop condition ......................................................................................................... .................... 601 15.5.6 wait ................................................................................................................... .......................... 602 15.5.7 canc eling wait ......................................................................................................... .................... 604 15.5.8 interrupt request (intiica) gen eration timing and wait cont rol ................................................... 605 15.5.9 address matc h detection method ......................................................................................... ....... 606 15.5.10 erro r detec tion....................................................................................................... .................... 606 15.5.11 exte nsion code........................................................................................................ .................. 606 15.5.12 arbi tration........................................................................................................... ....................... 607 15.5.13 wake up func tion....................................................................................................... ................. 609 15.5.14 communicati on reserv ation............................................................................................. .......... 612 15.5.15 ca utions .............................................................................................................. ...................... 616 15.5.16 communica tion oper ations.............................................................................................. .......... 617 15.5.17 timing of i 2 c interrupt request (int iica) occu rrence ................................................................ 625 15.6 timing charts ............................................................................................................ ............... 646 chapter 16 lcd controller/driver ....................................................................................... 661 16.1 functions of lcd controller/driver....................... ................................................................ . 661 16.2 configuration of lcd controller/driver ................ ................................................................. 66 5 16.3 registers controlling lcd controller/driver........... .............................................................. 667 16.4 lcd display data memory.................................................................................................. ..... 675 16.5 setting lcd controller/driver ............................................................................................ ..... 678
16.6 common and segment signals .............................................................................................. 6 80 16.7 display modes ............................................................................................................ .............. 687 16.7.1 static di splay ex ample................................................................................................. ................ 687 16.7.2 two-time-slic e display example ......................................................................................... ......... 690 16.7.3 three-time-slic e display example ....................................................................................... ......... 693 16.7.4 four-time-slic e display example ........................................................................................ .......... 697 16.7.5 eight-time-slic e display example ....................................................................................... .......... 700 16.8 supplying lcd drive voltages vlc0, vlc1, vlc2 , and vlc3 ............................................ 703 16.8.1 external resi stance divisi on met hod .................................................................................... ........ 703 16.8.2 internal vo ltage boosti ng method ....................................................................................... ......... 704 16.8.3 capacito r split method................................................................................................. ................ 705 16.9 selection of lcd display data ............................................................................................ .... 706 16.9.1 a-pattern ar ea and b-pattern area data di splay ......................................................................... . 706 16.9.2 blinking display (alternately disp laying a-pattern and b- pattern ar ea data) ................................ 707 chapter 17 multiplier/divider ............................................................................................... .... 708 17.1 functions of multiplier/divider .................................. ........................................................... 708 17.2 configuration of multiplier/divide r ....................................................................................... 708 17.3 register controlling multiplier/div ider ................................................................................ 713 17.4 operations of multiplier/divider ............................................................................................ 714 17.4.1 multiplication operation....................................................................................................... ..... 714 17.4.2 division op eratio n ............................................................................................................. ....... 715 chapter 18 dma controller .................................................................................................. ... 717 18.1 functions of dma controller .............................................................................................. .... 717 18.2 configuration of dma controller .................... ...................................................................... .. 718 18.3 registers controlling dma controller ................................................................................... 72 1 18.4 operation of dma contro ller.............................................................................................. ..... 724 18.4.1 operat ion proc edure .................................................................................................... ............... 724 18.4.2 trans fer m ode .......................................................................................................... ................... 725 18.4.3 termination of dma tr ansfer ............................................................................................ ........... 725 18.5 example of setting of dma controller .................. ................................................................. 72 5 18.5.1 csi consec utive trans mission ........................................................................................... .......... 725 18.5.2 csi mast er reception................................................................................................... ................ 727 18.5.3 csi transmi ssion/rec eption ............................................................................................. ............ 729 18.5.4 consecut ive capturing of a/d conversion results ........................................................................ 731 18.5.5 uart consec utive reception + ack transmi ssion ...................................................................... 733 18.5.6 holding dma trans fer pending by dwaitn ................................................................................. 735 18.5.7 forced terminat ion by so ftware ......................................................................................... .......... 736 18.6 cautions on using dma controller ........................................................................................ 7 38 chapter 19 interrupt functions.............................................................................................. 740 19.1 interrupt function types ................................................................................................. ........ 740 19.2 interrupt sources and configur ation ..................................................................................... 7 41 19.3 registers controlling interrupt functions............ ................................................................. 746 19.4 interrupt servicing oper ations ........................................................................................... .... 764 19.4.1 maskable interr upt acknow ledgment ...................................................................................... ..... 764 19.4.2 software interrupt request ack nowledg ment .............................................................................. . 766 19.4.3 multiple in terrupt se rvicing........................................................................................... ................ 767
19.4.4 interrupt request hold ................................................................................................. ................. 770 chapter 20 key interrupt function ..................................................................................... 771 20.1 functions of key interrupt ............................................................................................... ....... 771 20.2 configuration of key in terrupt ........................................................................................... ..... 771 20.3 register controlling key interrupt ........................ ............................................................... .. 772 chapter 21 standby function ................................................................................................ .. 773 21.1 standby function and co nfiguration ..................................................................................... 77 3 21.1.1 standby func tion ....................................................................................................... .................. 773 21.1.2 registers contro lling standby function................................................................................. ........ 773 21.2 standby function operatio n ............................................................................................... .... 776 21.2.1 ha lt m ode .............................................................................................................. ................... 776 21.2.2 st op m ode .............................................................................................................. .................. 782 chapter 22 reset function.................................................................................................. ...... 788 22.1 register for confirming reset source .................. ................................................................. 79 7 chapter 23 power-on-clear circuit...................................................................................... 798 23.1 functions of power-on-clear circuit..................... ................................................................. 798 23.2 configuration of power-on-clea r circuit ............................................................................... 799 23.3 operation of power-on-clear circuit ..................... ................................................................. 799 23.4 cautions for power-on-clear circuit ..................... ................................................................. 802 chapter 24 low-voltage detector ....................................................................................... 804 24.1 functions of low-voltage detector....................... ................................................................. 804 24.2 configuration of low-voltage detector ................................................................................. 805 24.3 registers controlling low-voltage detector........... .............................................................. 805 24.4 operation of low-voltage detector ....................... ................................................................. 810 24.4.1 when us ed as re set ..................................................................................................... ............... 811 24.4.2 when used as interrupt ................................................................................................. .............. 817 24.5 cautions for low-voltage detector ....................... ................................................................. 823 chapter 25 regulator ........................................................................................................ ......... 827 25.1 regulator overview....................................................................................................... ........... 827 25.2 registers controlling regulator .......................................................................................... ... 827 chapter 26 option byte..................................................................................................... .......... 829 26.1 functions of option by tes ................................................................................................ ...... 829 26.1.1 user option byte (000c0h to 000c2h/010c0h to 010c 2h) ....................................................... 829 26.1.2 on-chip debug option byte (000c3h / 010c3h )........................................................................... 83 0 26.2 format of user option byte ............................................................................................... ..... 830 26.3 format of on-chip debug option byte.................. ................................................................. 832 26.4 setting of option byte................................................................................................... ........... 833 chapter 27 flash memory .................................................................................................... ...... 834 27.1 writing with flash memory programmer ............................................................................... 834 27.2 programming environment .................................................................................................. ... 834
27.3 communication mode ....................................................................................................... ....... 835 27.4 connection of pins on board.............................................................................................. .... 837 27.4.1 fl md0 pin.............................................................................................................. ..................... 837 27.4.2 t ool0 pi n.............................................................................................................. ..................... 838 27.4.3 r eset pin .............................................................................................................. .................... 838 27.4.4 po rt pins .............................................................................................................. ........................ 838 27.4.5 re gc pin ............................................................................................................... ..................... 838 27.4.6 x1 an d x2 pins ......................................................................................................... ................... 838 27.4.7 powe r suppl y........................................................................................................... .................... 839 27.5 registers controlling flash memory...................................................................................... 8 39 27.6 programming method ....................................................................................................... ....... 840 27.6.1 controlli ng flash memory............................................................................................... .............. 840 27.6.2 flash memory programmi ng mode.......................................................................................... .... 840 27.6.3 selecting communicati on mode ........................................................................................... ....... 841 27.6.4 communi cation co mmands................................................................................................. ........ 841 27.7 security settings ........................................................................................................ .............. 843 27.8 flash memory programming by self-programming ............................................................. 845 27.8.1 boot swap func tion ..................................................................................................... ................. 847 27.8.2 flash shield window f unction........................................................................................... ............ 849 27.9 creating rom code to place order for previ ously written product .................................. 850 27.9.1 procedure for using rom code to plac e an or der ................................................................... 850 chapter 28 on-chip debug function ..................................................................................... 851 28.1 connecting qb-mini2 to 78k0r/lx3 microcontro llers ......................................................... 851 28.2 on-chip debug security id ................................................................................................ ..... 852 28.3 securing of user resources ............................................................................................... .... 852 chapter 29 bcd correction circuit ....................... .............................................................. 854 29.1 bcd correction circuit function........................... ............................................................... .. 854 29.2 registers used by bcd correction circuit .......... ................................................................. 854 29.3 bcd correction circuit operation ......................... ................................................................ . 855 chapter 30 instruction set.................................................................................................. ...... 857 30.1 conventions used in operation list ..................... ................................................................. 8 57 30.1.1 operand identifiers and specificat ion me thods.......................................................................... .. 857 30.1.2 description of operation column ........................................................................................ .......... 858 30.1.3 description of flag operati on colu mn ................................................................................... ........ 859 30.1.4 prefix instruct ion ..................................................................................................... ................. 859 30.2 operation list ........................................................................................................... ................ 860 chapter 31 electrical specifications ................................................................................. 877 chapter 32 package drawings ................................................................................................. 934 32.1 78k0r/lf3...................................................................................................................... ......... 934 32.2 78k0r/lg3 ...................................................................................................................... ........ 936 32.3 78k0r/lh3 ...................................................................................................................... ........ 937 chapter 33 recommended soldering conditions ........................................................... 938
appendix a development tools............................................................................................... 940 a.1 software package .......................................................................................................... ............ 943 a.2 language processing software ..................................... ......................................................... . 943 a.3 flash memory programming tools.......................................................................................... 94 4 a.3.1 when using flash memory programmer pg-fp5 and fl-p r5...................................................... 944 a.3.2 when using on-chip debug emulator with programm ing function qb-mini2................................. 944 a.4 debugging tools (hardware)............................................. ................................................... .... 945 a.4.1 when using in-circuit emulator qb -78k0rlx 3 ............................................................................. 9 45 a.4.2 when using on-chip debug emulator with programm ing function qb-mini2................................. 946 a.5 debugging tools (software) .............................................. .................................................. ..... 946 appendix b register index .................................................................................................. ....... 947 b.1 register index (in alphabeti cal order with respect to regist er names) ............................ 947 b.2 register index (in alphabetical order with respect to register symbol)........................... 952 appendix c list of cautions ............................................................................................... ...... 957 appendix d revision history ................................................................................................ ..... 996 d.1 major revisions in this edition ........................................................................................... .... 996 d.2 revision history of preceding editions ................. ............................................................... 1000
r01uh0004ej0501 rev.5.01 1 jun 20, 2011 r01uh0004ej0501 rev.5.01 jun 20, 2011 78k0r/lx3 renesas mcu chapter 1 outline the 78k0r/lx3 microcontrollers are 16-bit single-chip microcontrollers that include the 78k0r cpu core and peripheral functions such as rom/ram, lcd controller/drive r, a/d converter, d/a conver ter, operational amplifier, multifunctional serial interfaces, multifunctional timers, real-time counter, and watchdog timer. 1.1 features { minimum instruction execution time can be changed from high speed (0.05 s: @ 20 mhz operation with high-speed system clock) to ultra low-speed (61 s: @ 32.768 khz operation with subsystem clock) { general-purpose register: 8 bits 32 registers (8 bits 8 registers 4 banks) { rom, ram capacities 78k0r/lf3 78k0r/lg3 78k0r/lh3 program memory (rom) data memory (ram) 80 pins 100 pins 128 pins 64 kb 4 kb pd78f1500a, pd78f1510a pd78f1503a, pd78f1513a pd78f1506a, pd78f1516a 96 kb 6 kb pd78f1501a pd78f1504a pd78f1507a 128 kb 7 kb pd78f1502a, pd78f1512a pd78f1505a, pd78f1515a pd78f1508a, pd78f1518a { on-chip internal high-speed oscillation clock ? 20 mhz internal high-speed s oscillation clock: 20 mhz 2.4 % ? 8 mhz internal high-speed s oscillation clock: 8 mhz 2 % (when 1.8 v v dd < 2.7 v) ? 1 mhz internal high-speed s oscillation clock: 1 mhz 13 % { on-chip single-power-supply flash memory (with prohib ition of chip erase/block erase/writing function) { self-programming (with boot swap func tion/flash shield window function) { on-chip debug function { on-chip power-on-clear (poc) circuit and low-voltage detector (lvi) { on-chip watchdog timer (can operate on dedicated internal low-speed oscillation clock) { on-chip multiplier/divider (16 bits 16 bits, 32 bits 32 bits) { on-chip key interrupt function { on-chip clock output/buzzer out put controller (output: 2) { on-chip bcd adjustment { i/o ports: ? 78k0r/lf3: 51 ? 78k0r/lg3: 67 (n-ch open drain: 2) ? 78k0r/lh3: 83 (n-ch open drain: 2) { timer timer 78k0r/lf3 78k0r/lg3 78k0r/lh3 16-bit timer 12 ch (input: 6, output: 6) 12 ch (input: 8, output: 8) 12 ch (input: 12, output: 12) watchdog timer 1 ch real-time counter 1 ch (output:2)
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 2 jun 20, 2011 { serial interface: 1 channel ? 78k0r/lf3: csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel uart (lin-bus supported): 1 channel ? 78k0r/lg3: csi: 1 channel/uart: 1 channel csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel uart (lin-bus supported): 1 channel multimaster i 2 c: 1 channel ? 78k0r/lh3: csi: 2 channels/uart: 1 channel csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel csi: 1 channel/uart: 1 channel/simplified i 2 c: 1 channel uart (lin-bus supported): 1 channel multimaster i 2 c: 1 channel { 12-bit resolution a/d conversion ( pd78f150xa only) ? 78k0r/lf3: 8 channels ? 78k0r/lg3, 78k0r/lh3: 12 channels { 10-bit resolution a/d conversion ( pd78f151xa only) ? 78k0r/lf3: 8 channels ? 78k0r/lg3, 78k0r/lh3: 12 channels { 12-bit resolution d/a converter ( pd78f150xa only): 2 channels { operational amplifier ( pd78f150xa only) ? 78k0r/lf3: 2 channels ? 78k0r/lg3, 78k0r/lh3: 3 channels { on-chip voltage reference (2.0 v/2.5 v) ( pd78f150xa only) { lcd controller/driver (internal volt age boosting method, capacitor split met hod, and external resistance division method are switchable) lcd controller/driver 78k0r/lf3 78k0r/lg3 78k0r/lh3 segment signal output 31 (27) note 40 (36) note 54 (50) note common signal output 4 (8) note note the values in parentheses are the number of signal outputs when 8com is used. { dma controller: 2 channels { power supply voltage: v dd = 1.8 to 5.5 v { operating ambient temperature: t a = ? 40 to +85 c
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 3 jun 20, 2011 1.2 ordering information ? flash memory version (lead-free products) 78k0r/lx3 microcontrollers package part number 80-pin plastic lqfp (14x14) pd78f1500agc-gad-ax, 78f1501agc-gad-ax, 78f1502agc-gad-ax, 78f1510agc-gad-ax, 78f1512agc-gad-ax, 78k0r/lf3 80-pin plastic lqfp (f ine pitch) (12x12) pd78f1500agk-gak-ax, 78f1501agk-gak-ax, 78f1502agk-gak-ax, 78f1510agk-gak-ax, 78f1512agk-gak-ax 78k0r/lg3 100-pin plastic lqfp (fine pitch) (14x14) pd78f1503agc-ueu-ax, 78f1504agc-ueu-ax, 78f1505agc-ueu-ax , 78f1513agc-ueu-ax, 78f1515agc-ueu-ax 78k0r/lh3 128-pin plastic lqfp (fine pitch) (14x20) pd78f1506agf-gat-ax, 78f1507agf-gat-ax, 78f1508agf-gat-ax, 78f1516agf-gat-ax, 78f1518agf-gat-ax caution the 78k0r/lx3 microcontrollers have an on-chip debug function, wh ich is provided for development and evaluation. do not use the on-chip debug functi on in products designated for mass production, because the guaranteed number of re writable times of the flash memory may be exceeded when this function is used, and produc t reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used.
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 4 jun 20, 2011 1.3 pin configuration (top view) 1.3.1 78k0r/lf3 (1) pd78f150xa ? 80-pin plastic lqfp (14 14) ? 80-pin plastic lqfp (fine pitch) (12 12) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 64 63 62 61 67 66 65 21 22 23 24 25 26 27 28 29 30 31 32 33 37 38 39 40 34 35 36 av ss av dd0 p111/ano1 p110/ano0 av dd1 com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 p10/sck20/scl20 p11/intp6/si20/rxd2/sda20 p12/to02/so20/txd2 p13/to04/so10/txd1 p14/intp4/si10/rxd1/sda10 p15/intp7/sck10/scl10 p30/intp1/ti03/to00/rtc1hz p31/intp2/ti00/to03/rtcdiv/rtccl/pclbuz1 p32/intp5/ti01/to01/pclbuz0 p33/intp3/ti07/to07 p130 p20/ani0/amp0- p21/ani1/amp0o p22/ani2/amp0+ p23/ani3/amp1- p24/ani4/amp1o p25/ani5/amp1+ p26/ani6 p157/ani15/av refm v refout /av refp p50/seg30/rxd3 p51/seg29/txd3 p52/seg28/ti02 p53/seg27/ti04 p54/seg26 p55/seg25 p56/seg24 p57/seg23 p90/seg22 p91/seg21 p92/seg20 p140/seg19 p141/seg18 p142/seg17 p143/seg16 p144/seg15 p145/seg14 p146/seg13 p147/seg12 p100/seg11 p120/intp0/exlvi p41/tool1 p40/tool0 p00/caph p01/capl p02/v lc3 v lc2 v lc1 v lc0 reset p124/xt2 p123/xt1 flmd0 p122/x2/exclk p121/x1 regc v ss ev ss v dd ev dd cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to vss via a capacitor (0.47 to 1 f).
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 5 jun 20, 2011 (2) pd78f150xa 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 64 63 62 61 67 66 65 21 22 23 24 25 26 27 28 29 30 31 32 33 37 38 39 40 34 35 36 av ss av dd p111 p110 ev dd1 com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 p10/sck20/scl20 p11/intp6/si20/rxd2/sda20 p12/to02/so20/txd2 p13/to04/so10/txd1 p14/intp4/si10/rxd1/sda10 p15/intp7/sck10/scl10 p30/intp1/ti03/to00/rtc1hz p31/intp2/ti00/to03/rtcdiv/rtccl/pclbuz1 p32/intp5/ti01/to01/pclbuz0 p33/intp3/ti07/to07 p130 p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p157/ani15 av ref p50/seg30/rxd3 p51/seg29/txd3 p52/seg28/ti02 p53/seg27/ti04 p54/seg26 p55/seg25 p56/seg24 p57/seg23 p90/seg22 p91/seg21 p92/seg20 p140/seg19 p141/seg18 p142/seg17 p143/seg16 p144/seg15 p145/seg14 p146/seg13 p147/seg12 p100/seg11 p120/intp0/exlvi p41/tool1 p40/tool0 p00/caph p01/capl p02/v lc3 v lc2 v lc1 v lc0 reset p124/xt2 p123/xt1 flmd0 p122/x2/exclk p121/x1 regc v ss ev ss v dd ev dd cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to vss via a capacitor (0.47 to 1 f).
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 6 jun 20, 2011 pin identification amp0- , amp1- : amplifier input minus amp0+ , amp1+ : amplifier input plus amp0o , amp0o : amplifier output ani0 to ani6, ani15 : analog input (adc) ano0, ado1 : analog output (dac) av ref : analog reference voltage av refm : analog reference voltage minus av refp : analog reference voltage plus av ss : analog ground av dd : analog power supply av dd0 : analog power supply (adc/vref/opamp) av dd1 : analog power supply (dac) caph, capl : capacitor for lcd com0 to com7 : lcd common output ev dd , ev dd1 : power supply for port ev ss : gnd for port exclk : external clock input (main system clock) exlvi : external potential input for low voltage detector flmd0 : flash programming mode intp0 to intp7 : exte rnal interrupt input p00 to p02 : port 0 p10 to p15 : port 1 p20 to p26 : port 2 p30 to p33 : port 3 p40, p41 : port 4 p50 to p57 : port 5 p90 to p92 : port 9 p100 : port 10 p110, p111 : port 11 p120 to p124 : port 12 p130 : port 13 p140 to p147 : port 14 p157 : port 15 pclbuz0, pclbuz1 : programmable clock output /buzzer output regc : regulator capacitance reset: reset rtc1hz : real-time counter correction clock (1hz) output rtccl : real-time counter clock (32 khz original oscillation) output rtcdiv : real-time counter clock (32 khz divided frequency) output rxd1 to rxd3 : receive data sck10, sck20 : serial clock input/output scl10, scl20 : serial clock input/output sda10, sda20 : serial data input/output seg0 to seg30 : lcd segment output si10, si20 : serial data input so10, so20 : serial data output ti00 to ti04, ti07 : timer input to00 to to04, to07 : timer output tool0 : data input/output for tool tool1 : clock output for tool txd1 to txd3 : transmit data v dd : power supply v lc0 to v lc3 : lcd power supply v refout : voltage reference output v ss : ground x1, x2 : crystal oscillator (main system clock) xt1, xt2 : crystal oscillator (subsystem clock)
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 7 jun 20, 2011 1.3.2 78k0r/lg3 (1) pd78f150xa ? 100-pin plastic lqfp (fine pitch) (14 14) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p120/exlvi/intp0 p41/tool1 p40/tool0 p80/intp11/sck00 p81/intp9/rxd0/si00 p82/txd0/so00 p00/caph p01/capl p02/v lc3 v lc2 v lc1 v lc0 reset p124/xt2 p123/xt1 flmd0 p122/x2/exclk p121/x1 regc v ss ev ss v dd ev dd p60/scl0 p61/sda0 p50/seg39/rxd3 p51/seg38/txd3 p52/seg37/ti02 p53/seg36/ti04 p54/seg35 p55/seg34 p56/seg33 p57/seg32 p90/seg31 p91/seg30 p92/seg29 p93/seg28 p94/seg27 p95/seg26 p96/seg25 p97/seg24 p140/seg23 p141/seg22 p142/seg21 p143/seg20 p144/seg19 p145/seg18 p146/seg17 p147/seg16 p100/seg15 v refout /av refp av ss av dd0 p111/ano1 p110/ano0 av dd1 com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 p10/sck20/scl20 p11/intp6/si20/rxd2/sda20 p12/to02/so20/txd2 p13/to04/so10/txd1 p14/intp4/si10/rxd1/sda10 p15/intp7/sck10/scl10 p16/intp10/ti05/to05 p30/intp1/ti03/to00/rtc1hz p31/intp2/ti00/to03/rtcdiv/rtccl/pclbuz1 p32/intp5/ti01/to01/pclbuz0 p33/intp3/ti07/to07 p34/intp8/ti06/to06 p130 p20/ani0/amp0- p21/ani1/amp0o p22/ani2/amp0+ p23/ani3/amp1- p24/ani4/amp1o p25/ani5/amp1+ p26/ani6/amp2- p27/ani7/amp2o p150/ani8/amp2+ p151/ani9 p152/ani10 p157/ani15/av refm cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to vss via a capacitor (0.47 to 1 f).
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 8 jun 20, 2011 (2) pd78f151xa ? 100-pin plastic lqfp (fine pitch) (14 14) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p120/exlvi/intp0 p41/tool1 p40/tool0 p80/intp11/sck00 p81/intp9/rxd0/si00 p82/txd0/so00 p00/caph p01/capl p02/v lc3 v lc2 v lc1 v lc0 reset p124/xt2 p123/xt1 flmd0 p122/x2/exclk p121/x1 regc v ss ev ss v dd ev dd p60/scl0 p61/sda0 p50/seg39/rxd3 p51/seg38/txd3 p52/seg37/ti02 p53/seg36/ti04 p54/seg35 p55/seg34 p56/seg33 p57/seg32 p90/seg31 p91/seg30 p92/seg29 p93/seg28 p94/seg27 p95/seg26 p96/seg25 p97/seg24 p140/seg23 p141/seg22 p142/seg21 p143/seg20 p144/seg19 p145/seg18 p146/seg17 p147/seg16 p100/seg15 av ref av ss av dd p111 p110 ev dd1 com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 p10/sck20/scl20 p11/intp6/si20/rxd2/sda20 p12/to02/so20/txd2 p13/to04/so10/txd1 p14/intp4/si10/rxd1/sda10 p15/intp7/sck10/scl10 p16/intp10/ti05/to05 p30/intp1/ti03/to00/rtc1hz p31/intp2/ti00/to03/rtcdiv/rtccl/pclbuz1 p32/intp5/ti01/to01/pclbuz0 p33/intp3/ti07/to07 p34/intp8/ti06/to06 p130 p20/ani0- p21/ani1 p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p150/ani8 p151/ani9 p152/ani10 p157/ani15 cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to vss via a capacitor (0.47 to 1 f).
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 9 jun 20, 2011 pin identification amp0- to amp2- : amplifier input minus amp0+ to amp2+ : amplifier input plus amp0o to amp2o : amplifier output ani0 to ani10, ani15 : analog input (adc) ano0, ado1 : analog output (dac) av ref : analog reference voltage av refm : analog reference voltage minus av refp : analog reference voltage plus av ss : analog ground av dd : analog power supply av dd0 : analog power supply (adc/vref/opamp) av dd1 : analog power supply (dac) caph, capl : capacitor for lcd com0 to com7 : lcd common output ev dd , ev dd1 : power supply for port ev ss : gnd for port exclk : external clock input (main system clock) exlvi : external potential input for low voltage detector flmd0 : flash programming mode intp0 to intp11 : external interrupt input p00 to p02 : port 0 p10 to p16 : port 1 p20 to p27 : port 2 p30 to p34 : port 3 p40, p41 : port 4 p50 to p57 : port 5 p60, p61 : port 6 p80 to p82 : port 8 p90 to p97 : port 9 p100 : port 10 p110, p111 : port 11 p120 to p124 : port 12 p130 : port 13 p140 to p147 : port 14 p150 to p152, p157 : port 15 pclbuz0, pclbuz1 : programmable clock output /buzzer output regc : regulator capacitance reset: reset rtc1hz : real-time counter correction clock (1hz) output rtccl : real-time counter clock (32 khz original oscillation) output rtcdiv : real-time counter clock (32 khz divided frequency) output rxd0 to rxd3 : receive data sck00, sck10, sck20 : serial clock input/output scl0, scl10, scl20 : se rial clock input/output sda0, sda10, sda20 : se rial data input/output seg0 to seg39 : lcd segment output si00, si10, si20 : serial data input so00, so10, so20 : serial data output ti00 to ti07 : timer input to00 to to07 : timer output tool0 : data input/output for tool tool1 : clock output for tool txd0 to txd3 : transmit data v dd : power supply v lc0 to v lc3 : lcd power supply v refout : voltage reference output v ss : ground x1, x2 : crystal oscillator (main system clock) xt1, xt2 : crystal oscillator (subsystem clock)
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 10 jun 20, 2011 1.3.3 78k0r/lh3 (1) pd78f150xa ? 128-pin plastic lqfp (fine pitch) (14 20) p120/exlvi/intp0 p77/kr7/so01 p76/kr6/si01 p75/kr5/sck01 p74/kr4 p73/kr3 p72/kr2 p71/kr1 p70/kr0 p41/tool1 p40/tool0 p80/intp11/sck00 p81/intp9/rxd0/si00 p82/txd0/so00 p83 p84/to10/ti10 p85/to11/ti11 p86/to12/ti12 p87/to13/ti13 p00/caph p01/capl p02/v lc3 v lc2 v lc1 v lc0 reset p124/xt2 p123/xt1 flmd0 p122/x2/exclk p121/x1 regc v ss ev ss v dd ev dd p60/scl0 p61/sda0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 v refout /av refp av ss av dd0 p111/ano1 p110/ano0 av dd1 com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 p102/seg27 p50/seg53/rxd3 p51/seg52/txd3 p52/seg51/ti02 p53/seg50/ti04 p54/seg49 p55/seg48 p56/seg47 p57/seg46 p90/seg45 p91/seg44 p92/seg43 p93/seg42 p94/seg41 p95/seg40 p96/seg39 p97/seg38 p140/seg37 p141/seg36 p142/seg35 p143/seg34 p144/seg33 p145/seg32 p146/seg31 p147/seg30 p100/seg29 p101/seg28 p10/sck20/scl20 p11/intp6/si20/rxd2/sda20 p12/to02/so20/txd2 p13/to04/so10/txd1 p14/intp4/si10/rxd1/sda10 p15/intp7/sck10/scl10 p16/intp10/ti05/to05 p17 p30/intp1/ti03/to00/rtc1hz p31/intp2/ti00/to03/rtcdiv/rtccl/pclbuz1 p32/intp5/ti01/to01/pclbuz0 p33/intp3/ti07/to07 p34/intp8/ti06/to06 p130 p20/ani0/amp0- p21/ani1/amp0o p22/ani2/amp0+ p23/ani3/amp1- p24/ani4/amp1o p25/ani5/amp1+ p26/ani6/amp2- p27/ani7/amp2o p150/ani8/amp2+ p151/ani9 p152/ani10 p157/ani15/av refm cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to vss via a capacitor (0.47 to 1 f).
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 11 jun 20, 2011 (2) pd78f151xa p120/exlvi/intp0 p77/kr7/so01 p76/kr6/si01 p75/kr5/sck01 p74/kr4 p73/kr3 p72/kr2 p71/kr1 p70/kr0 p41/tool1 p40/tool0 p80/intp11/sck00 p81/intp9/rxd0/si00 p82/txd0/so00 p83 p84/to10/ti10 p85/to11/ti11 p86/to12/ti12 p87/to13/ti13 p00/caph p01/capl p02/v lc3 v lc2 v lc1 v lc0 reset p124/xt2 p123/xt1 flmd0 p122/x2/exclk p121/x1 regc v ss ev ss v dd ev dd p60/scl0 p61/sda0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 av ref av ss av dd p111 p110 ev dd1 com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 p102/seg27 p50/seg53/rxd3 p51/seg52/txd3 p52/seg51/ti02 p53/seg50/ti04 p54/seg49 p55/seg48 p56/seg47 p57/seg46 p90/seg45 p91/seg44 p92/seg43 p93/seg42 p94/seg41 p95/seg40 p96/seg39 p97/seg38 p140/seg37 p141/seg36 p142/seg35 p143/seg34 p144/seg33 p145/seg32 p146/seg31 p147/seg30 p100/seg29 p101/seg28 p10/sck20/scl20 p11/intp6/si20/rxd2/sda20 p12/to02/so20/txd2 p13/to04/so10/txd1 p14/intp4/si10/rxd1/sda10 p15/intp7/sck10/scl10 p16/intp10/ti05/to05 p17 p30/intp1/ti03/to00/rtc1hz p31/intp2/ti00/to03/rtcdiv/rtccl/pclbuz1 p32/intp5/ti01/to01/pclbuz0 p33/intp3/ti07/to07 p34/intp8/ti06/to06 p130 p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p150/ani8 p151/ani9 p152/ani10 p157/ani15 cautions 1. make av ss the same potential as v ss . 2. connect the regc pin to vss via a capacitor (0.47 to 1 f).
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 12 jun 20, 2011 pin identification amp0- to amp2- : amplifier input minus amp0+ to amp2+ : amplifier input plus amp0o to amp2o : amplifier output ani0 to ani10, ani15 : analog input (adc) ano0, ado1 : analog output (dac) av ref : analog reference voltage av refm : analog reference voltage minus av refp : analog reference voltage plus av ss : analog ground av dd : analog power supply av dd0 : analog power supply (adc/vref/opamp) av dd1 : analog power supply (dac) caph, capl : capacitor for lcd com0 to com7 : lcd common output ev dd , ev dd1 : power supply for port ev ss : gnd for port exclk : external clock input (main system clock) exlvi : external potential input for low voltage detector flmd0 : flash programming mode intp0 to intp11 : external interrupt input kr0 to kr7 : key return p00 to p02 : port 0 p10 to p17 : port 1 p20 to p27 : port 2 p30 to p34 : port 3 p40, p41 : port 4 p50 to p57 : port 5 p60, p61 : port 6 p70 to p77 : port 7 p80 to p87 : port 8 p90 to p97 : port 9 p100 to p102 : port 10 p110, p111 : port 11 p120 to p124 : port 12 p130 : port 13 p140 to p147 : port 14 p150 to p152, p157 : port 15 pclbuz0, pclbuz1 : programmable clock output /buzzer output regc : regulator capacitance reset: reset rtc1hz : real-time counter correction clock (1hz) output rtccl : real-time counter clock (32 khz original oscillation) output rtcdiv : real-time counter clock (32 khz divided frequency) output rxd0 to rxd3 : receive data sck00, sck01, sck10, sck20 : serial clock input/output scl0, scl10, scl20 : se rial clock input/output sda0, sda10, sda20 : se rial data input/output seg0 to seg53 : lcd segment output si00, si01, si10, si20 : serial data input so00, so01, so10, so20 : serial data output ti00 to ti07, ti10 to ti13 : timer input to00 to to07, to10 to to13 : timer output tool0 : data input/output for tool tool1 : clock output for tool txd0 to txd3 : transmit data v dd : power supply v lc0 to v lc3 : lcd power supply v refout : voltage reference output v ss : ground x1, x2 : crystal oscillator (main system clock) xt1, xt2 : crystal oscillator (subsystem clock)
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 13 jun 20, 2011 1.4 block diagram 1.4.1 78k0r/lf3 (1) pd78f1500a, 78f1501a, 78f1502a port 0 p00 to p02 3 p20 to p26 7 p30 to p33 4 v ss , ev ss flmd0 v dd , ev dd p10 to p15 6 p40, p41 2 p50 to p57 8 p140 to p147 8 ram 78k0r cpu core flash memory timer array unit0 (8ch) ch0 ch1 ti00/p31 to00/p30 ti01/to01/p32 ch2 ti02/p52 ch3 ch4 p121 to p124 4 p90 to p92 3 p110, p111 2 p130 p120 interrupt control intp1/p30, intp2/p31, intp3/p33, intp4/p14, intp5/p32, intp6/p11, intp7/p15 7 intp0/p120 rxd3/p50 (linsel) buzzer output clock output control voltage regulator regc power on clear/ low voltage indicator poc/lvi control reset control exlvi/p120 reset x1/p121 x2/exclk/p122 system control high-speed internal oscillator xt1/p123 xt2/p124 multiplier direct memory access control a/d converter ani0/p20 to ani6/p26 av dd0 av ss pclbuz0/p32, pclbuz1/p31 2 d/a converter ano0/p110, ano1/p111 av dd1 av ss 2 ch7 rxd3/p50 (linsel) ti07/to07/p33 on-chip debug tool0/p40 tool1/p41 bcd adjustment port 1 port 2 port 3 port 4 port 5 port 9 port 10 port 11 port 12 port 13 port 14 port 15 op-amp 0 amp0-/p20 ampo0/p21 amp0+/p22 op-amp 1 amp1-/p23 ampo1/p24 amp1+/p25 voltage reference v refout /av refp av refm /p157 window watchdog timer low-speed internal oscillator realtime counter serial array unit0 (2ch) uart1 rxd1/p14 txd1/p13 csi10 sck10/p15 so10/p13 si10/p14 iic10 scl10/p15 sda10/p14 rtc1hz/p30 rtcdiv/rtccl/p31 serial array unit1 (4ch) uart3 linsel rxd3/p50 txd3/p51 iic20 scl20/p10 sda20/p11 csi20 sck20/p10 so20/p12 si20/p11 rxd2/p11 txd2/p12 uart2 lcd controller/ driver ram space for lcd data seg0 to seg30 31 8 com0 to com7 v lc0 to v lc3 caph capl to02/p12 ti03/p30 to03/p31 ti04/p53 to04/p13 p100 7 p157 ch5 ch6 timer array unit1 (4ch) ch0 ch1 ch2 ch3
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 14 jun 20, 2011 (2) pd78f1510a, 78f1512a port 0 p00 to p02 3 p20 to p27 8 p30 to p34 5 v ss , ev ss flmd0 v dd , ev dd p10 to p16 7 p60, p61 2 p40, p41 2 p50 to p57 8 p140 to p147 8 ram 78k0r cpu core flash memory timer array unit0 (8ch) ch0 ch1 ti00/p31 to00/p30 ti01/to01/p32 ch2 ti02/p52 ch3 ch4 ch5 ti05/to05/p16 ch6 ti06/to06/p34 ch7 rxd3/p50 (linsel) p121 to p124 4 p90 to p97 8 p110, p111 2 p130 p120 p150 to p152, p157 4 interrupt control intp1/p30, intp2/p31, intp3/p33, intp4/p14, intp5/p32, intp6/p11, intp7/p15, intp8/p34, intp9/p81, intp10/p16, intp11/p80 11 intp0/p120 rxd3/p50 (linsel) buzzer output clock output control voltage regulator regc power on clear/ low voltage indicator poc/lvi control reset control exlvi/p120 reset x1/p121 x2/exclk/p122 system control high-speed internal oscillator xt1/p123 xt2/p124 multiplier direct memory access control a/d converter ani0/p20 to ani7/p27, ani8/p150 to ani10/p152, ani15/p157 pclbuz0/p32, pclbuz1/p31 2 ti07/to07/p33 p80 to p82 3 on-chip debug tool0/p40 tool1/p41 window watchdog timer low-speed internal oscillator realtime counter serial array unit0 (4ch) uart0 uart1 csi00 rxd0/p81 txd0/p82 rxd1/p14 txd1/p13 sck00/p80 so00/p82 si00/p81 csi10 sck10/p15 so10/p13 si10/p14 iic10 scl10/p15 sda10/p14 rtc1hz/p30 rtcdiv/rtccl/p31 serial array unit1 (4ch) uart3 linsel rxd3/p50 txd3/p51 serial interface iica sda0/p61 scl0/p60 iic20 scl20/p10 sda20/p11 csi20 sck20/p10 so20/p12 si20/p11 rxd2/p11 txd2/p12 uart2 bcd adjustment port 1 port 2 port 3 port 4 port 5 port 6 port 8 port 9 port 10 port 11 port 12 port 13 port 14 port 15 av ref lcd controller/ driver ram space for lcd data seg0 to seg39 40 8 com0 to com7 v lc0 to v lc3 caph capl to02/p12 ti03/p30 to03/p31 ti04/p53 to04/p13 p100 12 timer array unit1 (4ch) ch0 ch1 ch2 ch3
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 15 jun 20, 2011 1.4.2 78k0r/lg3 (1) pd78f1503a, 78f1504a, 78f1505a port 0 p00 to p02 3 p20 to p27 8 p30 to p34 5 v ss , ev ss flmd0 v dd , ev dd p10 to p16 7 p60, p61 2 p40, p41 2 p50 to p57 8 p140 to p147 8 ram 78k0r cpu core flash memory timer array unit0 (8ch) ch0 ch1 ti00/p31 to00/p30 ti01/to01/p32 ch2 ti02/p52 ch3 ch4 ch5 ti05/to05/p16 ch6 ti06/to06/p34 ch7 rxd3/p50 (linsel) p121 to p124 4 p90 to p97 8 p110, p111 2 p130 p120 p150 to p152, p157 4 interrupt control intp1/p30, intp2/p31, intp3/p33, intp4/p14, intp5/p32, intp6/p11, intp7/p15, intp8/p34, intp9/p81, intp10/p16, intp11/p80 11 intp0/p120 rxd3/p50 (linsel) buzzer output clock output control voltage regulator regc power on clear/ low voltage indicator poc/lvi control reset control exlvi/p120 reset x1/p121 x2/exclk/p122 system control high-speed internal oscillator xt1/p123 xt2/p124 multiplier direct memory access control a/d converter ani0/p20 to ani7/p27, ani8/p150 to ani10/p152, ani15/p157 av dd0 av ss pclbuz0/p32, pclbuz1/p31 2 d/a converter ano0/p110, ano1/p111 av dd1 av ss 2 ti07/to07/p33 p80 to p82 3 on-chip debug tool0/p40 tool1/p41 window watchdog timer low-speed internal oscillator realtime counter serial array unit0 (4ch) uart0 uart1 csi00 rxd0/p81 txd0/p82 rxd1/p14 txd1/p13 sck00/p80 so00/p82 si00/p81 csi10 sck10/p15 so10/p13 si10/p14 iic10 scl10/p15 sda10/p14 rtc1hz/p30 rtcdiv/rtccl/p31 serial array unit1 (4ch) uart3 linsel rxd3/p50 txd3/p51 serial interface iica sda0/p61 scl0/p60 iic20 scl20/p10 sda20/p11 csi20 sck20/p10 so20/p12 si20/p11 rxd2/p11 txd2/p12 uart2 bcd adjustment port 1 port 2 port 3 port 4 port 5 port 6 port 8 port 9 port 10 port 11 port 12 port 13 port 14 port 15 op-amp 0 amp0-/p20 ampo0/p21 amp0+/p22 op-amp 1 amp1-/p23 ampo1/p24 amp1+/p25 op-amp 2 amp2-/p26 ampo2/p27 amp2+/p150 voltage reference v refout /av refp av refm /p157 lcd controller/ driver ram space for lcd data seg0 to seg39 40 8 com0 to com7 v lc0 to v lc3 caph capl to02/p12 ti03/p30 to03/p31 ti04/p53 to04/p13 p100 12 timer array unit1 (4ch) ch0 ch1 ch2 ch3
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 16 jun 20, 2011 (2) pd78f1513a, 78f1515a port 0 p00 to p02 3 p20 to p27 8 p30 to p34 5 v ss , ev ss flmd0 v dd , ev dd p10 to p16 7 p60, p61 2 p40, p41 2 p50 to p57 8 p140 to p147 8 ram 78k0r cpu core flash memory timer array unit0 (8ch) ch0 ch1 ti00/p31 to00/p30 ti01/to01/p32 ch2 ti02/p52 ch3 ch4 ch5 ti05/to05/p16 ch6 ti06/to06/p34 ch7 rxd3/p50 (linsel) p121 to p124 4 p90 to p97 8 p110, p111 2 p130 p120 p150 to p152, p157 4 interrupt control intp1/p30, intp2/p31, intp3/p33, intp4/p14, intp5/p32, intp6/p11, intp7/p15, intp8/p34, intp9/p81, intp10/p16, intp11/p80 11 intp0/p120 rxd3/p50 (linsel) buzzer output clock output control voltage regulator regc power on clear/ low voltage indicator poc/lvi control reset control exlvi/p120 reset x1/p121 x2/exclk/p122 system control high-speed internal oscillator xt1/p123 xt2/p124 multiplier direct memory access control a/d converter ani0/p20 to ani7/p27, ani8/p150 to ani10/p152, ani15/p157 pclbuz0/p32, pclbuz1/p31 2 ti07/to07/p33 p80 to p82 3 on-chip debug tool0/p40 tool1/p41 window watchdog timer low-speed internal oscillator realtime counter serial array unit0 (4ch) uart0 uart1 csi00 rxd0/p81 txd0/p82 rxd1/p14 txd1/p13 sck00/p80 so00/p82 si00/p81 csi10 sck10/p15 so10/p13 si10/p14 iic10 scl10/p15 sda10/p14 rtc1hz/p30 rtcdiv/rtccl/p31 serial array unit1 (4ch) uart3 linsel rxd3/p50 txd3/p51 serial interface iica sda0/p61 scl0/p60 iic20 scl20/p10 sda20/p11 csi20 sck20/p10 so20/p12 si20/p11 rxd2/p11 txd2/p12 uart2 bcd adjustment port 1 port 2 port 3 port 4 port 5 port 6 port 8 port 9 port 10 port 11 port 12 port 13 port 14 port 15 av ref lcd controller/ driver ram space for lcd data seg0 to seg39 40 8 com0 to com7 v lc0 to v lc3 caph capl to02/p12 ti03/p30 to03/p31 ti04/p53 to04/p13 p100 12 timer array unit1 (4ch) ch0 ch1 ch2 ch3
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 17 jun 20, 2011 1.4.3 78k0r/lh3 (1) pd78f1506a, 78f1507a, 78f1508a port 0 p00 to p02 3 p20 to p27 8 p30 to p34 5 v ss , ev ss flmd0 v dd , ev dd p10 to p17 8 p60, p61 2 p70 to p77 8 p40, p41 2 p50 to p57 8 p140 to p147 8 ram 78k0r cpu core flash memory timer array unit0 (8ch) ch0 ch1 ti00/p31 to00/p30 ti01/to01/p32 ch2 ti02/p52 ch3 ch4 ch5 ti05/to05/p16 ch6 ti06/to06/p34 ch7 rxd3/p50 (linsel) p121 to p124 4 p90 to p97 8 p110, p111 2 p130 p120 p150 to p152, p157 4 interrupt control intp1/p30, intp2/p31, intp3/p33, intp4/p14, intp5/p32, intp6/p11, intp7/p15, intp8/p34, intp9/p81, intp10/p16, intp11/p80 11 intp0/p120 rxd3/p50 (linsel) buzzer output clock output control voltage regulator regc power on clear/ low voltage indicator poc/lvi control reset control key return 8 kr0/p70 to kr7/p77 exlvi/p120 reset x1/p121 x2/exclk/p122 system control high-speed internal oscillator xt1/p123 xt2/p124 multiplier direct memory access control a/d converter ani0/p20 to ani7/p27, ani8/p150 to ani10/p152, ani15/p157 av dd0 av ss pclbuz0/p32, pclbuz1/p31 2 d/a converter ano0/p110, ano1/p111 av dd1 av ss 2 ti07/to07/p33 p80 to p87 8 on-chip debug tool0/p40 tool1/p41 window watchdog timer low-speed internal oscillator realtime counter serial array unit0 (4ch) uart0 uart1 csi00 rxd0/p81 txd0/p82 rxd1/p14 txd1/p13 sck00/p80 so00/p82 si00/p81 csi10 sck10/p15 so10/p13 si10/p14 iic10 scl10/p15 sda10/p14 csi01 sck01/p75 so01/p77 si01/p76 rtc1hz/p30 rtcdiv/rtccl/p31 serial array unit1 (4ch) uart3 linsel rxd3/p50 txd3/p51 serial interface iica sda0/p61 scl0/p60 iic20 scl20/p10 sda20/p11 csi20 sck20/p10 so20/p12 si20/p11 rxd2/p11 txd2/p12 uart2 bcd adjustment port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port 10 p100 to p102 3 port 11 port 12 port 13 port 14 port 15 op-amp 0 amp0-/p20 ampo0/p21 amp0+/p22 op-amp 1 amp1-/p23 ampo1/p24 amp1+/p25 op-amp 2 amp2-/p26 ampo2/p27 amp2+/p150 voltage reference v refout /av refp av refm /p157 lcd controller/ driver ram space for lcd data seg0 to seg53 54 8 com0 to com7 v lc0 to v lc3 caph capl to02/p12 ti03/p30 to03/p31 ti04/p53 to04/p13 12 timer array unit1 (4ch) ch0 ch1 ti11/to11/p85 ti10/to10/p84 ch2 ti12/to12/p86 ch3 ti13/to13/p87
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 18 jun 20, 2011 (2) pd78f1516a, 78f1518a port 0 p00 to p02 3 p20 to p27 8 p30 to p34 5 v ss , ev ss flmd0 v dd , ev dd p10 to p17 8 p60, p61 2 p70 to p77 8 p40, p41 2 p50 to p57 8 p140 to p147 8 ram 78k0r cpu core flash memory timer array unit0 (8ch) ch0 ch1 ti00/p31 to00/p30 ti01/to01/p32 ch2 ti02/p52 ch3 ch4 ch5 ti05/to05/p16 ch6 ti06/to06/p34 ch7 rxd3/p50 (linsel) p121 to p124 4 p90 to p97 8 p110, p111 2 p130 p120 p150 to p152, p157 4 interrupt control intp1/p30, intp2/p31, intp3/p33, intp4/p14, intp5/p32, intp6/p11, intp7/p15, intp8/p34, intp9/p81, intp10/p16, intp11/p80 11 intp0/p120 rxd3/p50 (linsel) buzzer output clock output control voltage regulator regc power on clear/ low voltage indicator poc/lvi control reset control key return 8 kr0/p70 to kr7/p77 exlvi/p120 reset x1/p121 x2/exclk/p122 system control high-speed internal oscillator xt1/p123 xt2/p124 multiplier direct memory access control a/d converter ani0/p20 to ani7/p27, ani8/p150 to ani10/p152, ani15/p157 pclbuz0/p32, pclbuz1/p31 2 ti07/to07/p33 p80 to p87 8 on-chip debug tool0/p40 tool1/p41 window watchdog timer low-speed internal oscillator realtime counter serial array unit0 (4ch) uart0 uart1 csi00 rxd0/p81 txd0/p82 rxd1/p14 txd1/p13 sck00/p80 so00/p82 si00/p81 csi10 sck10/p15 so10/p13 si10/p14 iic10 scl10/p15 sda10/p14 csi01 sck01/p75 so01/p77 si01/p76 rtc1hz/p30 rtcdiv/rtccl/p31 serial array unit1 (4ch) uart3 linsel rxd3/p50 txd3/p51 serial interface iica sda0/p61 scl0/p60 iic20 scl20/p10 sda20/p11 csi20 sck20/p10 so20/p12 si20/p11 rxd2/p11 txd2/p12 uart2 bcd adjustment port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port 10 p100 to p102 3 port 11 port 12 port 13 port 14 port 15 av ref lcd controller/ driver ram space for lcd data seg0 to seg53 54 8 com0 to com7 v lc0 to v lc3 caph capl to02/p12 ti03/p30 to03/p31 ti04/p53 to04/p13 12 timer array unit1 (4ch) ch0 ch1 ti11/to11/p85 ti10/to10/p84 ch2 ti12/to12/p86 ch3 ti13/to13/p87
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 19 jun 20, 2011 1.5 outline of functions pd78f150xa (1/2) 78k0r/lf3 78k0r/lg3 78k0r/lh3 item pd78 f1500a pd78 f1501a pd78 f1502a pd78 f1503a pd78 f1504a pd78 f1505a pd78 f1506a pd78 f1507a pd78 f1508a flash memory (self-programming supported) 64 kb 96 kb 128 kb 64 kb 96 kb 128 kb 64 kb 96 kb 128 kb internal memory ram 4 kb 6kb 7kb 4 kb 6kb 7kb 4 kb 6kb 7kb memory space 1 mb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) 2 to 20 mhz: v dd = 2.7 to 5.5 v, 2 to 5 mhz: v dd = 1.8 to 5.5 v internal high-speed oscillation clock internal oscillation 1 mhz (typ.) or 8 mhz (typ.) selected by an option byte main system clock (oscillation frequency) 20 mhz internal high- speed oscillation clock internal oscillation 20 mhz (typ.) : v dd = 2.7 to 5.5 v subsystem clock (oscillation frequency) xt1 (crystal) oscillation 32.768 khz (typ.) internal low-speed oscillation clock (for wdt) internal oscillation 30 khz (typ.) general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) 0.05 s (high-speed system clock: f mx = 20 mhz operation) 0.125 s (internal high-speed oscillation clock: f ih = 8 mhz (typ.) operation) minimum instruction execution time 30.5 s (subsystem clock: f sub = 32.768 khz operation) instruction set ? 8-bit operation, 16-bit operation ? multiply (16 bits 16 bits) ? bit manipulation (set, reset, test, and boolean operation), etc. total 51 67 83 cmos 46 60 76 i/o n-ch ? 2 2 output cmos 1 1 1 i/o port input cmos 4 4 4 timer ? 16-bit timer: 12 channels ? watchdog timer: 1 channel ? real-time counter: 1 channel timer outputs 6 (pwm output: 5 (timer array unit 0)) 8 (pwm output: 7 (timer array unit 0)) 12 (pwm output: 7 (timer array unit 0), 3 (timer array unit 1)) rtc outputs 2 ? 1 hz (subsystem clock: f sub = 32.768 khz) ? 512 hz or 16.384 khz or 32.768 khz (subsystem clock: f sub = 32.768 khz) clock output/buzzer output 2 ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (peripheral hardware clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) a/d converter 12-bit resolution 8 channels 12-bit resolution 12 channels d/a converter 12-bit resolution 2 channels
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 20 jun 20, 2011 pd78f150xa (2/2) 78k0r/lf3 78k0r/lg3 78k0r/lh3 item pd78 f1500a pd78 f1501a pd78 f1502a pd78 f1503a pd78 f1504a pd78 f1505a pd78 f1506a pd78 f1507a pd78 f1508a operational amplifier 2 channels 3 channels voltage reference 2.0 v/2.5 v uart supporting lin-bus 1 csi/uart/ simplified i 2 c 2 csi/uart ? 1 ? csi (2 ch) /uart ? ? 1 serial interface multimaster i 2 c ? 1 lcd controller/driver internal voltage boosting method, capacitor split method, and exter nal resistance division method are switchable. segment signal output 31 (27) note 1 40 (36) note 1 54 (50) note 1 common signal output 4 (8) note 1 multiplier/divider 16 bits 16 bits = 32 bits (multiplication), 32 bits 32 bits = 32 bits, 32-bit remainder (division) dma controller 2 channels internal 30 33 33 vectored interrupt sources external 8 12 13 key interrupt ? key interrupt (intkr) occurs by detecting falling edge of the key input pins (kr0 to kr7). reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-clear ? internal reset by low-voltage detector ? internal reset by illegal instruction execution note 2 power-on-clear circuit ? power-on-reset: 1.61 0.09 v ? power-down-reset: 1.59 0.09 v v dd voltage detector 1.91 v to 4.22 v (16 stages) low-voltage detector exlvi voltage detector 1.21 v on-chip debug function bcd adjustment provided power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to +85 c package ? 80-pin plastic lqfp (14x14) ? 80-pin plastic lqfp (fine pitch) (12x12) 100-pin plastic lqfp (fine pitch) (14x14) 128-pin plastic lqfp (fine pitch) (14x20) notes 1. the values in parentheses are the number of signal outputs when 8com is used. 2. when instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circu it emulator or on-chip debug emulator.
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 21 jun 20, 2011 pd78f151xa (1/2) 78k0r/lf3 78k0r/lg3 78k0r/lh3 item pd78 f1500a pd78 f1502a pd78 f1503a pd78 f1505a pd78 f1506a pd78 f1508a flash memory (self-programming supported) 64 kb 128 kb 64 kb 128 kb 64 kb 128 kb internal memory ram 4 kb 7kb 4 kb 7kb 4 kb 7kb memory space 1 mb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) 2 to 20 mhz: v dd = 2.7 to 5.5 v, 2 to 5 mhz: v dd = 1.8 to 5.5 v internal high-speed oscillation clock internal oscillation 1 mhz (typ.) or 8 mhz (typ.) selected by an option byte main system clock (oscillation frequency) 20 mhz internal high- speed oscillation clock internal oscillation 20 mhz (typ.) : v dd = 2.7 to 5.5 v subsystem clock (oscillation frequency) xt1 (crystal) oscillation 32.768 khz (typ.) internal low-speed oscillation clock (for wdt) internal oscillation 30 khz (typ.) general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) 0.05 s (high-speed system clock: f mx = 20 mhz operation) 0.125 s (internal high-speed oscillation clock: f ih = 8 mhz (typ.) operation) minimum instruction execution time 30.5 s (subsystem clock: f sub = 32.768 khz operation) instruction set ? 8-bit operation, 16-bit operation ? multiply (16 bits 16 bits) ? bit manipulation (set, reset, test, and boolean operation), etc. total 51 67 83 cmos 46 60 76 i/o n-ch ? 2 2 output cmos 1 1 1 i/o port input cmos 4 4 4 timer ? 16-bit timer: 12 channels ? watchdog timer: 1 channel ? real-time counter: 1 channel timer outputs 6 (pwm output: 5 (timer array unit 0)) 8 (pwm output: 7 (timer array unit 0)) 12 (pwm output: 7 (timer array unit 0), 3 (timer array unit 1)) rtc outputs 2 ? 1 hz (subsystem clock: f sub = 32.768 khz) ? 512 hz or 16.384 khz or 32.768 khz (subsystem clock: f sub = 32.768 khz) clock output/buzzer output 2 ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (peripheral hardware clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) a/d converter 12-bit resolution 8 channels 12-bit resolution 12 channels
78k0r/lx3 chapter 1 outline r01uh0004ej0501 rev.5.01 22 jun 20, 2011 pd78f150xa (2/2) 78k0r/lf3 78k0r/lg3 78k0r/lh3 item pd78 f1500a pd78 f1502a pd78 f1503a pd78 f1505a pd78 f1506a pd78 f1508a uart supporting lin-bus 1 csi/uart/ simplified i 2 c 2 csi/uart ? 1 ? csi (2 ch) /uart ? ? 1 serial interface multimaster i 2 c ? 1 lcd controller/driver internal voltage boosting method, capacitor split method, and exter nal resistance division method are switchable. segment signal output 31 (27) note 1 40 (36) note 1 54 (50) note 1 common signal output 4 (8) note 1 multiplier/divider 16 bits 16 bits = 32 bits (multiplication), 32 bits 32 bits = 32 bits, 32-bit remainder (division) dma controller 2 channels internal 30 33 33 vectored interrupt sources external 8 12 13 key interrupt ? key interrupt (intkr) occurs by detecting falling edge of the key input pins (kr0 to kr7). reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-clear ? internal reset by low-voltage detector ? internal reset by illegal instruction execution note 2 power-on-clear circuit ? power-on-reset: 1.61 0.09 v ? power-down-reset: 1.59 0.09 v v dd voltage detector 1.91 v to 4.22 v (16 stages) low-voltage detector exlvi voltage detector 1.21 v on-chip debug function bcd adjustment provided power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to +85 c package ? 80-pin plastic lqfp (14x14) ? 80-pin plastic lqfp (fine pitch) (12x12) 100-pin plastic lqfp (fine pitch) (14x14) 128-pin plastic lqfp (fine pitch) (14x20) notes 1. the values in parentheses are the number of signal outputs when 8com is used. 2. when instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circu it emulator or on-chip debug emulator.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 23 jun 20, 2011 chapter 2 pin functions 2.1 pin function list there are four types of pin i/o buffer power supplies: av dd0 , av dd, av dd1 , ev dd1 , ev dd , and v dd . the relationship between these power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av dd0 , av dd p20 to p27, p150 to p152, p157 av dd1 , ev dd1 p110, p111 ev dd ? port pins other than p20 to p27, p110, p111, p150 to p152, p157 ? reset, flmd0 pins v dd pins other than port , reset, flmd0 pins
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 24 jun 20, 2011 2.1.1 78k0r/lf3 (1) port functions (1/2) : 78k0r/lf3 function name i/o function after reset alternate function p00 caph p01 capl p02 i/o port 0. 3-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port v lc3 p10 sck20/scl20 p11 si20/rxd2/sda20/ intp6 p12 so20/txd2/to02 p13 so10/txd1/to04 p14 si10/rxd1/sda10/ intp4 p15 i/o port 1. 6-bit i/o port. input/output can be specified in 1-bit units. input of p10, p11, p14 and p15 can be set to ttl buffer. output of p10 to p15 can be set to n-ch open-drain output (v dd tolerance). use of an on-chip pull-up resistor can be specified by a software setting. input port sck10/scl10/intp7 p20 ani0/amp0- note 1 p21 ani1/amp0o note 1 p22 ani2/amp0+ note 1 p23 ani3/amp1- note 1 p24 ani4/amp1o note 1 p25 ani5/amp1+ note 1 p26 i/o port 2. 7-bit i/o port. input/output can be specified in 1-bit units. digital input port ani6 p30 ti03/to00/rtc1hz/ intp1 p31 ti00/to03/rtcdiv/ rtccl/pclbuz1/ intp2 p32 ti01/to01/intp5/ pclbuz0 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti07/to07/intp3 p40 note 2 tool0 p41 i/o port 4. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port tool1 notes 1. ampxx applies to pd78f150xa only. 2. if on-chip debugging is enabled by using an option byte, be sure to pull up the p40/tool0 pin externally.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 25 jun 20, 2011 (1) port functions (2/2) : 78k0r/lf3 function name i/o function after reset alternate function p50 seg30/rxd3 p51 seg29/txd3 p52 seg28/ti02 p53 seg27/ti04 p54 to p57 i/o port 5. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg26 to seg23 p90 to p92 i/o port 9. 3-bit i/o port. inputs/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg22 to seg20 p100 i/o port 10. 1-bit i/o port. inputs/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg11 p110 ano0 note p111 i/o port 11. 2-bit i/o port. inputs/output can be specified in 1-bit units. input port ano1 note p120 i/o intp0/exlvi p121 x1 p122 x2/exclk p123 xt1 p124 input port 12. 1-bit i/o port and 4-bit input port. for only p120, input/output can be specified in 1-bit units. for only p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2 p130 output port 13. 1-bit output port. output port ? p140 to p147 i/o port 14. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg19 to seg12 p157 i/o port 15. 1-bit i/o port. input/output can be specified in 1-bit units. digital input port ani15/av refm note note anox and av refm apply to pd78f150xa only.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 26 jun 20, 2011 (2) non-port functions (1/4) : 78k0r/lf3 function name i/o function after reset alternate function ani0 p20/amp0- note 1 ani1 p21/amp0o note 1 ani2 p22/amp0+ note 1 ani3 p23/amp1- note 1 ani4 p24/amp1o note 1 ani5 p25/amp1+ note 1 ani6 p26 ani15 input a/d converter analog input digital input port p157/av refm note 1 amp0- note 1 p20/ani0 amp1- note 1 input operational amplifier input (negative side) digital input port p23/ani3 amp0+ note 1 p22/ani2 amp1+ note 1 input operational amplifie r input (positive side) digital input port p25/ani5 amp0o note 1 p21/ani1 amp1o note 1 output operational amplifier output digital input port p24/ani4 av refm note 1 analog negative reference voltage input digital input port p157/ani15 av refp note 1 v refout note 1 av ref note 2 input analog positive reference voltage input input ? v refout note 1 output analog reference voltage output input av refp note 1 ano0 note 1 p110 ano1 note 1 output d/a converter analog output input port p111 seg0 to seg3 com4 to com7 seg4 to seg10 ? seg11 p100 seg12 to seg19 p147 to p140 seg20 to seg22 p92 to p90 seg23 to seg26 p57 to p54 seg27 p53/ti04 seg28 p52/ti02 seg29 p51/txd3 seg30 output lcd controller/driver segment signal outputs output p50/rxd3 com0 to com3 ? com4 to com7 output lcd controller/driver common signal outputs output seg0 to seg3 v lc0 to v lc2 ? ? v lc3 ? lcd drive voltage input port p02 notes 1. ampxx, anox, av refp , av refm , and v refout apply to pd78f150xa only. 2. av ref applies to pd78f151xa only.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 27 jun 20, 2011 (2) non-port functions (2/4) : 78k0r/lf3 function name i/o function after reset alternate function caph p00 capl ? connecting a capacitor for lcd controller/driver input port p01 exlvi input potential input for external low-voltage detection input port p120/intp0 intp0 p120/exlvi intp1 p30/ti03/to00/ rtc1hz intp2 p31/ti00/to03/ rtcdiv/rtccl/ pclbuz1 intp3 p33/ti07/to07 intp4 p14/si10/rxd1/ sda10 intp5 p32/ti01/to01/ pclbuz0 intp6 p11/si20/rxd2/ sda20 intp7 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input port p15/sck10/scl10 pclbuz0 p32/ti01/to01/ intp5 pclbuz1 output clock output/buzzer output input port p31/ti00/to03/ rtcdiv/rtccl/intp2 regc ? connecting regulator output (2.4 v) stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 to 1 f). ? ? rtcdiv output real-time counter clock ( 32 khz divided frequency) output input port p31/ti00/to03/ pclbuz1/rtccl/ intp2 rtccl output real-time counter clock (32 khz original oscillation) output input port p31/ti00/to03/ pclbuz1/rtcdiv/ intp2 rtc1hz output real-time counter correction clock (1 hz) output input port p30/ti03/to00/ intp1 reset input system reset input ? ? rxd1 serial data input to uart1 p14/si10/sda10/ intp4 rxd2 serial data input to uart2 p11/si20/sda20/ intp6 rxd3 input serial data input to uart3 input port p50/seg30 sck10 clock input/output for csi10 p15/scl10/intp7 sck20 i/o clock input/output for csi20 input port p10/scl20 scl10 p15/sck10/intp7 scl20 i/o clock input/output for simplified i 2 c input port p10/sck20
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 28 jun 20, 2011 (2) non-port functions (3/4) : 78k0r/lf3 function name i/o function after reset alternate function sda10 p14/si10/rxd1/ intp4 sda20 serial data i/o for simplified i 2 c p11/si20/rxd2/ intp6 si10 serial data input to csi10 p14/rxd1/sda10/ intp4 si20 i/o serial data input to csi20 input port p11/rxd2/sda20/ intp6 so10 serial data output from csi10 p13/txd1/to04 so20 output serial data output from csi20 input port p12/txd2/to02 ti00 external count clock input to 16-bit timer 00 p31/to03/rtcdiv/ rtccl/pclbuz1/ intp2 ti01 external count clock input to 16-bit timer 01 p32/to01/intp5/ pclbuz0 ti02 external count clock input to 16-bit timer 02 p52/seg28 ti03 external count clock input to 16-bit timer 03 p30/to00/rtc1hz/ intp1 ti04 external count clock input to 16-bit timer 04 p53/seg27 ti07 input external count clock input to 16-bit timer 07 input port p33/to07/intp3 to00 16-bit timer 00 output p30/ti03/rtc1hz/ intp1 to01 16-bit timer 01 output p32/ti01/intp5/ pclbuz0 to02 16-bit timer 02 output p12/so20/txd2 to03 16-bit timer 03 output p31/ti00/rtcdiv/ rtccl/pclbuz1/ intp2 to04 16-bit timer 04 output p13/so10/txd1 to07 output 16-bit timer 07 output input port p33/ti07/intp3 txd1 serial data output from uart1 p13/so10/to04 txd2 serial data output from uart2 p12/so20/to02 txd3 output serial data output from uart3 input port p51/seg29 x1 ? input port p121 x2 ? resonator connection for main system clock input port p122/exclk exclk input external clock input for ma in system clock input port p122/x2 xt1 ? input port p123 xt2 ? resonator connection for subsystem clock input port p124 v dd ? positive power supply (pins other than port and reset, flmd0 pins) ? ? ev dd ? positive power supply for reset , flmd0 pins, and port pins other than p20 to p26, p110, p111, p157 ? ?
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 29 jun 20, 2011 (2) non-port functions (4/4) : 78k0r/lf3 function name i/o function after reset alternate function av dd note 1 av dd note 2 ? positive power supply for p20 to p26, p157 ? ? av dd1 note 1 ev dd1 note 2 ? positive power supply for p110, p111 ? ? v ss ? ground potential (pins other than port and reset, flmd0 pins) ? ? ev ss ? ground potential for reset, flmd0 pins, and port pins other than p20 to p26, p110, p111, p157 ? ? av ss ? ground potential for p20 to p26, p110, p111, p157 ? ? flmd0 ? flash memory programming mode setting ? ? tool0 i/o data i/o for flash memory programmer/debugger input port p40 tool1 output clock output for debugger input port p41 notes 1. av dd0 and av dd1 apply to pd78f150xa only. 2. av dd and ev dd1 apply to pd78f151xa only.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 30 jun 20, 2011 2.1.2 78k0r/lg3 (1) port functions (1/2) : 78k0r/lg3 function name i/o function after reset alternate function p00 caph p01 capl p02 i/o port 0. 3-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port v lc3 p10 sck20/scl20 p11 si20/rxd2/sda20/ intp6 p12 so20/txd2/to02 p13 so10/txd1/to04 p14 si10/rxd1/sda10/ intp4 p15 sck10/scl10/intp7 p16 i/o port 1. 7-bit i/o port. input/output can be specified in 1-bit units. input of p10, p11, p14 and p15 can be set to ttl buffer. output of p10 to p15 can be set to n-ch open-drain output (v dd tolerance). use of an on-chip pull-up resistor can be specified by a software setting. input port ti05/to05/intp10 p20 ani0/amp0- note 1 p21 ani1/amp0o note 1 p22 ani2/amp0+ note 1 p23 ani3/amp1- note 1 p24 ani4/amp1o note 1 p25 ani5/amp1+ note 1 p26 ani6/amp2- note 1 p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. digital input port ani7/amp2o note 1 p30 ti03/to00/rtc1hz/ intp1 p31 ti00/to03/rtcdiv/ rtccl/pclbuz1/ intp2 p32 ti01/to01/intp5/ pclbuz0 p33 ti07/to07/intp3 p34 i/o port 3. 5-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti06/to06/intp8 p40 note 2 tool0 p41 i/o port 4. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port tool1 notes 1. ampxx applies to pd78f150xa only. 2. if on-chip debugging is enabled by using an option byte, be sure to pull up the p40/tool0 pin externally.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 31 jun 20, 2011 (1) port functions (2/2) : 78k0r/lg3 function name i/o function after reset alternate function p50 seg39/rxd3 p51 seg38/txd3 p52 seg37/ti02 p53 seg36/ti04 p54 to p57 i/o port 5. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg35 to seg32 p60 scl0 p61 i/o port 6. 2-bit i/o port. output is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port sda0 p80 sck00/intp11 p81 rxd0/si00/intp9 p82 i/o port 8. 3-bit i/o port. inputs/output can be specified in 1-bit units. output of p80 and p82 can be set to n-ch open-drain output (v dd tolerance). use of an on-chip pull-up resistor can be specified by a software setting. input port txd0/so00 p90 to p97 i/o port 9. 8-bit i/o port. inputs/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg31 to seg24 p100 i/o port 10. 1-bit i/o port. inputs/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg15 p110 ano0 note p111 i/o port 11. 2-bit i/o port. inputs/output can be specified in 1-bit units. input port ano1 note p120 i/o intp0/exlvi p121 x1 p122 x2/exclk p123 xt1 p124 input port 12. 1-bit i/o port and 4-bit input port. for only p120, input/output can be specified in 1-bit units. for only p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2 p130 output port 13. 1-bit output port. output port ? p140 to p147 i/o port 14. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg23 to seg16 p150 ani8/amp2+ p151 ani9 p152 ani10 p157 i/o port 15. 4-bit i/o port. input/output can be specified in 1-bit units. digital input port ani15/av refm note note anox and av refm apply to pd78f150xa only.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 32 jun 20, 2011 (2) non-port functions (1/4) : 78k0r/lg3 function name i/o function after reset alternate function ani0 p20/amp0- note 1 ani1 p21/amp0o note 1 ani2 p22/amp0+ note 1 ani3 p23/amp1- note 1 ani4 p24/amp1o note 1 ani5 p25/amp1+ note 1 ani6 p26/amp2- note 1 ani7 p27/amp2o note 1 ani8 p150/amp2+ note 1 ani9 p151 ani10 p152 ani15 input a/d converter analog input digital input port p157/av refm note 1 amp0- note 1 p20/ani0 amp1- note 1 p23/ani3 amp2- note 1 input operational amplifier input (negative side) digital input port p26/ani6 amp0+ note 1 p22/ani2 amp1+ note 1 p25/ani5 amp2+ note 1 input operational amplifie r input (positive side) digital input port p150/ani8 amp0o note 1 p21/ani1 amp1o note 1 p24/ani4 amp2o note 1 output operational amplifier output digital input port p27/ani7 av refm note 1 analog negative reference voltage input digital input port p157/ani15 av refp note 1 v refout note 1 av ref note 2 input analog positive reference voltage input input ? v refout note 1 output analog reference voltage output input av refp note 1 ano0 note 1 p110 ano1 note 1 output d/a converter analog output input port p111 seg0 to seg3 com4 to com7 seg4 to seg14 output ? seg15 p100 seg16 to seg23 p147 to p140 seg24 to seg31 p97 to p90 seg32 to seg35 p57 to p54 seg36 p53/ti04 seg37 p52/ti02 seg38 p51/txd3 seg39 output lcd controller/driver segment signal outputs input port p50/rxd3 notes 1. ampxx, anox, av refp , av refm , and v refout apply to pd78f150xa only. 2. am ref applies to pd78f151xa only.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 33 jun 20, 2011 (2) non-port functions (2/4) : 78k0r/lg3 function name i/o function after reset alternate function com0 to com3 ? com4 to com7 output lcd controller/driver common signal outputs output seg0 to seg3 v lc0 to v lc2 ? ? v lc3 ? lcd drive voltage input port p02 caph p00 capl ? connecting a capacitor for lcd controller/driver input port p01 exlvi input potential input for external low-voltage detection input port p120/intp0 intp0 p120/exlvi intp1 p30/ti03/to00/ rtc1hz intp2 p31/ti00/to03/ rtcdiv/rtccl/ pclbuz1 intp3 p33/ti07/to07 intp4 p14/si10/rxd1/ sda10 intp5 p32/ti01/to01/ pclbuz0 intp6 p11/si20/rxd2/ sda20 intp7 p15/sck10/scl10 intp8 p34/ti06/to06 intp9 p81/rxd0/si00 intp10 p16/ti05/to05 intp11 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input port p80/sck00 pclbuz0 p32/ti01/to01/ intp5 pclbuz1 output clock output/buzzer output input port p31/ti00/to03/ rtcdiv/rtccl/intp2 regc ? connecting regulator output (2.4 v) stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 to 1 f). ? ? rtcdiv output real-time counter clock ( 32 khz divided frequency) output input port p31/ti00/to03/ pclbuz1/rtccl/ intp2 rtccl output real-time counter clock (32 khz original oscillation) output input port p31/ti00/to03/ pclbuz1/rtcdiv/ intp2 rtc1hz output real-time counter correction clock (1 hz) output input port p30/ti03/to00/ intp1 reset input system reset input ? ?
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 34 jun 20, 2011 (2) non-port functions (3/4) : 78k0r/lg3 function name i/o function after reset alternate function rxd0 serial data input to uart0 p81/si00/intp9 rxd1 serial data input to uart1 p14/si10/sda10/ intp4 rxd2 serial data input to uart2 p11/si20/sda20/ intp6 rxd3 input serial data input to uart3 input port p50/seg39 sck00 clock input/output for csi00 p80/intp11 sck10 clock input/output for csi10 p15/scl10/intp7 sck20 i/o clock input/output for csi20 input port p10/scl20 scl0 i/o clock input/output for i 2 c input port p60 scl10 p15/sck10/intp7 scl20 i/o clock input/output for simplified i 2 c input port p10/sck20 sda0 i/o serial data i/o for i 2 c input port p61 sda10 p14/si10/rxd1/ intp4 sda20 i/o serial data i/o for simplified i 2 c input port p11/si20/rxd2/ intp6 si00 serial data input to csi00 p81/rxd0/intp9 si10 serial data input to csi10 p14/rxd1/sda10/ intp4 si20 input serial data input to csi20 input port p11/rxd2/sda20/ intp6 so00 serial data output from csi00 p82/txd0 so10 serial data output from csi10 p13/txd1/to04 so20 output serial data output from csi20 input port p12/txd2/to02 ti00 external count clock input to 16-bit timer 00 p31/to03/rtcdiv/ rtccl/pclbuz1/ intp2 ti01 external count clock input to 16-bit timer 01 p32/to01/intp5/ pclbuz0 ti02 external count clock input to 16-bit timer 02 p52/seg37 ti03 external count clock input to 16-bit timer 03 p30/to00/rtc1hz/ intp1 ti04 external count clock input to 16-bit timer 04 p53/seg36 ti05 external count clock input to 16-bit timer 05 p16/to05/intp10 ti06 external count clock input to 16-bit timer 06 p34/to06/intp8 ti07 input external count clock input to 16-bit timer 07 input port p33/to07/intp3
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 35 jun 20, 2011 (2) non-port functions (4/4) : 78k0r/lg3 function name i/o function after reset alternate function to00 16-bit timer 00 output p30/ti03/rtc1hz/ intp1 to01 16-bit timer 01 output p32/ti01/intp5/ pclbuz0 to02 16-bit timer 02 output p12/so20/txd2 to03 16-bit timer 03 output p31/ti00/rtcdiv/ rtccl/pclbuz1/ intp2 to04 16-bit timer 04 output p13/so10/txd1 to05 16-bit timer 05 output p16/ti05/intp10 to06 16-bit timer 06 output p34/ti06/intp8 to07 output 16-bit timer 07 output input port p33/ti07/intp3 txd0 serial data output from uart0 p82/so00 txd1 serial data output from uart1 p13/so10/to04 txd2 serial data output from uart2 p12/so20/to02 txd3 output serial data output from uart3 input port p51/seg38 x1 ? input port p121 x2 ? resonator connection for main system clock input port p122/exclk exclk input external clock input for ma in system clock input port p122/x2 xt1 ? input port p123 xt2 ? resonator connection for subsystem clock input port p124 v dd ? positive power supply (pins other than port and reset, flmd0 pins) ? ? ev dd ? positive power supply for reset , flmd0 pins, and port pins other than p20 to p27, p110, p111, p150 to p152, p157 ? ? av dd note 1 av dd note 2 ? positive power supply for p20 to p27, p150 to p152, p157 ? ? av dd1 note 1 ev dd1 note 2 ? positive power supply for p110, p111 ? ? v ss ? ground potential (pins other than port and reset, flmd0 pins) ? ? ev ss ? ground potential for reset, flmd0 pins, and port pins other than p20 to p27, p110, p111, p150 to p152, p157 ? ? av ss ? ground potential for p20 to p27, p110, p111, p150 to p152, p157 ? ? flmd0 ? flash memory programming mode setting ? ? tool0 i/o data i/o for flash memory programmer/debugger input port p40 tool1 output clock output for debugger input port p41 notes 1. av dd0 and av dd1 apply to pd78f150xa only. 2. av dd and ev dd1 apply to pd78f151xa only.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 36 jun 20, 2011 2.1.3 78k0r/lh3 (1) port functions (1/3) : 78k0r/lh3 function name i/o function after reset alternate function p00 caph p01 capl p02 i/o port 0. 3-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port v lc3 p10 sck20/scl20 p11 si20/rxd2/sda20/ intp6 p12 so20/txd2/to02 p13 so10/txd1/to04 p14 si10/rxd1/sda10/ intp4 p15 sck10/scl10/intp7 p16 ti05/to05/intp10 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. input of p10, p11, p14 and p15 can be set to ttl buffer. output of p10 to p15 can be set to n-ch open-drain output (v dd tolerance). use of an on-chip pull-up resistor can be specified by a software setting. input port ? p20 ani0/amp0- note 1 p21 ani1/amp0o note 1 p22 ani2/amp0+ note 1 p23 ani3/amp1- note 1 p24 ani4/amp1o note p25 ani5/amp1+ note 1 p26 ani6/amp2- note 1 p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. digital input port ani7/amp2o note 1 p30 ti03/to00/rtc1hz/ intp1 p31 ti00/to03/rtcdiv/ rtccl/pclbuz1/ intp2 p32 ti01/to01/intp5/ pclbuz0 p33 ti07/to07/intp3 p34 i/o port 3. 5-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti06/to06/intp8 p40 note 2 tool0 p41 i/o port 4. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port tool1 notes 1. ampxx applies to pd78f150xa only. 2. if on-chip debugging is enabled by using an option byte, be sure to pull up the p40/tool0 pin externally.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 37 jun 20, 2011 (1) port functions (2/3) : 78k0r/lh3 function name i/o function after reset alternate function p50 seg53/rxd3 p51 seg52/txd3 p52 seg51/ti02 p53 seg50/ti04 p54 to p57 i/o port 5. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg49 to seg46 p60 scl0 p61 i/o port 6. 2-bit i/o port. output is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port sda0 p70 to p74 kr0 to kr4 p75 kr5/sck01 p76 kr6/si01 p77 i/o port 7. 8-bit i/o port. input/output can be specified in 1-bit units. input of p75 and p76 can be set to ttl buffer. output of p75 and p77 can be set to n-ch open-drain output (v dd tolerance). use of an on-chip pull-up resistor can be specified by a software setting. input port kr7/so01 p80 sck00/intp11 p81 rxd0/si00/intp9 p82 txd0/so00 p83 ? p84 ti10/to10 p85 ti11/to11 p86 ti12/to12 p87 i/o port 8. 8-bit i/o port. inputs/output can be specified in 1-bit units. output of p80 and p82 can be set to n-ch open-drain output (v dd tolerance). use of an on-chip pull-up resistor can be specified by a software setting. input port ti13/to13 p90 to p97 i/o port 9. 8-bit i/o port. inputs/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg45 to seg38 p100 to p102 i/o port 10. 3-bit i/o port. inputs/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg29 to seg27 p110 ano0 note p111 i/o port 11. 2-bit i/o port. inputs/output can be specified in 1-bit units. input port ano1 note p120 i/o intp0/exlvi p121 x1 p122 x2/exclk p123 xt1 p124 input port 12. 1-bit i/o port and 4-bit input port. for only p120, input/output can be specified in 1-bit units. for only p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2 p130 output port 13. 1-bit output port. output port ? note anox applies to pd78f150xa only.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 38 jun 20, 2011 (1) port functions (3/3) : 78k0r/lh3 function name i/o function after reset alternate function p140 to p147 i/o port 14. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg37 to seg30 p150 ani8/amp2+ note p151 ani9 p152 ani10 p157 i/o port 15. 4-bit i/o port. input/output can be specified in 1-bit units. digital input port ani15/av refm note note amp2+ and av refm apply to pd78f150xa only. (2) non-port functions (1/5) : 78k0r/lh3 function name i/o function after reset alternate function ani0 p20/amp0- note 1 ani1 p21/amp0o note 1 ani2 p22/amp0+ note 1 ani3 p23/amp1- note 1 ani4 p24/amp1o note 1 ani5 p25/amp1+ note 1 ani6 p26/amp2- note 1 ani7 p27/amp2o note 1 ani8 p150/amp2+ note 1 ani9 p151 ani10 p152 ani15 input a/d converter analog input digital input port p157/av refm note 1 amp0- note 1 p20/ani0 amp1- note 1 p23/ani3 amp2- note 1 input operational amplifier input (negative side) digital input port p26/ani6 amp0+ note 1 p22/ani2 amp1+ note 1 p25/ani5 amp2+ note 1 input operational amplifie r input (positive side) digital input port p150/ani8 amp0o note 1 p21/ani1 amp1o note 1 p24/ani4 amp2o note 1 output operational amplifier output digital input port p27/ani7 av refm note 1 analog negative reference voltage input digital input port p157/ani15 av refp note 1 v refout note 1 av ref note 2 input analog positive reference voltage input input ? v refout note 1 output analog reference voltage output input av refp note 1 ano0 note 1 p110 ano1 note 1 output d/a converter analog output input port p111 notes 1. ampxx, anox, av refp , av refm , and av refout apply to pd78f150xa only. 2. av ref applies to pd78f151xa only.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 39 jun 20, 2011 (2) non-port functions (2/5) : 78k0r/lh3 function name i/o function after reset alternate function seg0 to seg3 com4 to com7 seg4 to seg26 ? seg27 to seg29 p102 to p100 seg30 to seg37 p147 to p140 seg38 to seg45 p97 to p90 seg46 to seg49 p57 to p54 seg50 p53/ti04 seg51 p52/ti02 seg52 p51/txd3 seg53 output lcd controller/driver segment signal outputs output p50/rxd3 com0 to com3 ? com4 to com7 output lcd controller/driver common signal outputs output seg0 to seg3 v lc0 to v lc2 ? ? v lc3 ? lcd drive voltage input port p02 caph p00 capl ? connecting a capacitor for lcd controller/driver input port p01 exlvi input potential input for external low-voltage detection input port p120/intp0 intp0 p120/exlvi intp1 p30/ti03/to00/ rtc1hz intp2 p31/ti00/to03/ rtcdiv/rtccl/ pclbuz1 intp3 p33/ti07/to07 intp4 p14/si10/rxd1/ sda10 intp5 p32/ti01/to01/ pclbuz0 intp6 p11/si20/rxd2/ sda20 intp7 p15/sck10/scl10 intp8 p34/ti06/to06 intp9 p81/rxd0/si00 intp10 p16/ti05/to05 intp11 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input port p80/sck00
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 40 jun 20, 2011 (2) non-port functions (3/5) : 78k0r/lh3 function name i/o function after reset alternate function kr0 to kr4 p70-p74 kr5 p75/sck01 kr6 p76/si01 kr7 input key interrupt input input port p77/so01 pclbuz0 p32/ti01/to01/ intp5 pclbuz1 output clock output/buzzer output input port p31/ti00/to03/ rtcdiv/rtccl/intp2 regc ? connecting regulator output (2.4 v) stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 to 1 f). ? ? rtcdiv output real-time counter clock ( 32 khz divided frequency) output input port p31/ti00/to03/ pclbuz1/rtccl/ intp2 rtccl output real-time counter clock (32 khz original oscillation) output input port p31/ti00/to03/ pclbuz1/rtcdiv/ intp2 rtc1hz output real-time counter correction clock (1 hz) output input port p30/ti03/to00/ intp1 reset input system reset input ? ? rxd0 serial data input to uart0 p81/si00/intp9 rxd1 serial data input to uart1 p14/si10/sda10/ intp4 rxd2 serial data input to uart2 p11/si20/sda20/ intp6 rxd3 input serial data input to uart3 input port p50/seg53 sck00 clock input/output for csi00 p80/intp11 sck01 clock input/output for csi01 p75/kr5 sck10 clock input/output for csi10 p15/scl10/intp7 sck20 i/o clock input/output for csi20 input port p10/scl20 scl0 i/o clock input/output for i 2 c input port p60 scl10 p15/sck10/intp7 scl20 i/o clock input/output for simplified i 2 c input port p10/sck20 sda0 i/o serial data i/o for i 2 c input port p61 sda10 p14/si10/rxd1/ intp4 sda20 i/o serial data i/o for simplified i 2 c input port p11/si20/rxd2/ intp6
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 41 jun 20, 2011 (2) non-port functions (4/5) : 78k0r/lh3 function name i/o function after reset alternate function si00 serial data input to csi00 p81/rxd0/intp9 si01 serial data input to csi01 p76/kr6 si10 serial data input to csi10 p14/rxd1/sda10/ intp4 si20 input serial data input to csi20 input port p11/rxd2/sda20/ intp6 so00 serial data output from csi00 p82/txd0 so01 serial data output from csi01 p77/kr7 so10 serial data output from csi10 p13/txd1/to04 so20 output serial data output from csi20 input port p12/txd2/to02 ti00 external count clock input to 16-bit timer 00 p31/to03/rtcdiv/ rtccl/pclbuz1/ intp2 ti01 external count clock input to 16-bit timer 01 p32/to01/intp5/ pclbuz0 ti02 external count clock input to 16-bit timer 02 p52/seg51 ti03 external count clock input to 16-bit timer 03 p30/to00/rtc1hz/ intp1 ti04 external count clock input to 16-bit timer 04 p53/seg50 ti05 external count clock input to 16-bit timer 05 p16/to05/intp10 ti06 external count clock input to 16-bit timer 06 p34/to06/intp8 ti07 external count clock input to 16-bit timer 07 p33/to07/intp3 ti10 external count clock input to 16-bit timer 10 p84/to10 ti11 external count clock input to 16-bit timer 11 p85/to11 ti12 external count clock input to 16-bit timer 12 p86/to12 ti13 input external count clock input to 16-bit timer 13 input port p87/to13 to00 16-bit timer 00 output p30/ti03/rtc1hz/ intp1 to01 16-bit timer 01 output p32/ti01/intp5/ pclbuz0 to02 16-bit timer 02 output p12/so20/txd2 to03 16-bit timer 03 output p31/ti00/rtcdiv/ rtccl/pclbuz1/ intp2 to04 16-bit timer 04 output p13/so10/txd1 to05 16-bit timer 05 output p16/ti05/intp10 to06 16-bit timer 06 output p34/ti06/intp8 to07 output 16-bit timer 07 output input port p33/ti07/intp3
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 42 jun 20, 2011 (2) non-port functions (5/5) : 78k0r/lh3 function name i/o function after reset alternate function to10 16-bit timer 10 output p84/ti10 to11 16-bit timer 11 output p85/ti11 to12 16-bit timer 12 output p86/ti12 to13 output 16-bit timer 13 output input port p87/ti13 txd0 serial data output from uart0 p82/so00 txd1 serial data output from uart1 p13/so10/to04 txd2 serial data output from uart2 p12/so20/to02 txd3 output serial data output from uart3 input port p51/seg52 x1 ? input port p121 x2 ? resonator connection for main system clock input port p122/exclk exclk input external clock input for ma in system clock input port p122/x2 xt1 ? input port p123 xt2 ? resonator connection for subsystem clock input port p124 v dd ? positive power supply (pins other than port and reset, flmd0 pins) ? ? ev dd ? positive power supply for reset , flmd0 pins, and port pins other than p20 to p27, p110, p111, p150 to p152, p157 ? ? av dd , note 1 av dd note 2 ? positive power supply for p20 to p27, p150 to p152, p157 ? ? av dd1 note 1 ev dd1 note 2 ? positive power supply for p110, p111 ? ? v ss ? ground potential (pins other than port and reset, flmd0 pins) ? ? ev ss ? ground potential for reset, flmd0 pins, and port pins other than p20 to p27, p110, p111, p150 to p152, p157 ? ? av ss ? ground potential for p20 to p27, p110, p111, p150 to p152, p157 ? ? flmd0 ? flash memory programming mode setting ? ? tool0 i/o data i/o for flash memory programmer/debugger input port p40 tool1 output clock output for debugger input port p41 notes 1. av dd0 and av dd1 apply to pd78f150xa only. 2. av dd and ev dd1 apply to pd78f151xa only.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 43 jun 20, 2011 2.2 description of pin functions remark the pins mounted depend on the product. refer to 1.3 pin configuration (top view) and 2.1 pin function list . 2.2.1 p00 to p02 p00 to p02 function as an i/o port. this port can also be us ed for connecting a capacitor for lcd controller/driver, and power supply voltage pin for driving the lcd. 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p00/caph p01/capl p02/v lc3 the following operation modes can be specified in 1-bit units. (1) port mode p00 to p02 function as an i/o port. p00 to p02 can be set to input or output port in 1-bit units using port mode register 0 (pm0). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). (2) control mode p00 to p02 function as connecting a capacitor for lcd contro ller/driver, and power supply voltage pin for driving the lcd. (a) caph, capl these are the pins for connecting a capacitor for lcd controller/driver. (b) v lc3 this is the pin for inputting a power supply voltage pin for driving the lcd. caution to use p00/caph, p01/capl, and p02/v lc3 as a general-purpose port, set bit 5 (mdset1) and bit 4 (mdset0) of lcd mode register (lcdmd) to ?0?, which is the same as their default status setting.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 44 jun 20, 2011 2.2.2 p10 to p17 p10 to p17 function as an i/o port. this port can also be us ed for external interrupt request input, serial interface data i/o, clock i/o, and timer i/o. input to the p10, p11, p14, and p15 pins can be specified through a normal input buffer or a ttl input buffer in 1-bit units using port input mode register 1 (pim1). output from the p10-p15 pins can be specified as n-ch open-drain output (v dd tolerance) in 1-bit units using port output mode register 1 (pom1). 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p10/sck20/scl20 p11/si20/rxd2/sda20/intp6 p12/so20/txd2/to02 p13/so10/txd1/to04 p14/si10/rxd1/sda10/intp4 p15/sck10/scl10/intp7 p16/ti05/to05/intp10 ? p17 ? ? the following operation modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an i/o port. p10 to p17 can be set to input or output port in 1-bit units using port mode register 1 (pm1). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). (2) control mode p10 to p17 function as serial interface clock i/o, data i/o, timer i/o, and exter nal interrupt request input. (a) sck10, sck20 these are serial clock i/o pin of se rial interface csi10 and csi20. (b) si10, si20 these are serial data input pin of serial interface csi10 and csi20. (c) so10, so20 these are serial data output pin of serial interface csi10 and csi20. (d) scl10, scl20 these are serial clock i/o pin of serial interface iic10 and iic20 (simplified i 2 c). (e) sda10, sda20 these are serial data i/o pin of serial interface iic10 and iic20 (simplified i 2 c). (f) rxd1, rxd2 these are serial data input pin of serial interface uart1 and uart2.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 45 jun 20, 2011 (g) txd1, txd2 these are serial data output pin of serial interface uart1 and uart2. (h) ti05 this is a timer input pin of 16-bit timer 05. (i) to02, to04, to05 these are the timer output pins of 16-bit timers 02, 04, and 05. (j) intp4, intp6, intp7, intp10 these are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. cautions 1. to use p10/sck20/scl2 0 and p11/si20/rxd2/sda20/intp6 as a general-purpose port, note the serial array unit 1 setting. for de tails, refer to table 14-9 relati onship between register settings and pins (channel 0 of unit 1: csi20, uart2 reception, iic20). 2. to use p12/to02/so20/txd2 as a general-purpose port, set bit 2 (to02) of timer output register 0 (to0) and bit 2 (toe02) of timer output enable re gister 0 (toe0) to ?0?, which is the same as their default status setting. and as a general-pur pose port, note the serial array unit 1 setting. for details of serial array unit 1 setting, refer to table 14-9 relationship between register settings and pins (channel 0 of unit 1: csi20, uart2 reception, iic20). 3. to use p13/to04/so10/txd1 as a general-purpose port, set bit 4 (to04) of timer output register 0 (to0) and bit 4 (toe04) of timer output enable re gister 0 (toe0) to ?0?, which is the same as their default status setting. and as a general-pur pose port, note the serial array unit 0 setting. for details of serial array unit 0 setting, refer to table 14-7 relationship between register settings and pins (channel 2 of unit 0: csi10, uart1 transmission, iic10) 4. to use p14/si10/rxd1/sda10/intp4 and p15/ sck10/scl10/intp7 as a general-purpose port, note the serial array unit 0 setting. for details, refer to table 14- 7 relationship between register settings and pins (channel 2 of unit 0: csi10, uart1 transmission, iic10) 5. to use p16/to05/ti05/intp10 as a general-purpose po rt, set bit 5 (to05) of timer output register 0 (to0) and bit 5 (toe05) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 46 jun 20, 2011 2.2.3 p20 to p27 p20 to p27 function as an i/o port. this port can also be us ed for a/d converter analog i nput, and operatio nal amplifier i/o. pd78f150xa pd78f151xa 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) p20/ani0/amp0- p20/ani0 p21/ani1/amp0o p20/ani1 p22/ani2/amp0+ p20/ani2 p23/ani3/amp1- p20/ani3 p24/ani4/amp1o p20/ani4 p25/ani5/amp1+ p20/ani5 p26/ani6/amp2- p26/ani6 p26/ani6 p27/ani7/amp2o ? ? p27/ani7 the following operation modes can be specified in 1-bit units. (1) port mode p20 to p27 function as an i/o port. p20 to p27 can be set to input or output port in 1-bit units using port mode register 2 (pm2). (2) control mode p20 to p27 function as a/d converter analog input and operational amplifier i/o. (a) ani0 to ani7 these are a/d converter analog input pins. (b) amp0-, amp1-, amp2- these are pins that the input voltage on the negative side of operational amplifiers 0 to 2. (c) amp0+, amp1+ these are pins that the input voltage on the positive side of oper ational amplifiers 0 and 1. (d) amp0o, amp1o, amp2o these are operational amplif iers 0 to 2 output pins. cautions 1. p20/ani0/amp0- to p27/ ani7/anp2o are set in the digital in put (general-purpose port) mode after release of reset. 2. when using at least one port of ports p20/ani0/amp0- to p 27/ani7/anp2o as a digital port, set av dd0 to the same potential as ev dd or v dd .
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 47 jun 20, 2011 2.2.4 p30 to p34 p30 to p34 function as an i/o port. this port can also be used for timer i/o, real -time counter clock output, correction clock output, clock output/buzzer output, a nd external interrupt request input. 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p30/ti03/to00/rtc1hz/intp1 p31/ti00/to03/rtcdiv/rtccl/ pclbuz1/intp2 p32/ti01/to01/pclbuz0/intp5 p33/ti07/to07/ intp3 p34/ti06/to06/ intp8 ? the following operation modes can be specified in 1-bit units. (1) port mode p30 to p34 function as an i/o port. p30 to p34 can be set to input or output port in 1-bit units using port mode register 3 (pm3). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). (2) control mode p30 to p34 function as timer i/o, real-time counter clo ck output, correction clock outpu t, clock output/buzzer output, and external interrupt request input. (a) ti00, ti01, ti03 ti06, ti07 these are the timer input pins of 16-bit timers 00, 01, 03, 06, and 07. (b) to00, to01, to03, to06, to07 these are the timer output pins of 16-bit timers 00, 01, 03, 06, and 07. (c) rtccl this is a real-time counter clock (32 kh z, original oscillation) output pin. (d) rtcdiv this is a real-time counter clo ck (32 khz, divided) output pin. (e) rtc1hz this is a real-time counter correction clock (1 hz) output pin. (f) pclbuz0, pclbuz1 these are clock output/buzzer output pins. (g) intp1, intp2, intp3, intp5, intp8 these are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 48 jun 20, 2011 cautions 1. to use p30/to00/ti03/rt c1hz/intp1 as a general-purpose port, set bit 5 (rcloe1) of real-time counter control register 0 (rtcc0), bit 0 (to00) of timer output register 0 (to0) and bit 0 (toe00) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting. 2. to use p31/to03/ti00/rtcdi v/rtccl/pclbuz1/intp2 as a general-purpose port, set bit 4 (rcloe0) of real-time counter control register 0 (rtcc0), bit 6 (rcloe2) of real-time counter control register 2 (rtcc2), bit 3 (to03) of timer output register 0 (to0), bit 3 (toe03) of timer output enable register 0 (toe0) and bit 7 of clock output select register 1 (cks1) to ?0?, which is the same as their default status setting. 3. to use p32/to01/ti01/intp5/pcl buz0 as a general-purpose port, set bit 1 (to01) of timer output register 0 (to0), bit 1 (toe01) of timer output en able register 0 (toe0) and bit 7 of clock output select register 0 (cks0) to ?0?, which is the same as their default status setting. 4. to use p33/to07/ti07/intp3 and p34/to06/ti06/intp8 as a gene ral-purpose port, set bit 7, 6 (to07, to06) of timer output regist er 0 (to0), and bit 7, 6 (toe07, toe06) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting. 2.2.5 p40, p41 p40 and p41 function as an i/o port. these pins also function as data i/o for a flash memory programmer/debugger and clock output for a debugger. 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p40/tool0 p41/tool1 the following operation modes can be specified in 1-bit units. (1) port mode p40 and p41 function as an i/o port. p 40 and p41 can be set to in put or output port in 1- bit units using port mode register 4 (pm4). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (pu4). be sure to connect an external pull-up resistor to p40 when on-chip debugging is enabled (by using an option byte). (2) control mode p40 and p41 function as data i/o for a flash memory programmer/debugger and clock output for a debugger. (a) tool0 this is a data i/o pin for a flash memory programmer/debugger. be sure to pull up this pin externally when on-chip debugging is enabled (pulling it down is prohibited).
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 49 jun 20, 2011 (b) tool1 this is a clock output pin for a debugger. when the on-chip debug function is us ed, p41/tool1 pin can be used as fo llows by the mode setting on the debugger. 1-line mode: can be used as a port (p41). 2-line mode: used as a tool1 pin a nd cannot be used as a port (p41). caution the function of the p40/tool0 pin var ies as described in (a) to (c) below. in the case of (b) or (c), make the specified connection. (a) in normal operation mode and when on-chip debugging is disabled (ocdenset = 0) by an option byte (000c3h) => use this pin as a port pin (p40). (b) in normal operation mode and when on-chip debugging is enabled (ocdenset = 1) by an option byte (000c3h) => connect this pin to v dd via an external resistor, and a lways input a high level to the pin before reset release. (c) when on-chip debug functi on is used, or in write mode of flash memory programmer => use this pin as tool0. directly connect this pin to the on-chip debug emulator or a flas h memory programmer, or pull it up by connecting it to v dd via an external resistor. 2.2.6 p50 to p57 p50 to p57 function as an i/o port. this port can also be used for serial interface data i/o, timer input, and segment output of lcd controller/driver. 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p50/rxd3/segxx (xx = 30) ( xx = 39) ( xx = 53) p51/txd3/segxx ( xx = 29) ( xx = 38) ( xx = 52) p52/ti02/segxx ( xx = 28) ( xx = 37) ( xx = 51) p53/ti04/segxx ( xx = 27) ( xx = 36) ( xx = 50) p54/segxx ( xx = 26) ( xx = 35) ( xx = 49) p55/segxx ( xx = 25) ( xx = 34) ( xx = 48) p56/segxx ( xx = 24) ( xx = 33) ( xx = 47) p57/segxx ( xx = 23) ( xx = 32) ( xx = 46) the following operation modes can be specified in 1-bit units. (1) port mode p50 to p57 function as an i/o port. p50 to p57 can be set to input or output port in 1-bit units using port mode register 5 (pm5). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (pu5).
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 50 jun 20, 2011 (2) control mode p50 to p57 function as serial interface data i/o, time r input, and segment output of lcd controller/driver. (a) rxd3 this is a serial data input pi n of serial interface uart3. (b) txd3 this is a serial data output pin of serial interface uart3. (c) ti02, ti04 these are the timer input pins of 16-bit timers 02 and 04. (d) segxx this is a segment output pin of lcd controller/driver. 2.2.7 p60, p61 p60 and p61 function as an i/o port. this port can al so be used for s serial interface iica data i/o and clock i/o. 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p60/scl0 ? p61/sda0 ? the following operation modes can be specified in 1-bit units. (1) port mode p60 and p61 function as an i/o port. p60 and p61 can be set to input port or output port in 1-bit units using port mode register 6 (pm6). output of p60 and p61 is n-ch open- drain output (6 v tolerance). (2) control mode p60 and p61 function as serial interface iica clock i/o and data i/o. (a) scl0 this is a serial clock i/o pi n of serial interface iica. (b) sda0 this is a serial data i/o pin of serial interface iica. caution when using p60/scl0 and p61/sda0 as a ge neral-purpose port, stop the operation of serial interface iica.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 51 jun 20, 2011 2.2.8 p70 to p77 p70 to p77 function as an i/o port. this port can also be us ed for key return in put, serial interface clock i/o, and data i/o. input to the p75, and p76 pins can be specified through a no rmal input buffer or a ttl input buffer in 1-bit units using port input mode register 7 (pim7). output from the p75, and p77 pins can be specified as n-ch open-drain output (v dd tolerance) in 1-bit units using port output mode register 7 (pom7). 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p70/kr0 ? p71/kr1 ? p72/kr2 ? p73/kr3 ? p74/kr4 ? p75/sck01 ? p76/kr6/si01 ? p77/kr7/so01 ? the following operation modes can be specified in 1-bit units. (1) port mode p70 to p77 function as an i/o port. p70 to p77 can be set to input or output port in 1-bit units using port mode register 7 (pm7). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (pu7). (2) control mode p70 to p77 function as key interrupt in put, serial interface clock i/o, and data i/o. (a) kr0 to kr7 these are the key return input pins (b) sck01 this is a clock i/o pin of serial interface csi01. (c) si01 this is a serial data input pi n of serial interface csi01. (d) so01 this is a serial data output pin of serial interface csi01. caution to use p75/sck01/kr5, p76/ si01/kr6, and p77/so01/kr7, as a gene ral-purpose port, note the serial array unit 0 setting. for details, refer to table 14- 6 relationship between regi ster settings and pins (channel 1 of unit 0: csi01, uart0 reception).
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 52 jun 20, 2011 2.2.9 p80 to p87 p80 to p87 function as an i/o port. this port can also be used for serial interface clock i/o, data i/o, timer i/o, and external interrupt request input. output from the p80 and p82 pins can be specified as n-ch open-drain output (v dd tolerance) in 1-bit units using port output mode register 8 (pom8). 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p80/sck00/intp11 ? p81/rxd0/si00/intp9 ? p82/txd0/so00 ? p83 ? ? p84/to10/ti10 ? ? p85/to11/ti11 ? ? p86/to12/ti12 ? ? p87/to13/ti13 ? ? the following operation modes can be specified in 1-bit units. (1) port mode p80 to p87 function as an i/o port. p80 to p87 can be set to input or output port in 1-bit units using port mode register 8 (pm8). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 8 (pu8). (2) control mode p80 to p87 function as serial interface clock i/o, data i/o, timer i/o, and exter nal interrupt request input. (a) sck00 this is a clock i/o pin of serial interface csi00. (b) si00 this is a serial data input pi n of serial interface csi00. (c) so00 this is a serial data output pin of serial interface csi00. (d) rxd0 this is a serial data input pin for serial interface uart0. (e) txd0 this is a serial data output pin for serial interface uart0. (f) ti10 to ti13 these are the timer input pins of 16-bit timers 10 to 13. (g) to10 to to13 these are the timer output pins of 16-bit timers 10 to 13.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 53 jun 20, 2011 (h) intp9, intp11 these are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. caution to use p80/sck00/intp11, p81/rxd0/si00/in tp9, and p82/so00/txd0, as a general-purpose port, note the serial array unit 0 setting. for details, re fer to table 14-5 relationship between register settings and pins (channel 0 of unit 0: csi00, uart0 reception). 2.2.10 p90 to p97 p90 to p97 function as an i/o port. this port can also be used for segment output of lcd controller/driver. 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p90/segxx (xx = 22) (xx = 31) (xx = 45) p91/segxx (xx = 21) (xx = 30) (xx = 44) p92/segxx (xx = 20) (xx = 29) (xx = 43) p93/segxx ? (xx = 28) (xx = 42) p94/segxx ? (xx = 27) (xx = 41) p95/segxx ? (xx = 26) (xx = 40) p96/segxx ? (xx = 25) (xx = 39) p97/segxx ? (xx = 24) (xx = 38) the following operation modes can be specified in 1-bit units. (1) port mode p90 to p97 function as an i/o port. p90 to p97 can be set to input or output port in 1-bit units using port mode register 9 (pm9). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 9 (pu9). (2) control mode p90 to p97 function as segment output of lcd controller/driver (segxx).
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 54 jun 20, 2011 2.2.11 p100 to p102 p100 to p102 function as an i/o port. this port can also be used for segment output of lcd controller/driver. 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p100/segxx (xx = 11) (xx = 15) (xx = 29) p101/segxx ? ? (xx = 28) p102/segxx ? ? (xx = 27) the following operation modes can be specified in 1-bit units. (1) port mode p100 to p102 function as an i/o port. p100 to p102 can be set to input or output port in 1-bit units using port mode register 10 (pm10). use of an on-chip pull-up resistor ca n be specified by pull-up resistor option register 10 (pu10). (2) control mode p100 to p102 function as segment output of lcd controller/driver (segxx). 2.2.12 p110, p111 p110 and p111 function as an i/o port. this port can also be used for d/a converter analog output. pd78f150xa pd78f151xa 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) p110/ano0 p110 p111/ano1 p111 the following operation modes can be specified in 1-bit units. (1) port mode p110 and p111 function as an i/o port. p110 and p111 can be set to input or output port in 1-bit units using port mode register 11 (pm11). (2) control mode p110 and p111 function as d/a conv erter analog output (ano0, ano1). caution when using at least one port of p 110/ano0 and p111/ano1 as a digital port, set av dd1 to the same potential as ev dd or v dd .
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 55 jun 20, 2011 2.2.13 p120 to p124 p120 function as an i/o port. p121 to p124 function as an input port. these pins also func tion as potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonat or for subsystem clock, external clock input for main system clo ck, and external interrupt request input. 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p120/intp0/exlvi p121/x1 p122/x2/exclk p123/xt1 p124/xt2 the following operation modes can be specified in 1-bit units. (1) port mode p120 functions as an i/o port. p120 can be set to input por t or output port using port mode register 12 (pm12). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). p121 to p124 function as an input port. (2) control mode p120 to p124 function as potential input for external low- voltage detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external interrupt request input. (a) exlvi this is a potential input pin for external low-voltage detection. (b) x1, x2 these are the pins for connecting a resonator for main system clock. (c) exclk this is an external clock inpu t pin for main system clock. (d) xt1, xt2 these are the pins for connecting a resonator for subsystem clock. (e) intp0 this is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. caution the function setting on p121 to p124 is available only once after the reset release. the port once set for connection to an oscillato r cannot be used as an input port unless the reset is performed.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 56 jun 20, 2011 2.2.14 p130 p130 functions as an output port. 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p130 remark the p130 pin outputs a low level when it is used as a port function pin and a reset is effected. if p130 is set to output a high level before reset is effected, the output signal of p130 can be dummy-output as the cpu reset signal (see the figure for remark in 4.2.14 port 13 ). 2.2.15 p140 to p147 p140 to p147 function as an i/o port. this port can also be used for segment output of lcd controller/driver. 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p140/segxx (xx = 19) (xx = 23) (xx = 37) p141/segxx (xx = 18) (xx = 22) (xx = 36) p142/segxx (xx = 17) (xx = 21) (xx = 35) p143/segxx (xx = 16) (xx = 20) (xx = 34) p144/segxx (xx = 15) (xx = 19) (xx = 33) p145/segxx (xx = 14) (xx = 18) (xx = 32) p146/segxx (xx = 13) (xx = 17) (xx = 31) p147/segxx (xx = 12) (xx = 16) (xx = 30) the following operation modes can be specified in 1-bit units. (1) port mode p140 to p147 function as an i/o port. p140 to p147 can be set to input or output port in 1-bit units using port mode register 14 (pm14). use of an on-chip pull-up resistor ca n be specified by pull-up resistor option register 14 (pu14). (2) control mode p140 to p147 function as segment output of lcd controller/driver (segxx).
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 57 jun 20, 2011 2.2.16 p150 to p152, p157 p150 to p152 and p157 function as an i/o port. this port c an also be used for a/d converter analog input, reference voltage input, and operational amplifier input. pd78f150xa pd78f151xa 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) p150/ani8/amp2+ ? ? p150/ani8 p151/ani9 ? ? p152/ani10 ? ? p157/ani15/av refm p157/ani15 the following operation modes can be specified in 1-bit units. (1) port mode p150 to p152 and p157 function as an i/o port. p150 to p152 and p157 can be set to input or output port in 1-bit units using port mode register 15 (pm15). (2) control mode p150 to p152 and p157 function as a/d converter analog input, reference voltage input, and operational amplifier input. (a) ani8 to ani10, ani15 these are a/d converter analog input pins. (b) av refm this is the pin that inputs the negativ e reference voltage of a/d converter. (c) amp2+ this is the pin that the input voltage on the positive side of operational amplifier 2. cautions 1. p150/ani8/amp2+ to p152/ani10 and p157/ani15/av refm are set in the digital input (general- purpose port) mode after release of reset. 2. when using at least one port of p 150/ani8/amp2+ to p152/ ani10 and p157/ani15/av refm as a digital port, set av dd0 to the same potential as ev dd or v dd . 2.2.17 com0 to com7 these are common outputs of lcd controller/driver. 2.2.18 segxx these are segment outputs of lcd controller/driver. remark 78k0r/lf3: seg0 to seg30 78k0r/lg3: seg0 to seg39 78k0r/lh3: seg0 to seg53 2.2.19 v lc0 to v lc3 these are the pins for inputting a power supply voltage pin for driving the lcd.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 58 jun 20, 2011 2.2.20 v refout /av refp ( pd78f150xa only) v refout is an analog reference voltage output pin for voltage reference. av refp is the pin that inputs the pos itive reference voltage of the a/ d converter and d/a converter. 2.2.21 av ref ( pd78f151xa only) av ref is the pin that inputs the positive re ference voltage of the a/d converter. 2.2.22 reset this is the active-low system reset input pin. when the external reset pin is not used, connect this pin directly to ev dd or via a resistor. when the external reset pin is used, design the circuit based on v dd . 2.2.23 regc this is the pin for connecting regulator output (2.4 v) stab ilization capacitance for internal operation. connect this pin to v ss via a capacitor (0.47 to 1 f). also, use a capacitor with good characteristics, si nce it is used to stabilize internal voltage. regc v ss caution keep the wiring length as short as possible for the broken- line part in the above figure. 2.2.24 flmd0 this is a pin for setting flash memory programming mode. perform either of the following processing. (a) in normal operation mode it is recommended to leave this pin open during normal operation. the flmd0 pin must always be kept at the v ss level before reset release but does not have to be pulled down externally because it is internally pulled down by rese t. however, pulling it down must be kept selected (i.e., flmdpup = ?0?, default value) by using bit 7 (flmdpup ) of the background event control register (bectl) (see 27.5 (1) back ground event control register ). to pull it down externally, use a resistor of 200 k or smaller. self programming and the rewriting of flash memory wit h the programmer can be prohibited using hardware, by directly connecting this pin to the v ss pin. (b) in self programming mode it is recommended to leave this pin open when using the self programming function. to pull it down externally, use a resistor of 100 k to 200 k . in the self programming mode, the setting is swit ched to pull up in the self programming library. (c) in flash memory programming mode directly connect this pin to a flash memory programmer when data is written by the flash memory programmer. this supplies a writing voltage of the v dd level to the flmd0 pin. the flmd0 pin does not have to be pulled down externally bec ause it is internally pulled down by reset. to pull it down externally, use a resistor of 1 k to 200 k .
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 59 jun 20, 2011 2.2.25 av dd0 , av dd1 , av dd , ev dd1 , av ss , ev dd , ev ss , v dd , v ss (1) av dd0 ( pd78f150xa only) this is the ground potential pi n of a/d converter, operational amplifier, voltage referenc e, p20 to p27, p150 to p152 and p157. when using at least one port of ports 2 and 15 as a digita l port, or when not using th e a/d converter, operational amplifier, or voltage reference, set av dd0 to the same potential as ev dd or v dd . (2) av dd1 ( pd78f150xa only) this is the ground potential pin of d/a converter, p110 and p111. when using at least one port of ports 11 as a digi tal port, or when not using the d/a converter set av dd1 to the same potential as ev dd or v dd . (3) av dd ( pd78f151xa only) this is the ground potential pi n of a/d converter, p20 to p27, p150 to p152 and p157. when using at least one port of ports 2 and 15 as a di gital port, or when not using the a/d converter, set av dd to the same potential as ev dd or v dd . (4) ev ddi ( pd78f151xa only) this is the ground potentia l pin of p110 and p111. when using at least one port of ports 11 as a digital port, set ev dd1 to the same potential as ev dd or v dd . (5) av ss this is the ground potential pin of a/d converter, d/a converte r, operational amplifier, volt age reference, p20 to p27, p110, p111, p150 to p152, and p157. even when the a/d converter, d/a c onverter, operational amplifier, and voltage reference is not used, always us e this pin with the same potential as ev ss and v ss . (6) ev dd this is the positive power supply pin fo r ports other than p20 to p27, p110, p 111, p150 to p152, and p157 as well as for the reset and flmd0 pins. (7) ev ss this is the ground potential pin for ports other than p20 to p27, p110, p111, p150 to p152, and p157 as well as for the reset and flmd0 pins. (8) v dd this is the positive power supply pin other than ports, reset, and flmd0 pins. (9) v ss this is the ground potential pin other than ports, reset, and flmd0 pins.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 60 jun 20, 2011 2.3 pin i/o circuits and recomme nded connection of unused pins 2.3.1 78k0r/lf3 table 2-2 shows the types of pin i/o circuits and the recommended connections of unused pins. table 2-2. connection of unused pins (78k0r/lf3) (1/3) pin name i/o circuit type i/o recommended connection of unused pins p00/caph p01/capl 12-h p02/v lc3 5-at p10/sck20/scl20 p11/si20/rxd2/sda20/ intp6 5-an p12/so20/txd2/to02 p13/so10/txd1/to04 5-ag p14/si10/rxd1/sda10/ intp4 p15/sck10/scl10/intp7 5-an input: independently connect to ev dd or ev ss via a resistor. output: leave open. p20/ani0/amp0- note 1, 2 11-p note 3 p21/ani1/amp0o note 1, 2 11-s note 3 p22/ani2/amp0+ note 1, 2 11-n note 3 p23/ani3/amp1- note 1, 2 11-p note 3 p24/ani4/amp1o note 1, 2 11-s note 3 p25/ani5/amp1+ note 1, 2 11-n note 3 p26/ani6 note 1, 2 11-g note 3 input: independently connect to av dd0 or av ss via a resistor. output: leave open. p30/ti03/to00/rtc1hz/ intp1 p31/ti00/to03/rtcdiv/ rtccl/pclbuz1/intp2 p32/ti01/to01/intp5/ pclbuz0 p33/ti07/to07/intp3 input: independently connect to ev dd or ev ss via a resistor. output: leave open. p40/tool0 8-r pull this pin up (pulling it down is prohibited). input: independently connect to ev dd or ev ss via a resistor. output: leave open. p41/tool1 5-ag input: independently connect to ev dd or ev ss via a resistor. output: leave open. p50/seg30/rxd3 17-q p51/seg29/txd3 17-p p52/seg28/ti02 p53/seg27/ti04 17-q p54/seg26 to p57/seg23 17-p i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. leave open. notes 1. p20/ani0/amp0- to p26/ani6 are set in the digital input port mode after release of reset. 2. ampxx applies to pd78f150xa only. 3. pd78f151xa corresponds to type 11-g.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 61 jun 20, 2011 table 2-2. connection of unused pins (78k0r/lf3) (2/3) pin name i/o circuit type i/o recommended connection of unused pins p90/seg22 to p92/seg20 p100/seg11 17-p input: independently connect to ev dd or ev ss via a resistor. output: leave open. leave open. p110/ano0 note 3 , p111/ano1 note 3 12-a note 4 i/o input: independently connect to av dd1 or av ss via a resistor. output: leave open. p120/intp0/exlvi 8-r i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. p121/x1 note 1 p122/x2/exclk note 1 37-c p123/xt1 note 1 p124/xt2 note 1 37-a input independently connect to ev dd or ev ss via a resistor. p130 3-c output leave open. p140/seg19 to p147/seg12 17-p i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. leave open. p157/ani15/av refm note 2, 3 11-t note 5 i/o input: independently connect to av dd0 or av ss via a resistor. output: leave open. seg0/com4 to seg3/com7 18-f seg4 to seg10 17-t com0 to com3 18-e output v lc0 to v lc2 ? ? leave open. notes 1. use recommended connection above in input port mode (see figure 5-2 format of clock operation mode control register (cmc) ) when these pins are not used. 2. p157/ani15/av refm is set in the digital input port mode after release of reset. 3. anox and av refm apply to pd78f150xa only. 4. pd78f151xa corresponds to type 5. 5. pd78f151xa corresponds to type 11-g.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 62 jun 20, 2011 table 2-2. connection of unused pins (78k0r/lf3) (3/3) pin name i/o circuit type i/o recommended connection of unused pins av dd0 note 1 , av dd note 2 ? ? make this pin the same potential as ev dd or v dd . make this pin to have a potential where 2.3 v av dd0 v dd . av dd1 note 1 ? ? make this pin the same potential as ev dd or v dd . make this pin to have a potential where 2.3 v av dd1 v dd . ev dd1 note 2 make this pin the same potential as ev dd or v dd . av ss ? ? make this pin the same potential as the ev ss or v ss . v refout note 1 /av refp note 1 , av ref note 2 ? ? make this pin the same potential as the av dd0 , ev dd or v dd . flmd0 2-w ? leave open or connect to v ss via a resistor of 100 k or more. reset 2 input connect directly to ev dd or via a resistor. regc ? ? connect to v ss via capacitor (0.47 to 1 f). notes 1. dedicated to pd78f150xa 2. dedicated to pd78f151xa
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 63 jun 20, 2011 2.3.2 78k0r/lg3 table 2-3 shows the types of pin i/o circuits and the recommended connections of unused pins. table 2-3. connection of u nused pins (78k0r/lg3) (1/3) pin name i/o circuit type i/o recommended connection of unused pins p00/caph p01/capl 12-h p02/v lc3 5-at p10/sck20/scl20 p11/si20/rxd2/sda20/ intp6 5-an p12/so20/txd2/to02 p13/so10/txd1/to04 5-ag p14/si10/rxd1/sda10/ intp4 p15/sck10/scl10/intp7 5-an p16/ti05/to05/intp10 8-r input: independently connect to ev dd or ev ss via a resistor. output: leave open. p20/ani0/amp0- note 1, 2 11-p note 3 p21/ani1/amp0o note 1, 2 11-s note 3 p22/ani2/amp0+ note 1, 2 11-n note 3 p23/ani3/amp1- note 1, 2 11-p note 3 p24/ani4/amp1o note 1, 2 11-s note 3 p25/ani5/amp1+ note 1, 2 11-n note 3 p26/ani6/amp2- note 1, 2 11-p note 3 p27/ani7/amp2o note 1, 2 11-s note 3 input: independently connect to av dd0 or av ss via a resistor. output: leave open. p30/ti03/to00/rtc1hz/ intp1 p31/ti00/to03/rtcdiv/ rtccl/pclbuz1/intp2 p32/ti01/to01/intp5/ pclbuz0 p33/ti07/to07/intp3 p34/ti06/to06/intp8 8-r input: independently connect to ev dd or ev ss via a resistor. output: leave open. p40/tool0 8-r pull this pin up (pulling it down is prohibited). input: independently connect to ev dd or ev ss via a resistor. output: leave open. p41/tool1 5-ag i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. notes 1. p20/ani0/amp0- to p27/ani7/anp2o are set in the digital input port mode after release of reset. 2. ampxx applies to pd78f150xa only. 3. pd78f151xa corresponds to type 11-g.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 64 jun 20, 2011 table 2-3. connection of u nused pins (78k0r/lg3) (2/3) pin name i/o circuit type i/o recommended connection of unused pins p50/seg39/rxd3 17-q p51/seg38/txd3 17-p p52/seg37/ti02 p53/seg36/ti04 17-q p54/seg35 to p57/seg32 17-p input: independently connect to ev dd or ev ss via a resistor. output: leave open. leave open. p60/scl0 p61/sda0 13-r p80/sck00/intp11 p81/rxd0/si00/intp9 8-r p82/so00/txd0 5-ag input: independently connect to ev dd or ev ss via a resistor. output: leave open. p90/seg31 to p97/seg24 p100/seg15 17-p input: independently connect to ev dd or ev ss via a resistor. output: leave open. leave open. p110/ano0 note 1 , p111/ano1 note 1 12-a input: independently connect to av dd1 or av ss via a resistor. output: leave open. p120/intp0/exlvi 8-r i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. p121/x1 note 3 p122/x2/exclk note 3 37-c p123/xt1 note 3 p124/xt2 note 3 37-a input independently connect to ev dd or ev ss via a resistor. p130 3-c output leave open. p140/seg23 to p147/seg16 17-p i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. leave open. notes 1. anox and av refm apply to pd78f150xa only. 2. pd78f151xa corresponds to type 5. 3. use recommended connection above in input port mode (see figure 5-2 format of clock operation mode control register (cmc) ) when these pins are not used.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 65 jun 20, 2011 table 2-3. connection of u nused pins (78k0r/lg3) (3/3) pin name i/o circuit type i/o recommended connection of unused pins p150/ani8/amp2+ note 1 11-n p151/ani9 note 1 p152/ani10 note 1 11-g p157/ani15/av refm note 1, 2 11-t note 3 i/o input: independently connect to av dd0 or av ss via a resistor. output: leave open. seg0/com4 to seg3/com7 18-f seg4 to seg14 17-t com0 to com3 18-e output v lc0 to v lc2 ? ? leave open. av dd0 ? ? make this pin the same potential as ev dd or v dd . make this pin to have a potential where 2.3 v av dd0 v dd . av dd1 ? ? make this pin the same potential as ev dd or v dd . make this pin to have a potential where 2.3 v av dd1 v dd . av ss ? ? make this pin the same potential as the ev ss or v ss . v refout /av refp ? ? make this pin the same potential as the av dd0 , ev dd or v dd . flmd0 2-w ? leave open or connect to v ss via a resistor of 100 k or more. reset 2 input connect directly to ev dd or via a resistor. regc ? ? connect to v ss via capacitor (0.47 to 1 f). notes 1. p150/ani8/amp2+ to p152/ani10 and p157/ani15/av refm are set in the digital input port mode after release of reset. 2. anox and av refm apply to pd78f150xa only. 3. pd78f151xa corresponds to type 11-g.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 66 jun 20, 2011 2.3.3 78k0r/lh3 table 2-4 to shows the types of pin i/o circui ts and the recommended connec tions of unused pins. table 2-4. connection of unused pins (78k0r/lh3) (1/3) pin name i/o circuit type i/o recommended connection of unused pins p00/caph p01/capl 12-h p02/v lc3 5-at p10/sck20/scl20 p11/si20/rxd2/sda20/ intp6 5-an p12/so20/txd2/to02 p13/so10/txd1/to04 5-ag p14/si10/rxd1/sda10/ intp4 p15/sck10/scl10/intp7 5-an p16/ti05/to05/intp10 8-r p17 5-ag input: independently connect to ev dd or ev ss via a resistor. output: leave open. p20/ani0/amp0- note 1, 2 11-p note 3 p21/ani1/amp0o note 1, 2 11-s note 3 p22/ani2/amp0+ note 1, 2 11-n note 3 p23/ani3/amp1- note 1, 2 11-p note 3 p24/ani4/amp1o note 1, 2 11-s note 3 p25/ani5/amp1+ note 1, 2 11-n note 3 p26/ani6/amp2- note 1, 2 11-p note 3 p27/ani7/amp2o note 1, 2 11-s note 3 input: independently connect to av dd0 or av ss via a resistor. output: leave open. p30/ti03/to00/rtc1hz/ intp1 p31/ti00/to03/rtcdiv/ rtccl/pclbuz1/intp2 p32/ti01/to01/intp5/ pclbuz0 p33/ti07/to07/intp3 p34/ti06/to06/intp8 8-r input: independently connect to ev dd or ev ss via a resistor. output: leave open. p40/tool0 8-r pull this pin up (pulling it down is prohibited). input: independently connect to ev dd or ev ss via a resistor. output: leave open. p41/tool1 5-ag i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. notes 1. p20/ani0/amp0- to p27/ani7/anp2o are set in the digital input port mode after release of reset. 2. ampxx applies to pd78f150xa only. 3. pd78f151xa corresponds to type 11-g.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 67 jun 20, 2011 table 2-4. connection of unused pins (78k0r/lh3) (2/3) pin name i/o circuit type i/o recommended connection of unused pins p50/seg53/rxd3 17-q p51/seg52/txd3 17-p p52/seg51/ti02 p53/seg50/ti04 17-q p54/seg49 to p57/seg46 17-p input: independently connect to ev dd or ev ss via a resistor. output: leave open. leave open. p60/scl0 p61/sda0 13-r p70/kr0 to p74/kr4 8-r p75/kr5/sck01 p76/kr6/si01 5-an p77/kr7/so01 p80/sck00/intp11 p81/rxd0/si00/intp9 8-r p82/so00/txd0 p83 5-ag p84/ti10/to10 p85/ti11/to11 p86/ti12/to12 p87/ti13/to13 8-r input: independently connect to ev dd or ev ss via a resistor. output: leave open. p90/seg45 to p97/seg38 p100/seg29 to p102/seg27 17-p input: independently connect to ev dd or ev ss via a resistor. output: leave open. leave open. p110/ano0 note 1 , p111/ano1 note 1 12-a note 2 i/o input: independently connect to av dd1 or av ss via a resistor. output: leave open. p120/intp0/exlvi 8-r i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. p121/x1 note 3 p122/x2/exclk note 3 37-c p123/xt1 note 3 p124/xt2 note 3 37-a input independently connect to ev dd or ev ss via a resistor. p130 3-c output leave open. p140/seg37 to p147/seg30 17-p i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. leave open. notes 1. anox applies to pd78f150xa only. 2. pd78f151xa corresponds to type 5. 3. use recommended connection above in input port mode (see figure 5-2 format of clock operation mode control register (cmc) ) when these pins are not used.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 68 jun 20, 2011 table 2-4. connection of unused pins (78k0r/lh3) (3/3) pin name i/o circuit type i/o recommended connection of unused pins p150/ani8/amp2+ note 1 11-n p151/ani9 note 1 p152/ani10 note 1 11-g note 3 p157/ani15/av refm note 1, 2 11-t i/o input: independently connect to av dd0 or av ss via a resistor. output: leave open. seg0/com4 to seg3/com7 18-f seg4 to seg26 17-t com0 to com3 18-e output v lc0 to v lc2 ? ? leave open. av dd0 ? ? make this pin the same potential as ev dd or v dd . make this pin to have a potential where 2.3 v av dd0 v dd . av dd1 ? ? make this pin the same potential as ev dd or v dd . make this pin to have a potential where 2.3 v av dd1 v dd . av ss ? ? make this pin the same potential as the ev ss or v ss . v refout /av refp ? ? make this pin the same potential as the av dd0 , ev dd or v dd . flmd0 2-w ? leave open or connect to v ss via a resistor of 100 k or more. reset 2 input connect directly to ev dd or via a resistor. regc ? ? connect to v ss via capacitor (0.47 to 1 f). notes 1. p150/ani8/amp2+ to p152/ani10 and p157/ani15/av refm are set in the digital input port mode after release of reset. 2. av refm applies to pd78f150xa only. 3. pd78f151xa corresponds to type 11-g.
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 69 jun 20, 2011 figure 2-1. pin i/o circuit list (1/5) type 2 type 2-w schmitt-triggered input with hysteresis characteristics in in pull-down enable n-ch pull-up enable p-ch v dd v ss schmitt-triggered input with hysteresis characteristics type 3-c type 5 ev dd p-ch n-ch data out ev ss pullup enable data output disable input enable ev dd p-ch ev dd ev ss p-ch in/out n -ch type 5-an type 5-ag pull-up enable data output disable p-ch ev dd ev dd ev ss p-ch in/out n -ch cmos ttl input characteristic pullup enable data output disable input enable ev dd p-ch ev dd ev ss p-ch in/out n -ch
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 70 jun 20, 2011 figure 2-1. pin i/o circuit list (2/5) type 5-at type 11-s pullup enable data output disable input enable p-ch p-ch in/out ev dd ev dd ev ss n -ch v lc3 data output disable av dd0 p-ch in/out n-ch p-ch n-ch comparator input enable + _ av ss av ss + _ op amp v ref (threshold voltage) type 8-r type 11-g data output disable ev dd p-ch in/out n-ch ev ss pullup enable ev dd p-ch data output disable av dd0 p-ch in/out n-ch p-ch n-ch input enable + _ av ss av ss comparator series resistor string voltage type 11-n type 11-p data output disable av ref p-ch in/out n-ch p-ch n-ch comparator input enable + _ av ss av ss + _ op amp v ref (threshold voltage) data output disable av ref p-ch in/out n-ch p-ch n-ch input enable + _ av ss av ss + _ op amp (threshold voltage) comparator v ref
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 71 jun 20, 2011 figure 2-1. pin i/o circuit list (3/5) type 11-t type 12-h data output disable av dd0 p-ch in/out n-ch p-ch n-ch comparator input enable + _ av ss av ss v ref (threshold voltage) p-ch n-ch av refm pullup enable data output disable input enable ev dd p-ch ev dd p-ch in/out n-ch p-ch n-ch caph, capl ev ss type 12-a type 17-p data output disable input enable av dd1 p-ch in/out n-ch p-ch n-ch av ss analog output voltage type 13-r in/out n -ch data output disable ev ss p-ch n-ch seg data p-ch n-ch p-ch p-ch n-ch pullup enable data output disable input enable p-ch p-ch in/out p-ch n-ch n-ch v lc0 v lc1 v lc2 ev dd ev dd n -ch v lc3 ev ss v ss
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 72 jun 20, 2011 figure 2-1. pin i/o circuit list (4/5) type 17-q type 17-t p-ch n-ch seg data p-ch n-ch p-ch n-ch out p-ch n-ch n-ch v lc0 v lc1 v lc2 v lc3 v ss type 18-e p-ch n-ch seg data p-ch n-ch p-ch n-ch pullup enable data output disable input enable p-ch p-ch in/out p-ch n-ch n-ch v lc0 v lc1 v lc2 ev dd ev dd n -ch v lc3 ev ss v ss p-ch com data p-ch n-ch out p-ch n-ch n-ch n-ch p-ch p-ch n-ch p-ch n-ch v lc0 v lc1 v lc2 v lc3 v ss
78k0r/lx3 chapter 2 pin functions r01uh0004ej0501 rev.5.01 73 jun 20, 2011 figure 2-1. pin i/o circuit list (5/5) type 18-f type 37-a xt1 input enable input enable p-ch n-ch xt2 type 37-c p-ch com data p-ch n-ch p-ch n-ch n-ch n-ch p-ch p-ch n-ch p-ch n-ch out p-ch n-ch seg data p-ch n-ch p-ch n-ch p-ch n-ch n-ch v lc0 v lc1 v lc2 v lc3 v ss v lc0 v lc1 v lc2 v lc3 v ss x1 input enable input enable p-ch n-ch x2
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 74 jun 20, 2011 chapter 3 cpu architecture 3.1 memory space products in the 78k0r/lx3 microcontrollers can access a 1 mb memory space. figures 3-1 to 3-3 show the memory maps. figure 3-1. memory map ( pd78f1500a, 78f1503a, 78f1506a, 78f1510a, 78f1513a, 78f1516a) 00000h effffh f0000h f07ffh f0800h f0fffh f1000h feeffh fef00h ffedfh ffee0h ffeffh fff00h fffffh 00000h 0007fh 00080h 000bfh 000c0h 000c3h 000c4h 00fffh 01000h 0107fh 01080h 010bfh 010c0h 010c3h 010c4h 0ffffh 0ffffh 10000h special function register (sfr) 256 bytes ram note 1 4 kb general-purpose register 32 bytes flash memory 64 kb extended special function register (2nd sfr) 2 kb mirror 55.75 kb vector table area 128 bytes callt table area 64 bytes program area option byte area note 2 4 bytes vector table area 128 bytes callt table area 64 bytes option byte area note 2 4 bytes program area reserved reserved program memory space data memory space on-chip debug security id setting area note 2 10 bytes 01fffh boot cluster 0 note 3 boot cluster 1 010cdh 010ceh on-chip debug security id setting area note 2 10 bytes 000cdh 000ceh notes 1. instructions can be executed from the ram ar ea excluding the general-purpose register area. 2. when boot swap is not used: set the option bytes to 000c0h to 000c3h, and the on-chip debug security ids to 000c4h to 000cdh. when boot swap is used: set the option bytes to 000c0h to 000c3h and 010c0h to 010c3h, and the on-chip debug security ids to 000c4h to 000cdh and 010c4h to 010cdh. 3. writing boot cluster 0 can be prohibited depending on the setting of security (see 27.7 security setting ).
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 75 jun 20, 2011 figure 3-2. memory map ( pd78f1501a, 78f1504a, 78f1507a) 00000h effffh f0000h f07ffh f0800h f0fffh f1000h fe6ffh fe700h ffedfh ffee0h ffeffh fff00h fffffh 00000h 0007fh 00080h 000bfh 000c0h 000c3h 000c4h 00fffh 01000h 0107fh 01080h 010bfh 010c0h 010c3h 010c4h 17fffh 17fffh 18000h special function register (sfr) 256 bytes ram note 1 6 kb general-purpose register 32 bytes flash memory 96 kb extended special function register (2nd sfr) 2 kb mirror 53.75 kb vector table area 128 bytes callt table area 64 bytes program area option byte area note 2 4 bytes vector table area 128 bytes callt table area 64 bytes option byte area note 2 4 bytes program area reserved reserved program memory space data memory space on-chip debug security id setting area note 2 10 bytes 01fffh boot cluster 0 note 3 boot cluster 1 010cdh 010ceh on-chip debug security id setting area note 2 10 bytes 000cdh 000ceh notes 1. instructions can be executed from the ram ar ea excluding the general-purpose register area. 2. when boot swap is not used: set the option bytes to 000c0h to 000c3h, and the on-chip debug security ids to 000c4h to 000cdh. when boot swap is used: set the option bytes to 000c0h to 000c3h and 010c0h to 010c3h, and the on-chip debug security ids to 000c4h to 000cdh and 010c4h to 010cdh. 3. writing boot cluster 0 can be prohibited depending on the setting of security (see 27.7 security setting ).
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 76 jun 20, 2011 figure 3-3. memory map ( pd78f1502a, 78f1505a, 78f1508a, 78f1512a, 78f1515a, 78f1518a) 00000h effffh f0000h f07ffh f0800h f0fffh f1000h fe2ffh fe300h ffedfh ffee0h ffeffh fff00h fffffh 00000h 0007fh 00080h 000bfh 000c0h 000c3h 000c4h 00fffh 01000h 0107fh 01080h 010bfh 010c0h 010c3h 010c4h 1ffffh 1ffffh 20000h special function register (sfr) 256 bytes ram note 1 7 kb general-purpose register 32 bytes flash memory 128 kb extended special function register (2nd sfr) 2 kb mirror 51.75 kb vector table area 128 bytes callt table area 64 bytes program area option byte area note 2 4 bytes vector table area 128 bytes callt table area 64 bytes option byte area note 2 4 bytes program area reserved reserved program memory space data memory space on-chip debug security id setting area note 2 10 bytes 01fffh boot cluster 0 note 3 boot cluster 1 010cdh 010ceh on-chip debug security id setting area note 2 10 bytes 000cdh 000ceh reserved fdeffh fdf00h notes 1. instructions can be executed from the ram ar ea excluding the general-purpose register area. 2. when boot swap is not used: set the option bytes to 000c0h to 000c3h, and the on-chip debug security ids to 000c4h to 000cdh. when boot swap is used: set the option bytes to 000c0h to 000c3h and 010c0h to 010c3h, and the on-chip debug security ids to 000c4h to 000cdh and 010c4h to 010cdh. 3. writing boot cluster 0 can be prohibited depending on the setting of security (see 27.7 security setting ).
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 77 jun 20, 2011 remark the flash memory is divided into blocks (one block = 1 kb). for the address val ues and block numbers, see table 3-1 correspondence between address va lues and block number s in flash memory . block 00h block 01h block 3fh 1 kb 003ffh 00400h 00000h 007ffh 0fbffh 0fc00h 0ffffh
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 78 jun 20, 2011 correspondence between the address values and block numbers in the flash memory are shown below. table 3-1. correspondence between address values and block number s in flash memory address value block number address value block number address value block number address value block number 00000h to 003ffh 00h 08000h to 083ffh 20h 10000h to 103ffh 40h 18000h to 183ffh 60h 00400h to 007ffh 01h 08400h to 087ffh 21h 10400h to 107ffh 41h 18400h to 187ffh 61h 00800h to 00bffh 02h 08800h to 08bffh 22h 10800h to 10bffh 42h 18800h to 18bffh 62h 00c00h to 00fffh 03h 08c00h to 08fffh 23h 10c00h to 10fffh 43h 18c00h to 18fffh 63h 01000h to 013ffh 04h 09000h to 093ffh 24h 11000h to 113ffh 44h 19000h to 193ffh 64h 01400h to 017ffh 05h 09400h to 097ffh 25h 11400h to 117ffh 45h 19400h to 197ffh 65h 01800h to 01bffh 06h 09800h to 09bffh 26h 11800h to 11bffh 46h 19800h to 19bffh 66h 01c00h to 01fffh 07h 09c00h to 09fffh 27h 11c00h to 11fffh 47h 19c00h to 19fffh 67h 02000h to 023ffh 08h 0a000h to 0a3ffh 28h 12000h to 123ffh 48h 1a000h to 1a3ffh 68h 02400h to 027ffh 09h 0a400h to 0a7ffh 29h 12400h to 127ffh 49h 1a400h to 1a7ffh 69h 02800h to 02bffh 0ah 0a800h to 0abffh 2ah 12800h to 12bffh 4ah 1a800h to 1abffh 6ah 02c00h to 02fffh 0bh 0ac00h to 0afffh 2bh 12c00h to 12fffh 4bh 1ac00h to 1afffh 6bh 03000h to 033ffh 0ch 0b000h to 0b3ffh 2ch 13000h to 133ffh 4ch 1b000h to 1b3ffh 6ch 03400h to 037ffh 0dh 0b400h to 0b7ffh 2dh 13400h to 137ffh 4dh 1b400h to 1b7ffh 6dh 03800h to 03bffh 0eh 0b800h to 0bbffh 2eh 13800h to 13bffh 4eh 1b800h to 1bbffh 6eh 03c00h to 03fffh 0fh 0bc00h to 0bfffh 2fh 13c00h to 13fffh 4fh 1bc00h to 1bfffh 6fh 04000h to 043ffh 10h 0c000h to 0c3ffh 30h 14000h to 143ffh 50h 1c000h to 1c3ffh 70h 04400h to 047ffh 11h 0c400h to 0c7ffh 31h 14400h to 147ffh 51h 1c400h to 1c7ffh 71h 04800h to 04bffh 12h 0c800h to 0cbffh 32h 14800h to 14bffh 52h 1c800h to 1cbffh 72h 04c00h to 04fffh 13h 0cc00h to 0cfffh 33h 14c00h to 14fffh 53h 1cc00h to 1cfffh 73h 05000h to 053ffh 14h 0d000h to 0d3ffh 34h 15000h to 153ffh 54h 1d000h to 1d3ffh 74h 05400h to 057ffh 15h 0d400h to 0d7ffh 35h 15400h to 157ffh 55h 1d400h to 1d7ffh 75h 05800h to 05bffh 16h 0d800h to 0dbffh 36h 15800h to 15bffh 56h 1d800h to 1dbffh 76h 05c00h to 05fffh 17h 0dc00h to 0dfffh 37h 15c00h to 15fffh 57h 1dc00h to 1dfffh 77h 06000h to 063ffh 18h 0e000h to 0e3ffh 38h 16000h to 163ffh 58h 1e000h to 1e3ffh 78h 06400h to 067ffh 19h 0e400h to 0e7ffh 39h 16400h to 167ffh 59h 1e400h to 1e7ffh 79h 06800h to 06bffh 1ah 0e800h to 0ebffh 3ah 16800h to 16bffh 5ah 1e800h to 1ebffh 7ah 06c00h to 06fffh 1bh 0ec00h to 0efffh 3bh 16c00h to 16fffh 5bh 1ec00h to 1efffh 7bh 07000h to 073ffh 1ch 0f000h to 0f3ffh 3ch 17000h to 173ffh 5ch 1f000h to 1f3ffh 7ch 07400h to 077ffh 1dh 0f400h to 0f7ffh 3dh 17400h to 177ffh 5dh 1f400h to 1f7ffh 7dh 07800h to 07bffh 1eh 0f800h to 0fbffh 3eh 17800h to 17bffh 5eh 1f800h to 1fbffh 7eh 07c00h to 07fffh 1fh 0fc00h to 0ffffh 3fh 17c00h to 17fffh 5fh 1fc00h to 1ffffh 7fh remark pd78f1500a, 78f1503a, 78f1506a, 78f1510a, 78f1513a, 78f1516a: block numbers 00h to 3fh pd78f1501a, 78f1504a, 78f1507a: block numbers 00h to 5fh pd78f1502a, 78f1505a, 78f1508a, 78f1512a, 78f1515a, 78f1518a: block numbers 00h to 7fh
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 79 jun 20, 2011 3.1.1 internal program memory space the internal program memory space st ores the program and table data. norma lly, it is addressed with the program counter (pc). 78k0r/lx3 microcontrollers products incorporate in ternal rom (flash memory), as shown below. table 3-2. intern al rom capacity internal rom part number structure capacity pd78f1500a, 78f1503a, 78f1506a, 78f1510a, 78f1513a, 78f1516a 65536 8 bits (00000h to 0ffffh) pd78f1501a, 78f1504a, 78f1507a 98303 8 bits (00000h to 17fffh) pd78f1502a, 78f1505a, 78f1508a, 78f1512a, 78f1515a, 78f1518a flash memory 131071 8 bits (00000h to 1ffffh) the internal program memory space is divided into the following areas. (1) vector table area the 128-byte area 00000h to 0007fh is reserved as a ve ctor table area. the progr am start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area. fu rthermore, the interrupt jump address is a 64 k address of 00000h to 0ffffh, becaus e the vector code is assumed to be 2 bytes. of the 16-bit address, the lower 8 bits ar e stored at even addresses and the higher 8 bits are stored at odd addresses.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 80 jun 20, 2011 table 3-3. vector table vector table address interrupt source lf3 lg3 lh3 vector table address interrupt source lf3 lg3 lh3 00030h inttm02 00000h reset input, poc, lvi, wdt, trap 00032h inttm03 00004h intwdti 00034h intad 00006h intlvi 00036h intrtc 00008h intp0 00038h intrtci 0000ah intp1 0003ah intkr ? ? 0000ch intp2 intst2 0000eh intp3 intcsi20 00010h intp4 0003ch intiic20 00012h intp5 0003eh intsr2 00014h intst3 00040h intsre2 00016h intsr3 00042h inttm04 00018h intsre3 00044h inttm05 0001ah intdma0 00046h inttm06 0001ch intdma1 00048h inttm07 intst0 ? 0004ah intp6 0001eh intcsi00 ? 0004ch intp7 intsr0 ? 0004eh intp8 ? 00020h intcsi01 ? ? 00050h intp9 ? 00022h intsre0 00052h intp10 ? intst1 00054h intp11 ? intcsi10 00056h inttm10 00024h intiic10 00058h inttm11 00026h intsr1 0005ah inttm12 00028h intsre1 0005ch inttm13 0002ah intiica ? 0005eh intmd 0002ch inttm00 0007eh brk 0002eh inttm01 (2) callt instruction table area the 64-byte area 00080h to 000bfh can st ore the subroutine entry address of a 2- byte call instruction (callt). set the subroutine entry address to a value in a range of 00000h to 0ffffh (becau se an address code is of 2 bytes). to use the boot swap function, set a callt instruction table also at 01080h to 010bfh. (3) option byte area a 4-byte area of 000c0h to 000c3h can be used as an opti on byte area. set the option byte at 010c0h to 010c3h when the boot swap is used. for details, see chapter 26 option byte .
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 81 jun 20, 2011 (4) on-chip debug security id setting area a 10-byte area of 000c4h to 000cdh and 010c4h to 010cdh can be used as an on-chip debug security id setting area. set the on-chip debug security id of 10 bytes at 000c4h to 000cdh when the boot swap is not used and at 000c4h to 000cdh and 010c4h to 010cdh when the boot swap is used. for details, see chapter 28 on-chip debug function . 3.1.2 mirror area the pd78f1500a, 78f1503a, 78f01506a, 78f1510a, 78f1513a, and 78f1516a mi rror the data flash area of 00000h to 0ffffh, to f0000h to fffffh (the data flash ar ea to be mirrored is set by the processor mode control register (pmc)). the pd78f1501a, 78f1502a, 78f1504a, 78f1505a, 78f1507a , 78f1508a, 78f1512a, 78f1515a, and 78f1518a mirror the data flash area of 00000h to 0ffffh or 10000h to 1ffffh, to f0000h to fffffh (the data flash area to be mirrored is set by the processor mode control register (pmc)). by reading data from f0000h to fffffh, an instruction that does not have the es r egisters as an operand can be used, and thus the contents of the data flash can be read with the shorter c ode. however, the data flash area is not mirrored to the sfr, extended sfr, ram, and use prohibited areas. the mirror area can only be read and no instruction can be fetched from this area.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 82 jun 20, 2011 the following show examples. remark maa: bit 0 of the processor mode control register (pmc). example 1 pd78f1500a, 78f1503a, 78f1506a, 78f1510a, 78f1513a, 78f1516a (flash memory: 64 kb, ram: 4 kb) setting maa = 0 example 2 pd78f1502a, 78f1505a, 78f1508a, 78f1512a, 78f1515a, 78f1518a (flash memory: 128 kb, ram: 7 kb) setting maa = 1 flash memory flash memory flash memory 01000h 00fffh 00000h 0ef00h 0eeffh 10000h 0ffffh mirror f0000h effffh f0800h f07ffh f1000h f0fffh fef00h feeffh ffee0h ffedfh fff00h ffeffh fffffh special-function register ( sfr) 256 bytes general-purpose register 32 bytes ram 4 kb flash memory (same data as 01000h to 0eeffh) reserved reserved extended special function register (2nd sfr) 2 kb for example, 02345h is mirrored to f2345h. data can therefore be read by mov a, !2345h, instead of mov es, #00h and mov a, es:!2345h. special-function register ( sfr) 256 bytes fffffh general-purpose register 32 bytes ffee0h ffedfh fff00h ffeffh ram 7 kb fe300h fe2ffh flash memory (same data as 11000h to 1de ff h) f0800h f07ffh f1000h f0fffh reserved f0000h effffh reserved mirror 20000h 1ffffh 00000h 1df00h 1deffh 11000h 10fffh flash memory flash memory flash memory extended special function register (2nd sfr) 2 kb reserved fdf00h fdeffh for example, 15432h is mirrored to f5432h. data can therefore be read by mov a, !5432h, instead of mov es, #01h and mov a, es:!5432h.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 83 jun 20, 2011 pmc register is described below. ? processor mode control register (pmc) this register selects the flash memory s pace for mirroring to area from f0000h to fffffh. pmc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 3-4. format of configuration of processor mode control register (pmc) address: ffffeh after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> pmc 0 0 0 0 0 0 0 maa maa selection of flash memory space fo r mirroring to area from f0000h to fffffh 0 00000h to 0ffffh is mirrored to f0000h to fffffh 1 10000h to 1ffffh is mirrored to f0000h to fffffh cautions 1. set pmc only once during the initial setti ngs prior to operating the dma controller. rewriting pmc other than during the init ial settings is prohibited. 2. after setting pmc, wait for at least one instruction and access the mirror area. 3. when the pd78f1500a, 78f1503a, 78f1506a, 78f1510 a, 78f1513a, and 78f1516a (flash memory size: 64 kb) are used, be sure to set bit 0 (maa) of this register to 0. 3.1.3 internal data memory space 78k0r/lx3 microcontrollers products incorporate the following rams. table 3-4. internal ram capacity part number internal ram pd78f1500a, 78f1503a, 78f1506a, 78f1510a, 78f1513a, 78f1516a 4096 8 bits (fef00h to ffeffh) pd78f1501a, 78f1504a, 78f1507a 6144 8 bits (fe700h to ffeffh) pd78f1502a, 78f1505a, 78f1508a, 78f1512a, 78f1515a, 78f1518a 7168 8 bits (fe300h to ffeffh) the internal ram can be used as a data area and a program area where instructions are wr itten and executed. four general-purpose register banks consisting of eight 8-bit registers per bank are a ssigned to the 32-byte area of ffee0h to ffeffh of the internal ram area. ho wever, instructions cannot be execut ed by using general-purpose registers. the internal ram is used as a stack memory. cautions 1. it is prohibi ted to use the general-purpose register (ffee0h to ffeffh) space for fetching instructions or as a stack area. 2. while using the self-programming function, th e area of ffe20h to ffeffh cannot be used as a stack memory.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 84 jun 20, 2011 3.1.4 special function register (sfr) area on-chip peripheral hardware special function registers (sfrs) are allo cated in the area fff00h to fffffh. caution do not access addresses to which sfrs are not assigned. 3.1.5 extended special function register (2 nd sfr: 2nd special function register) area on-chip peripheral hardware special function registers ( 2nd sfrs) are allocated in the area f0000h to f07ffh. sfrs other than those in the sfr area (f ff00h to fffffh) are allocated to this area. an instruction that accesses the 2nd sfr area, however, is 1 byte longer than an instruction that accesses the sfr area. caution do not access addresses to which 2nd sfrs are not assigned.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 85 jun 20, 2011 3.1.6 data memory addressing addressing refers to the method of spec ifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. several addressing modes are provided for addressing the memo ry relevant to the executio n of instructions for the 78k0r/lx3 microcontrollers, based on operability and other considerations. for areas containing data memory in particular, special addressing methods designed for the functi ons of special function regi sters (sfr) and general-purpose registers are available for use. figures 3-5 to 3-7 sh ow correspondence between data memory and addressing. figure 3-5. correspondence between data memory and addressing ( pd78f1500a, 78f1503a, 78f1506a, 78f1510a, 78f1513a, 78f1516a) special function register (sfr) 256 bytes ram 4 kb general-purpose register 32 bytes flash memory 64 kb mirror 55.75 kb reserved reserved direct addressing register indirect addressing based addressing based indexed addressing short direct addressing sfr addressing register addressing 00000h 0ffffh 10000h effffh f0000h f07ffh f0800h f0fffh f1000h feeffh fef00h ffe1fh ffe20h ffedfh ffee0h ffeffh fff00h fff1fh fff20h fffffh extended special function register (2nd sfr) 2 kb
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 86 jun 20, 2011 figure 3-6. correspondence between data memory and addressing ( pd78f1501a, 78f1504a, 78f1507a) special function register (sfr) 256 bytes ram 6 kb general-purpose register 32 bytes flash memory 96 kb mirror 53.75 kb reserved reserved direct addressing register indirect addressing based addressing based indexed addressing short direct addressing sfr addressing register addressing 00000h 17fffh 18000h effffh f0000h f07ffh f0800h f0fffh f1000h fe6ffh fe700h ffedfh ffee0h ffeffh fff00h fff1fh fff20h ffe1fh ffe20h fffffh extended special function register (2nd sfr) 2 kb
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 87 jun 20, 2011 figure 3-7. correspondence between data memory and addressing ( pd78f1502a, 78f1505a, 78f1508a, 78 f1512a, 78f1515a, 78f1518a) special function register (sfr) 256 bytes ram 7 kb general-purpose register 32 bytes flash memory 128 kb mirror 51.75 kb reserved reserved direct addressing register indirect addressing based addressing based indexed addressing short direct addressing sfr addressing register addressing 00000h effffh f0000h f07ffh f0800h f0fffh f1000h fe2ffh fe300h ffedfh ffee0h ffeffh fff00h fff1fh fff20h ffe1fh ffe20h fffffh 1ffffh 20000h extended special function register (2nd sfr) 2 kb reserved fdeffh fdf00h
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 88 jun 20, 2011 3.2 processor registers the 78k0r/lx3 microcontrollers products inco rporate the following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 20-bit regist er that holds the address information of the next program to be executed. in normal operation, pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, imme diate data and register contents are set. reset signal generation sets the reset vector table val ues at addresses 0000h and 0001h to the program counter. figure 3-8. format of program counter 19 pc 0 (2) program status word (psw) the program status word is an 8-bit r egister consisting of various flags set/reset by instruction execution. program status word contents are stored in the stack area upon interr upt request generation or push psw instruction execution and are re stored upon execution of the retb , reti and pop psw instructions. reset signal generation sets psw to 06h. figure 3-9. format of program status word ie z rbs1 ac rbs0 isp0 cy 70 isp1 psw (a) interrupt enable flag (ie) this flag controls the interrupt reques t acknowledge operations of the cpu. when 0, the ie flag is set to the interrupt disabled (di) state, and all maskable interrupt requests are disabled. when 1, the ie flag is set to the interrupt enabled (ei) state and interrupt request a cknowledgment is controlled with an in-service priority flag (isp1, isp0), an interrupt mask flag for various interrupt sources, and a priority specification flag. the ie flag is reset (0) upon di instruction executio n or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0 ) in all other cases. (c) register bank select flags (rbs0, rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information that indicates the re gister bank selected by sel rbn instruction execution is stored.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 89 jun 20, 2011 (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flags (isp1, isp0) this flag manages the priority of acknowledgeable maskabl e vectored interrupts. vectored interrupt requests specified lower than the value of isp0 and isp1 by a priority specificatio n flag register (prn0l, prn0h, prn1l, prn1h, prn2l, prn2h) (see 19.3 (3) ) can not be acknowledged. actual re quest acknowledgment is controlled by the interrupt enable flag (ie). remark n = 0, 1 (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit a ccumulator during bit operation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the st art address of the memory stack area. only the internal ram area can be set as the stack area. figure 3-10. format of stack pointer 15 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 the sp is decremented ahead of write (s ave) to the stack memory and is incr emented after read (restored) from the stack memory. each stack operation saves data as shown in figure 3-11. cautions 1. since reset signal gene ration makes the sp contents undefined, be sure to initialize the sp before using the stack. 2. it is prohibited to use the general-purpose register (ffee0 h to ffeffh) space as a stack area. 3. while using the self-programming function, th e area of ffe20h to ffeffh cannot be used as a stack memory.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 90 jun 20, 2011 figure 3-11. data to be saved to stack memory pc7 to pc0 pc15 to pc8 pc19 to pc16 psw interrupt, brk instruction sp sp ? 4 sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp call, callt instructions register pair lower register pair higher push rp instruction sp sp ? 2 sp ? 2 sp ? 1 sp (4-byte stack) (4-byte stack) pc7 to pc0 pc15 to pc8 pc19 to pc16 00h sp sp ? 4 sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp 00h psw push psw instruction sp sp ? 2 sp ? 2 sp ? 1 sp 3.2.2 general-purpose registers general-purpose registers are mapped at particular addresses (ffee0h to ffe ffh) of the data memory. the general- purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, and two 8-bit regi sters can also be used in a pair as a 16-bit register (ax, bc, de, and hl). these registers can be described in terms of function names (x , a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set by the cpu control instruction ( sel rbn). because of the 4- register bank configuration, an efficient program can be created by switching betwe en a register for normal processing and a register for interrupts for each bank. caution it is prohibited to u se the general-purpose register ( ffee0h to ffeffh) space for fetching instructions or as a stack area.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 91 jun 20, 2011 figure 3-12. configuration of general-purpose registers (a) function name register bank 0 register bank 1 register bank 2 register bank 3 ffeffh ffef8h ffee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing ffef0h ffee8h (b) absolute name register bank 0 register bank 1 register bank 2 register bank 3 ffeffh ffef8h ffee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing ffef0h ffee8h
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 92 jun 20, 2011 3.2.3 es and cs registers the es register is used for data access and the cs register is used to s pecify the higher address when a branch instruction is executed. the default value of the es register after reset is 0fh, and that of the cs register is 00h. figure 3-13. configuration of es and cs registers 0 0 0 0 es3 es2 es1 es0 70 es 6 5 4 3 21 0 0 0 0 cs3 cp2 cp1 cp0 70 cs 6 5 4 3 21
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 93 jun 20, 2011 3.2.4 special function registers (sfrs) unlike a general-purpose register, each sfr has a special function. sfrs are allocated to the fff00h to fffffh area. sfrs can be manipulated like general-purpo se registers, using operation, trans fer, and bit manipulation instructions. the manipulable bit units, 1, 8, and 16, depend on the sfr type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for the 1- bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler for the 8-bit manipulation instruct ion operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). when specifying an address, describe an even address. table 3-5 gives a list of the sfrs. the meani ngs of items in the table are as follows. ? symbol symbol indicating the address of a special function register . it is a reserved word in the ra78k0r, and is defined as an sfr variable using the #pragma sfr directive in t he cc78k0r. when using the ra78k0r, id78k0r-qb, and sm+ for 78k0r, symbols can be written as an instruction operand. ? r/w indicates whether the corresponding sfr can be read or written. r/w: read/write enable r: read only w: write only ? manipulable bit units ? ? indicates the manipulable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset signal generation. caution do not access addresses to which sfrs are not assigned. remark for extended sfrs (2nd sfrs), see 3.2.5 extended special function registers (2nd sfrs: 2nd special function registers) .
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 94 jun 20, 2011 table 3-5. sfr list (1/5) manipulable bit range address special function register (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/lf3 78k0r/lg3 78k0r/lh3 fff00h port register 0 p0 r/w ? 00h fff01h port register 1 p1 r/w ? 00h fff02h port register 2 p2 r/w ? 00h fff03h port register 3 p3 r/w ? 00h fff04h port register 4 p4 r/w ? 00h fff05h port register 5 p5 r/w ? 00h fff06h port register 6 p6 r/w ? 00h ? fff07h port register 7 p7 r/w ? 00h ? ? fff08h port register 8 p8 r/w ? 00h ? fff09h port register 9 p9 r/w ? 00h fff0ah port register 10 p10 r/w ? 00h fff0bh port register 11 p11 r/w ? 00h fff0ch port register 12 p12 r/w ? undefined fff0dh port register 13 p13 r/w ? 00h fff0eh port register 14 p14 r/w ? 00h fff0fh port register 15 p15 r/w ? 00h fff10h txd0/ sio00 ? ? fff11h serial data register 00 ? sdr00 r/w ? ? 0000h ? fff12h rxd0/ sio01 ? ? fff13h serial data register 01 ? sdr01 r/w ? ? 0000h ? fff14h txd3 ? fff15h serial data register 12 ? sdr12 r/w ? ? 0000h fff16h rxd3 ? fff17h serial data register 13 ? sdr13 r/w ? ? 0000h fff18h fff19h timer data register 00 tdr00 r/w ? ? 0000h fff1ah fff1bh timer data register 01 tdr01 r/w ? ? 0000h fff1eh 12-bit a/d conversion result register note adcr r ? ? 0000h fff1fh 8-bit a/d conversion result register adcrh r ? ? 00h fff20h port mode register 0 pm0 r/w ? ffh fff21h port mode register 1 pm1 r/w ? ffh fff22h port mode register 2 pm2 r/w ? ffh fff23h port mode register 3 pm3 r/w ? ffh fff24h port mode register 4 pm4 r/w ? ffh fff25h port mode register 5 pm5 r/w ? ffh fff26h port mode register 6 pm6 r/w ? ffh ? fff27h port mode register 7 pm7 r/w ? ffh ? ? note for pd78f151xa, 10-bit a/d conversion result register is applied.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 95 jun 20, 2011 table 3-5. sfr list (2/5) manipulable bit range address special function register (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/lf3 78k0r/lg3 78k0r/lh3 fff28h port mode register 8 pm8 r/w ? ffh ? fff29h port mode register 9 pm9 r/w ? ffh fff2ah port mode register 10 pm10 r/w ? ffh fff2bh port mode register 11 pm11 r/w ? ffh fff2ch port mode register 12 pm12 r/w ? ffh fff2eh port mode register 14 pm14 r/w ? feh fff2fh port mode register 15 pm15 r/w ? ffh fff30h a/d converter mode register adm r/w ? 00h fff31h analog input channel specification register ads r/w ? 00h fff32h a/d converter mode register 1 adm1 r/w ? 00h fff33h operational amplifier control register note oac r/w ? 00h fff36h analog reference voltage control register advrc r/w ? 00h fff37h key return mode register krm r/w ? 00h ? ? fff38h external interrupt rising edge enable register 0 egp0 r/w ? 00h fff39h external interrupt falling edge enable register 0 egn0 r/w ? 00h fff3ah external interrupt rising edge enable register 1 egp1 r/w ? 00h ? fff3bh external interrupt falling edge enable register 1 egn1 r/w ? 00h ? fff3ch input switch control register isc r/w ? 00h fff3eh timer input select register 0 tis0 r/w ? 00h fff3fh timer input select register 1 tis1 r/w ? 00h fff40h lcd mode register lcdmd r/w ? 00h fff41h lcd display mode register lcdm r/w ? 00h fff42h lcd clock control register 0 lcdc0 r/w ? 00h fff43h lcd boost level control register vlcd r/w ? 0fh fff44h txd1/ sio10 ? fff45h serial data register 02 ? sdr02 r/w ? ? 0000h fff46h rxd1 ? fff47h serial data register 03 ? sdr03 r/w ? ? 0000h fff48h txd2/ sio20 ? fff49h serial data register 10 ? sdr10 r/w ? ? 0000h fff4ah rxd2 ? fff4bh serial data register 11 ? sdr11 r/w ? ? 0000h fff50h iica shift register iica r/w ? ? 00h ? fff51h iica status register iics r ? 00h ? fff52h iica flag register iicf r/w ? 00h ? fff58h d/a d/a conversion value setting register 0 note dacs0 r/w ? ? 00h fff59h conversion value setting register w0 note ? dacs w0 r/w ? ? 0000h fff5ah d/a d/a conversion value setting register 1 note dacs1 r/w ? ? 00h fff5bh conversion value setting register w1 note ? dacs w1 r/w ? ? 0000h note dedicated to pd78f150xa.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 96 jun 20, 2011 table 3-5. sfr list (3/5) manipulable bit range address special function register (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/lf3 78k0r/lg3 78k0r/lh3 fff5ch d/a converter mode register dam r/w ? 00h fff64h fff65h timer data register 02 tdr02 r/w ? ? 0000h fff66h fff67h timer data register 03 tdr03 r/w ? ? 0000h fff68h fff69h timer data register 04 tdr04 r/w ? ? 0000h fff6ah fff6bh timer data register 05 tdr05 r/w ? ? 0000h fff6ch fff6dh timer data register 06 tdr06 r/w ? ? 0000h fff6eh fff6fh timer data register 07 tdr07 r/w ? ? 0000h fff70h fff71h timer data register 10 tdr10 r/w ? ? 0000h fff72h fff73h timer data register 11 tdr11 r/w ? ? 0000h fff74h fff75h timer data register 12 tdr12 r/w ? ? 0000h fff76h fff77h timer data register 13 tdr13 r/w ? ? 0000h fff90h fff91h sub-count register rsubc r ? ? 0000h fff92h second count register sec r/w ? ? 00h fff93h minute count register min r/w ? ? 00h fff94h hour count register hour r/w ? ? 12h note fff95h week count register week r/w ? ? 00h fff96h day count register day r/w ? ? 01h fff97h month count register month r/w ? ? 01h fff98h year count register year r/w ? ? 00h fff99h watch error correction register subcud r/w ? ? 00h fff9ah alarm minute register alarmwm r/w ? ? 00h fff9bh alarm hour register alarmwh r/w ? ? 12h fff9ch alarm week register alarmww r/w ? ? 00h note the value of this register is 00h if the ampm bit (bit 3 of the rtcc0 register) is set to 1 after reset.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 97 jun 20, 2011 table 3-5. sfr list (4/5) manipulable bit range address special function register (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/lf3 78k0r/lg3 78k0r/lh3 fff9dh real-time counter control register 0 rtcc0 r/w ? 00h fff9eh real-time counter control register 1 rtcc1 r/w ? 00h fff9fh real-time counter control register 2 rtcc2 r/w ? 00h fffa0h clock operation mode control register cmc r/w ? ? 00h fffa1h clock operation status control register csc r/w ? c0h fffa2h oscillation stabilization time counter status register ostc r ? 00h fffa3h oscillation stabilization time select register osts r/w ? ? 07h fffa4h clock control register ckc r/w ? 09h fffa5h clock output select register 0 cks0 r/w ? 00h fffa6h clock output select register 1 cks1 r/w ? 00h fffa8h reset control flag register resf r ? ? undefined note 1 fffa9h low-voltage detection register lvim r/w ? 00h note 2 fffaah low-voltage detection level select register lvis r/w ? 0eh note 3 fffabh watchdog timer enable register wdte r/w ? ? 1a/9a note 4 fffb0h dma sfr address register 0 dsa0 r/w ? ? 00h fffb1h dma sfr address register 1 dsa1 r/w ? ? 00h fffb2h dma ram address register 0l dra0l r/w ? 00h fffb3h dma ram address register 0h dra0h dra0 r/w ? 00h fffb4h dma ram address register 1l dra1l r/w ? 00h fffb5h dma ram address register 1h dra1h dra1 r/w ? 00h fffb6h dma byte count register 0l dbc0l r/w ? 00h fffb7h dma byte count register 0h dbc0h dbc0 r/w ? 00h fffb8h dma byte count register 1l dbc1l r/w ? 00h fffb9h dma byte count register 1h dbc1h dbc1 r/w ? 00h fffbah dma mode control register 0 dmc0 r/w ? 00h fffbbh dma mode control register 1 dmc1 r/w ? 00h fffbch dma operation control register 0 drc0 r/w ? 00h fffbdh dma operation control register 1 drc1 r/w ? 00h fffbeh back ground event control register bectl r/w ? 00h fffc0h ? pfcmd note 5 ? ? ? ? undefined fffc2h ? pfs note 5 ? ? ? ? undefined fffc4h ? flpmc note 5 ? ? ? ? undefined notes 1. the reset value of resf varies depending on the reset source. 2. the reset value of lvim varies depending on the reset source and the setting of the option byte. 3. the reset value of lvis varies depending on the reset source. 4. the reset value of wdte is determined by the setting of the option byte. 5. do not directly operate this sfr, because it is to be used in the self programming library.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 98 jun 20, 2011 table 3-5. sfr list (5/5) manipulable bit range address special function register (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/lf3 78k0r/lg3 78k0r/lh3 fffd0h if2l fffd1h interrupt request flag register 2 if2h if2 r/w 0000h fffd4h mk2l fffd5h interrupt mask flag register 2 mk2h mk2 r/w ffffh fffd8h pr02l fffd9h priority specificati on flag register 02 pr02h pr02 r/w ffffh fffdch pr12l fffddh priority specificati on flag register 12 pr12h pr12 r/w ffffh fffe0h interrupt request flag register 0l if0l r/w 00h fffe1h interrupt request flag register 0h if0h if0 r/w 00h fffe2h interrupt request flag register 1l if1l r/w 00h fffe3h interrupt request flag register 1h if1h if1 r/w 00h fffe4h interrupt mask flag register 0l mk0l mk0 r/w ffh fffe5h interrupt mask flag register 0h mk0h r/w ffh fffe6h interrupt mask flag register 1l mk1l r/w ffh fffe7h interrupt mask flag register 1h mk1h mk1 r/w ffh fffe8h priority specificati on flag register 00l pr00l r/w ffh fffe9h priority specificati on flag register 00h pr00h pr00 r/w ffh fffeah priority specificati on flag register 01l pr01l r/w ffh fffebh priority specificati on flag register 01h pr01h pr01 r/w ffh fffech priority specificati on flag register 10l pr10l r/w ffh fffedh priority specificati on flag register 10h pr10h pr10 r/w ffh fffeeh priority specificati on flag register 11l pr11l r/w ffh fffefh priority specificati on flag register 11h pr11h pr11 r/w ffh ffff0h ffff1h multiplication/division data register a (l) mdal/mula r/w ? ? 0000h ffff2h ffff3h multiplication/division data register a (h) mdah/mulb r/w ? ? 0000h ffff4h ffff5h multiplication/division data regi ster b (h) mdbh/muloh r/w ? ? 0000h ffff6h ffff7h multiplication/division data regi ster b (l) mdbl/mulol r/w ? ? 0000h remark for extended sfrs (2nd sfrs), see table 3-6 extended sfr (2nd sfr) list .
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 99 jun 20, 2011 3.2.5 extended special function registers (2nd sfrs: 2nd special function registers) unlike a general-purpose register, each extended sfr (2nd sfr) has a special function. extended sfrs are allocated to the f 0000h to f07ffh area. sfrs other t han those in the sfr area (fff00h to fffffh) are allocated to this area. an instruction that accesses t he extended sfr area, however, is 1 by te longer than an instruction that a ccesses the sfr area. extended sfrs can be manipulated like general-purpose regist ers, using operation, transfer, and bit manipulation instructions. the manipulable bit units, 1, 8, and 16, depe nd on the sfr type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (!addr16.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler for the 8- bit manipulation instruction operand (!addr16). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (!addr16). when specifying an address, describe an even address. table 3-6 gives a list of the ext ended sfrs. the meanings of item s in the table are as follows. ? symbol symbol indicating the address of an ex tended sfr. it is a reserved word in the ra78k0r, and is defined as an sfr variable using the #pragma sfr directive in the cc78k 0r. when using the ra78k0r, id78k0r-qb, and sm+ for 78k0r, symbols can be written as an instruction operand. ? r/w indicates whether the corresponding extended sfr can be read or written. r/w: read/write enable r: read only w: write only ? manipulable bit units ? ? indicates the manipulable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset signal generation. caution do not access addresses to which 2nd sfrs are not assigned. remark for sfrs in the sfr area, see 3.2.4 special functi on registers (sfrs) .
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 100 jun 20, 2011 table 3-6. extended sfr (2nd sfr) list (1/8) manipulable bit range address special function regi ster (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/lf3 78k0r/lg3 78k0r/lh3 f0017h a/d port configuration register adpc r/w ? ? 10h f0030h pull-up resistor option register 0 pu0 r/w ? 00h f0031h pull-up resistor option register 1 pu1 r/w ? 00h f0033h pull-up resistor option register 3 pu3 r/w ? 00h f0034h pull-up resistor option register 4 pu4 r/w ? 00h f0035h pull-up resistor option register 5 pu5 r/w ? 00h f0037h pull-up resistor option register 7 pu7 r/w ? 00h ? ? f0038h pull-up resistor option register 8 pu8 r/w ? 00h ? f0039h pull-up resistor option register 9 pu9 r/w ? 00h f003ah pull-up resistor option register 10 pu10 r/w ? 00h f003ch pull-up resistor option register 12 pu12 r/w ? 00h f003eh pull-up resistor option register 14 pu14 r/w ? 00h f0041h port input mode register 1 pim1 r/w ? 00h f0047h port input mode register 7 pim7 r/w ? 00h ? ? f0051h port output mode register 1 pom1 r/w ? 00h f0057h port output mode register 7 pom7 r/w ? 00h ? ? f0058h port output mode register 8 pom8 r/w ? 00h ? f0060h noise filter enable register 0 nfen0 r/w ? 00h f0061h noise filter enable register 1 nfen1 r/w ? 00h f0062h noise filter enable register 2 nfen2 r/w ? 00h ? ? f0080h port function register pfall r/w ? 00h f0081h segment enable register segen r/w ? 00h f00e0h f00e1h multiplication/division data register c (l) mdcl r ? ? 0000h f00e2h f00e3h multiplication/division data register c (h) mdch r ? ? 0000h f00e8h multiplication/division control register mduc r/w ? 00h f00f0h peripheral enable register 0 per0 r/w ? 00h f00f3h operation speed mode control register osmc r/w ? ? 00h f00f4h regulator mode control register rmc r/w ? ? 00h f00f6h 20 mhz internal high-speed oscillation control register dscctl r/w ? 00h f00feh bcd adjust result register bcdadj r ? ? undefined f0100h ssr00l ? ? f0101h serial status register 00 ? ssr00 r ? ? 0000h ? f0102h ssr01l ? ? f0103h serial status register 01 ? ssr01 r ? ? 0000h ? f0104h ssr02l ? f0105h serial status register 02 ? ssr02 r ? ? 0000h f0106h ssr03l ? f0107h serial status register 03 ? ssr03 r ? ? 0000h f0108h sir00l ? ? f0109h serial flag clear trigger register 00 ? sir00 r/w ? ? 0000h ?
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 101 jun 20, 2011 table 3-6. extended sfr (2nd sfr) list (2/8) manipulable bit range address special function regi ster (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/lf3 78k0r/lg3 78k0r/lh3 f010ah sir01l ? ? f010bh serial flag clear trigger register 01 ? sir01 r/w ? ? 0000h ? f010ch sir02l ? f010dh serial flag clear trigger register 02 ? sir02 r/w ? ? 0000h f010eh sir03l ? f010fh serial flag clear trigger register 03 ? sir03 r/w ? ? 0000h f0110h f0111h serial mode register 00 smr00 r/w ? ? 0020h ? f0112h f0113h serial mode register 01 smr01 r/w ? ? 0020h ? f0114h f0115h serial mode register 02 smr02 r/w ? ? 0020h f0116h f0117h serial mode register 03 smr03 r/w ? ? 0020h f0118h f0119h serial communication operation setting register 00 scr00 r/w ? ? 0087h ? f011ah f011bh serial communication operation setting register 01 scr01 r/w ? ? 0087h ? f011ch f011dh serial communication operation setting register 02 scr02 r/w ? ? 0087h f011eh f011fh serial communication operation setting register 03 scr03 r/w ? ? 0087h f0120h se0l f0121h serial channel enable status register 0 ? se0 r ? ? 0000h f0122h ss0l f0123h serial channel start register 0 ? ss0 r/w ? ? 0000h f0124h st0l f0125h serial channel stop register 0 ? st0 r/w ? ? 0000h f0126h sps0l ? f0127h serial clock select register 0 ? sps0 r/w ? ? 0000h f0128h f0129h serial output register 0 so0 r/w ? ? 0f0fh f012ah soe0l f012bh serial output enable register 0 ? soe0 r/w ? ? 0000h f0134h sol0l ? f0135h serial output level register 0 ? sol0 r/w ? ? 0000h f0140h ssr10l ? f0141h serial status register 10 ? ssr10 r ? ? 0000h f0142h ssr11l ? f0143h serial status register 11 ? ssr11 r ? ? 0000h
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 102 jun 20, 2011 table 3-6. extended sfr (2nd sfr) list (3/8) manipulable bit range address special function regi ster (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/lf3 78k0r/lg3 78k0r/lh3 f0144h ssr12l r ? f0145h serial status register 12 ? ssr12 ? ? 0000h f0146h ssr13l r ? f0147h serial status register 13 ? ssr13 ? ? 0000h f0148h sir10l ? f0149h serial flag clear trigger register 10 ? sir10 r/w ? ? 0000h f014ah sir11l ? f014bh serial flag clear trigger register 11 ? sir11 r/w ? ? 0000h f014eh sir13l ? f014fh serial flag clear trigger register 13 ? sir13 r/w ? ? 0000h f0150h f0151h serial mode register 10 smr10 r/w ? ? 0020h f0152h f0153h serial mode register 11 smr11 r/w ? ? 0020h f0154h f0155h serial mode register 12 smr12 r/w ? ? 0020h f0156h f0157h serial mode register 13 smr13 r/w ? ? 0020h f0158h f0159h serial communication operation setting register 10 scr10 r/w ? ? 0087h f015ah f015bh serial communication operation setting register 11 scr11 r/w ? ? 0087h f015ch f015dh serial communication operation setting register 12 scr12 r/w ? ? 0087h f015eh f015fh serial communication operation setting register 13 scr13 r/w ? ? 0087h f0160h se1l f0161h serial channel enable status register 1 ? se1 r ? ? 0000h f0162h ss1l f0163h serial channel start register 1 ? ss1 r/w ? ? 0000h f0164h st1l f0165h serial channel stop register 1 ? st1 r/w ? ? 0000h f0166h sps1l ? f0167h serial clock select register 1 ? sps1 r/w ? ? 0000h f0168h f0169h serial output register 1 so1 r/w ? ? 0f0fh f016ah soe1l f016bh serial output enable register 1 ? soe1 r/w ? ? 0000h
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 103 jun 20, 2011 table 3-6. extended sfr (2nd sfr) list (4/8) manipulable bit range address special function regi ster (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/lf3 78k0r/lg3 78k0r/lh3 f0174h sol1l ? f0175h serial output level register 1 ? sol1 r/w ? ? 0000h f0180h f0181h timer counter register 00 tcr00 r ? ? ffffh f0182h f0183h timer counter register 01 tcr01 r ? ? ffffh f0184h f0185h timer counter register 02 tcr02 r ? ? ffffh f0186h f0187h timer counter register 03 tcr03 r ? ? ffffh f0188h f0189h timer counter register 04 tcr04 r ? ? ffffh f018ah f018bh timer counter register 05 tcr05 r ? ? ffffh f018ch f018dh timer counter register 06 tcr06 r ? ? ffffh f018eh f018fh timer counter register 07 tcr07 r ? ? ffffh f0190h f0191h timer mode register 00 tmr00 r/w ? ? 0000h f0192h f0193h timer mode register 01 tmr01 r/w ? ? 0000h f0194h f0195h timer mode register 02 tmr02 r/w ? ? 0000h f0196h f0197h timer mode register 03 tmr03 r/w ? ? 0000h f0198h f0199h timer mode register 04 tmr04 r/w ? ? 0000h f019ah f019bh timer mode register 05 tmr05 r/w ? ? 0000h f019ch f019dh timer mode register 06 tmr06 r/w ? ? 0000h f019eh f019fh timer mode register 07 tmr07 r/w ? ? 0000h f01a0h tsr00l ? f01a1h timer status register 00 ? tsr00 r ? ? 0000h f01a2h tsr01l ? f01a3h timer status register 01 ? tsr01 r ? ? 0000h f01a4h tsr02l ? f01a5h timer status register 02 ? tsr02 r ? ? 0000h
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 104 jun 20, 2011 table 3-6. extended sfr (2nd sfr) list (5/8) manipulable bit range address special function regi ster (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/lf3 78k0r/lg3 78k0r/lh3 f01a6h tsr03l ? f01a7h timer status register 03 ? tsr03 r ? ? 0000h f01a8h tsr04l ? f01a9h timer status register 04 ? tsr04 r ? ? 0000h f01aah tsr05l ? ? f01abh timer status register 05 ? tsr05 r ? ? 0000h ? f01ach tsr06l ? ? f01adh timer status register 06 ? tsr06 r ? ? 0000h ? f01aeh tsr07l ? f01afh timer status register 07 ? tsr07 r ? ? 0000h f01b0h te0l f01b1h timer channel enable status register 0 ? te0 r ? ? 0000h f01b2h ts0l f01b3h timer channel start register 0 ? ts0 r/w ? ? 0000h f01b4h tt0l f01b5h timer channel stop register 0 ? tt0 r/w ? ? 0000h f01b6h tps0l ? f01b7h timer clock select register 0 ? tps0 r/w ? ? 0000h f01b8h to0l ? f01b9h timer output register 0 ? to0 r/w ? ? 0000h f01bah toe0l f01bbh timer output enable register 0 ? toe0 r/w ? ? 0000h f01bch tol0l ? f01bdh timer output level register 0 ? tol0 r/w ? ? 0000h f01beh tom0l ? f01bfh timer output mode register 0 ? tom0 r/w ? ? 0000h f01c0h f01c1h timer counter register 10 tcr10 r ? ? ffffh f01c2h f01c3h timer counter register 11 tcr11 r ? ? ffffh f01c4h f01c5h timer counter register 12 tcr12 r ? ? ffffh f01c6h f01c7h timer counter register 13 tcr13 r ? ? ffffh f01c8h f01c9h timer mode register 10 tmr10 r/w ? ? 0000h f01cah f01cbh timer mode register 11 tmr11 r/w ? ? 0000h f01cch f01cdh timer mode register 12 tmr12 r/w ? ? 0000h
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 105 jun 20, 2011 table 3-6. extended sfr (2nd sfr) list (6/8) manipulable bit range address special function regi ster (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/lf3 78k0r/lg3 78k0r/lh3 f01ceh f01cfh timer mode register 13 tmr13 r/w ? ? 0000h f01d0h tsr10l ? ? ? f01d1h timer status register 10 ? tsr10 r ? ? 0000h ? ? f01d2h tsr11l ? ? ? f01d3h timer status register 11 ? tsr11 r ? ? 0000h ? ? f01d4h tsr12l ? 0000h ? ? f01d5h timer status register 12 ? tsr12 r ? ? ? ? f01d6h tsr13l ? 0000h ? ? f01d7h timer status register 13 ? tsr13 r ? ? ? ? f01d8h te1l 0000h f01d9h timer channel enable status register 1 ? te1 r ? ? f01dah ts1l f01dbh timer channel start register 1 ? ts1 r/w ? ? 0000h f01dch tt1l f01ddh timer channel stop register 1 ? tt1 r/w ? ? 0000h f01deh tps1l ? f01dfh timer clock select register 1 ? tps1 r/w ? ? 0000h f01e0h to1l ? ? ? f01e1h timer output register 1 ? to1 r/w ? ? 0000h ? ? f01e2h toe1l ? ? f01e3h timer output enable register 1 ? toe1 r/w ? ? 0000h ? ? f01e4h tol1l ? ? ? f01e5h timer output level register 1 ? tol1 r/w ? ? 0000h ? ? f01e6h tom1l ? ? ? f01e7h timer output mode register 1 ? tom1 r/w ? ? 0000h ? ? f0230h iica control register 0 iicctl0 r/w ? 00h ? f0231h iica control register 1 iicctl1 r/w ? 00h ? f0232h iica low-level width setting register iicwl r/w ? ? ffh ? f0233h iica high-level width setting register iicwh r/w ? ? ffh ? f0234h slave address register sva r/w ? ? 00h ? f0400h lcd display data memory 0 seg0 r/w ? ? 00h f0401h lcd display data memory 1 seg1 r/w ? ? 00h f0402h lcd display data memory 2 seg2 r/w ? ? 00h f0403h lcd display data memory 3 seg3 r/w ? ? 00h f0404h lcd display data memory 4 seg4 r/w ? ? 00h f0405h lcd display data memory 5 seg5 r/w ? ? 00h f0406h lcd display data memory 6 seg6 r/w ? ? 00h f0407h lcd display data memory 7 seg7 r/w ? ? 00h f0408h lcd display data memory 8 seg8 r/w ? ? 00h
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 106 jun 20, 2011 table 3-6. extended sfr (2nd sfr) list (7/8) manipulable bit range address special function regi ster (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/lf3 78k0r/lg3 78k0r/lh3 f0409h lcd display data memory 9 seg9 r/w ? ? 00h f040ah lcd display data memory 10 seg10 r/w ? ? 00h f040bh lcd display data memory 11 seg11 r/w ? ? 00h f040ch lcd display data memory 12 seg12 r/w ? ? 00h f040dh lcd display data memory 13 seg13 r/w ? ? 00h f040eh lcd display data memory 14 seg14 r/w ? ? 00h f040fh lcd display data memory 15 seg15 r/w ? ? 00h f0410h lcd display data memory 16 seg16 r/w ? ? 00h f0411h lcd display data memory 17 seg17 r/w ? ? 00h f0412h lcd display data memory 18 seg18 r/w ? ? 00h f0413h lcd display data memory 19 seg19 r/w ? ? 00h f0414h lcd display data memory 20 seg20 r/w ? ? 00h f0415h lcd display data memory 21 seg21 r/w ? ? 00h f0416h lcd display data memory 22 seg22 r/w ? ? 00h f0417h lcd display data memory 23 seg23 r/w ? ? 00h f0418h lcd display data memory 24 seg24 r/w ? ? 00h f0419h lcd display data memory 25 seg25 r/w ? ? 00h f041ah lcd display data memory 26 seg26 r/w ? ? 00h f041bh lcd display data memory 27 seg27 r/w ? ? 00h f041ch lcd display data memory 28 seg28 r/w ? ? 00h f041dh lcd display data memory 29 seg29 r/w ? ? 00h f041eh lcd display data memory 30 seg30 r/w ? ? 00h f041fh lcd display data memory 31 seg31 r/w ? ? 00h ? f0420h lcd display data memory 32 seg32 r/w ? ? 00h ? f0421h lcd display data memory 33 seg33 r/w ? ? 00h ? f0422h lcd display data memory 34 seg34 r/w ? ? 00h ? f0423h lcd display data memory 35 seg35 r/w ? ? 00h ? f0424h lcd display data memory 36 seg36 r/w ? ? 00h ? f0425h lcd display data memory 37 seg37 r/w ? ? 00h ? f0426h lcd display data memory 38 seg38 r/w ? ? 00h ? f0427h lcd display data memory 39 seg39 r/w ? ? 00h ? f0428h lcd display data memory 40 seg40 r/w ? ? 00h ? ? f0429h lcd display data memory 41 seg41 r/w ? ? 00h ? ? f042ah lcd display data memory 42 seg42 r/w ? ? 00h ? ? f042bh lcd display data memory 43 seg43 r/w ? ? 00h ? ? f042ch lcd display data memory 44 seg44 r/w ? ? 00h ? ? f042dh lcd display data memory 45 seg45 r/w ? ? 00h ? ? f042eh lcd display data memory 46 seg46 r/w ? ? 00h ? ?
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 107 jun 20, 2011 table 3-6. extended sfr (2nd sfr) list (8/8) manipulable bit range address special function regi ster (sfr) name symbol r/w 1-bit 8-bit 16-bit after reset 78k0r/lf3 78k0r/lg3 78k0r/lh3 f042fh lcd display data memory 47 seg47 r/w ? ? 00h ? ? f0430h lcd display data memory 48 seg48 r/w ? ? 00h ? ? f0431h lcd display data memory 49 seg49 r/w ? ? 00h ? ? f0432h lcd display data memory 50 seg50 r/w ? ? 00h ? ? f0433h lcd display data memory 51 seg51 r/w ? ? 00h ? ? f0434h lcd display data memory 52 seg52 r/w ? ? 00h ? ? f0435h lcd display data memory 53 seg53 r/w ? ? 00h ? ? remark for sfrs in the sfr area, see table 3-5 sfr list .
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 108 jun 20, 2011 3.3 instruction address addressing 3.3.1 relative addressing [function] relative addressing stores in the progr am counter (pc) the result of adding a displacement value included in the instruction word (signed complement data: ? 128 to +127 or ? 32768 to +32767) to the program counter (pc)?s value (the start address of the next instruction) , and specifies the program address to be used as the branch destination. relative addressing is applied only to branch instructions. figure 3-14. outline of relative addressing op code pc displace 8/16 bits 3.3.2 immediate addressing [function] immediate addressing stores immediat e data of the instruction word in the program counter, and specifies the program address to be used as the branch destination. for immediate addressing, call !!addr20 or br !!addr20 is used to specify 20-bit addresses and call !addr16 or br !addr16 is used to specify 16-bit addresses. 0000 is set to the higher 4 bits when specifying 16-bit addresses. figure 3-15. example of call !!addr20/br !!addr20 op code pc low addr. high addr. seg addr. figure 3-16. example of call !addr16/br !addr16 op code pc s low addr. high addr. pc pc h pc l 0000
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 109 jun 20, 2011 3.3.3 table indirect addressing [function] table indirect addressing specifies a table address in the callt table area (0080h to 00bfh) with the 5-bit immediate data in the instruction word, stores the contents at t hat table address and the next address in the program counter (pc) as 16-bit data, and specifies the program addre ss. table indirect addressing is applied only for callt instructions. in the 78k0r microcontrollers, branc hing is enabled only to the 64 kb space from 00000h to 0ffffh. figure 3-17. outline of table indirect addressing low addr. high addr. 0 0000 op code 00000000 10 table address pc s pc pc h pc l memory
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 110 jun 20, 2011 3.3.4 register direct addressing [function] register direct addressing stores in the program counter (pc) the contents of a gener al-purpose register pair (ax/bc/de/hl) and cs register of the cu rrent register bank specif ied with the instruction wo rd as 20-bit data, and specifies the program address. regi ster direct addressing can be applied only to the call ax, bc, de, hl, and br ax instructions. figure 3-18. outline of register direct addressing op code pc s pc pc h pc l cs rp
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 111 jun 20, 2011 3.4 addressing for processing data addresses 3.4.1 implied addressing [function] instructions for accessing registers (such as accumulators) that have special functions ar e directly specified with the instruction word, without using any register spec ification field in the instruction word. [operand format] because implied addressing can be automatically empl oyed with an instruction, no particular operand format is necessary. implied addressing can be applied only to mulu x. figure 3-19. outline of implied addressing a register op code memory 3.4.2 register addressing [function] register addressing accesses a general-purpose register as an operand. the instruction word of 3-bit long is used to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl figure 3-20. outline of register addressing register op code memory
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 112 jun 20, 2011 3.4.3 direct addressing [function] direct addressing uses immediate data in the instruction word as an operand addre ss to directly specify the target address. [operand format] identifier description addr16 label or 16-bit immediate dat a (only the space from f0000h to fffffh is specifiable) es: addr16 label or 16-bit immediate data (higher 4- bit addresses are specified by the es register) figure 3-21. example of addr16 target memory op code memory low addr. high addr. fffffh f0000h figure 3-22. example of es:addr16 op code memory low addr. high addr. fffffh 00000h target memory es
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 113 jun 20, 2011 3.4.4 short direct addressing [function] short direct addressing directly specif ies the target addresses using 8-bit data in the instruction word. this type of addressing is applied only to the space from ffe20h to fff1fh. [operand format] identifier description saddr label, ffe20h to fff1fh immediate data, or 0fe20h to 0ff1fh immediate data (only the space from ffe20h to fff1fh is specifiable) saddrp label, ffe20h to fff1fh immediate data, or 0f e20h to 0ff1fh immediate data (even address only) (only the space from ffe20h to fff1fh is specifiable) figure 3-23. outline of short direct addressing op code memory saddr fff1fh ffe20h saddr remark saddr and saddrp are used to describe the values of addresses fe20h to ff1fh with 16-bit immediate data (higher 4 bits of actual a ddress are omitted), and the values of addresses ffe20h to fff1fh with 20- bit immediate data. regardless of whether saddr or saddrp is used, addresses within the space from ffe20h to fff1fh are specified for the memory.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 114 jun 20, 2011 3.4.5 sfr addressing [function] sfr addressing directly specifies the ta rget sfr addresses using 8-bit data in the instruction word. this type of addressing is applied only to t he space from fff00h to fffffh. [operand format] identifier description sfr sfr name sfrp 16-bit-manipulatable sf r name (even address only) figure 3-24. outline of sfr addressing op code memory sfr fffffh fff00h sfr
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 115 jun 20, 2011 3.4.6 register indirect addressing [function] register indirect addressing directly spec ifies the target addresses using the c ontents of the regist er pair specified with the instruction word as an operand address. [operand format] identifier description ? [de], [hl] (only the space from f0000h to fffffh is specifiable) ? es:[de], es:[hl] (higher 4-bit addresses are specified by the es register) figure 3-25. example of [de], [hl] target memory op code memory rp fffffh f0000h figure 3-26. example of es:[de], es:[hl] op code memory fffffh 00000h target memory es rp
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 116 jun 20, 2011 3.4.7 based addressing [function] based addressing uses the cont ents of a register pair spec ified with the instruction wo rd as a base address, and 8- bit immediate data or 16-bit immediate dat a as offset data. the sum of these values is used to specify the target address. [operand format] identifier description ? [hl + byte], [de + byte], [sp + byte] (only the space from f0000h to fffffh is specifiable) ? word[b], word[c] (only the space from f0000h to fffffh is specifiable) ? word[bc] (only the space from f0 000h to fffffh is specifiable) ? es:[hl + byte], es:[de + byte] (higher 4-bit addresses are specified by the es register) ? es:word[b], es:word[c] (higher 4-bit addresses are specified by the es register) ? es:word[bc] (higher 4-bit addresses are specified by the es register) figure 3-27. example of [sp+byte] target memory op code memory byte fffffh f0000h sp
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 117 jun 20, 2011 figure 3-28. example of [hl + byte], [de + byte] target memory op code memory byte fffffh f0000h rp (hl/de) figure 3-29. example of word[b], word[c] target memory memory fffffh f0000h r (b/c) op code low addr. high addr. figure 3-30. example of word[bc] target memory memory fffffh f0000h rp (bc) op code low addr. high addr.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 118 jun 20, 2011 figure 3-31. example of es :[hl + byte], es:[de + byte] op code byte rp (hl/de) memory fffffh 00000h target memory es figure 3-32. example of es:word[b], es:word[c] r (b/c) memory fffffh 00000h target memory es op code low addr. high addr. figure 3-33. example of es:word[bc] rp (bc) memory fffffh 00000h target memory es op code low addr. high addr.
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 119 jun 20, 2011 3.4.8 based indexed addressing [function] based indexed addressing uses the cont ents of a register pair specified wit h the instruction word as the base address, and the content of the b register or c register similarly specified wit h the instruction word as offset address. the sum of these values is used to specify the target address. [operand format] identifier description ? [hl+b], [hl+c] (only the space from f0000h to fffffh is specifiable) ? es:[hl+b], es:[hl+c] (higher 4-bit addres ses are specified by the es register) figure 3-34. example of [hl+b], [hl+c] target memory memory fffffh f0000h r (b/c) rp (hl) op code figure 3-35. example of es:[hl+b], es:[hl+c] r (b/c) op code rp (hl) es memory fffffh 00000h target memory
78k0r/lx3 chapter 3 cpu architecture r01uh0004ej0501 rev.5.01 120 jun 20, 2011 3.4.9 stack addressing [function] the stack area is indirectly address ed with the stack pointer (sp) contents. this addressing is automatically employed when the push, pop, subrouti ne call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. stack addressing is applied only to the internal ram area. [operand format] identifier description ? push ax/bc/de/hl pop ax/bc/de/hl call/callt ret brk retb (interrupt request generated) reti
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 121 jun 20, 2011 chapter 4 port functions 4.1 port functions there are four types of pin i/o buffer power supplies: av dd0 , av dd , av dd1 , ev dd1 , ev dd , and v dd . the relationship between these power supplies and the pins is shown below. table 4-1. pin i/o buffer power supplies power supply corresponding pins av dd0, av dd p20 to p27, p150 to p152, p157 av dd1, ev dd1 p110, p111 ev dd ? port pins other than p20 to p27, p110, p111, p150 to p152, p157 ? reset, flmd0 pins v dd pins other than port , reset, flmd0 pins 78k0r/lx3 products are provided with digital i/o ports, whic h enable variety of control oper ations. the functions of each port are shown in tables 4-2 to 4-4. in addition to the function as digital i/o ports, these ports have several alternate fu nctions. for details of the alternate functions, see chapter 2 pin functions .
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 122 jun 20, 2011 table 4-2. port functions (78k0r/lf3) (1/2) function name i/o function after reset alternate function p00 caph p01 capl p02 i/o port 0. 3-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port v lc3 p10 sck20/scl20 p11 si20/rxd2/sda20/ intp6 p12 so20/txd2/to02 p13 so10/txd1/to04 p14 si10/rxd1/sda10/ intp4 p15 i/o port 1. 6-bit i/o port. input/output can be specified in 1-bit units. input of p10, p11, p14 and p15 can be set to ttl buffer. output of p10 to p15 can be set to n-ch open-drain output (v dd tolerance). use of an on-chip pull-up resistor can be specified by a software setting. input port sck10/scl10/intp7 p20 ani0/amp0- note 1 p21 ani1/amp0o note 1 p22 ani2/amp0+ note 1 p23 ani3/amp1- note 1 p24 ani4/amp1o note 1 p25 ani5/amp1+ note 1 p26 i/o port 2. 7-bit i/o port. input/output can be specified in 1-bit units. digital input port ani6 p30 ti03/to00/rtc1hz/ intp1 p31 ti00/to03/rtcdiv/ rtccl/pclbuz1/ intp2 p32 ti01/to01/intp5/ pclbuz0 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti07/to07/intp3 p40 note tool0 p41 i/o port 4. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port tool1 notes 1. ampxx applies to pd78f150xa only. 2. if on-chip debugging is enabled by using an option byte, be sure to pull up the p40/tool0 pin externally.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 123 jun 20, 2011 table 4-2. port func tions (78k0r/lf3) (2/2) function name i/o function after reset alternate function p50 seg30/rxd3 p51 seg29/txd3 p52 seg28/ti02 p53 seg27/ti04 p54 to p57 i/o port 5. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg26 to seg23 p90 to p92 i/o port 9. 3-bit i/o port. inputs/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg22 to seg20 p100 i/o port 10. 1-bit i/o port. inputs/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg11 p110 ano0 note p111 i/o port 11. 2-bit i/o port. inputs/output can be specified in 1-bit units. input port ano1 note p120 i/o intp0/exlvi p121 x1 p122 x2/exclk p123 xt1 p124 input port 12. 1-bit i/o port and 4-bit input port. for only p120, input/output can be specified in 1-bit units. for only p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2 p130 output port 13. 1-bit output port. output port ? p140 to p147 i/o port 14. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg19 to seg12 p157 i/o port 15. 1-bit i/o port. input/output can be specified in 1-bit units. digital input port ani15/av refm note note anox and av refm apply to pd78f150xa only.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 124 jun 20, 2011 table 4-3. port functions (78k0r/lg3) (1/2) function name i/o function after reset alternate function p00 caph p01 capl p02 i/o port 0. 3-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port v lc3 p10 sck20/scl20 p11 si20/rxd2/sda20/ intp6 p12 so20/txd2/to02 p13 so10/txd1/to04 p14 si10/rxd1/sda10/ intp4 p15 sck10/scl10/intp7 p16 i/o port 1. 7-bit i/o port. input/output can be specified in 1-bit units. input of p10, p11, p14 and p15 can be set to ttl buffer. output of p10 to p15 can be set to n-ch open-drain output (v dd tolerance). use of an on-chip pull-up resistor can be specified by a software setting. input port ti05/to05/intp10 p20 ani0/amp0- note 1 p21 ani1/amp0o note 1 p22 ani2/amp0+ note 1 p23 ani3/amp1- note 1 p24 ani4/amp1o note 1 p25 ani5/amp1+ note 1 p26 ani6/amp2- note 1 p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. digital input port ani7/amp2o note 1 p30 ti03/to00/rtc1hz/ intp1 p31 ti00/to03/rtcdiv/ rtccl/pclbuz1/ intp2 p32 ti01/to01/intp5/ pclbuz0 p33 ti07/to07/intp3 p34 i/o port 3. 5-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti06/to06/intp8 p40 note 2 tool0 p41 i/o port 4. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port tool1 notes 1. ampxx applies to pd78f150xa only. 2. if on-chip debugging is enabled by using an option byte, be sure to pull up the p40/tool0 pin externally.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 125 jun 20, 2011 table 4-3. port functions (78k0r/lg3) (2/2) function name i/o function after reset alternate function p50 seg39/rxd3 p51 seg38/txd3 p52 seg37/ti02 p53 seg36/ti04 p54 to p57 i/o port 5. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg35 to seg32 p60 scl0 p61 i/o port 6. 2-bit i/o port. output is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port sda0 p80 sck00/intp11 p81 rxd0/si00/intp9 p82 i/o port 8. 3-bit i/o port. inputs/output can be specified in 1-bit units. output of p80 and p82 can be set to n-ch open-drain output (v dd tolerance). use of an on-chip pull-up resistor can be specified by a software setting. input port txd0/so00 p90 to p97 i/o port 9. 8-bit i/o port. inputs/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg31 to seg24 p100 i/o port 10. 1-bit i/o port. inputs/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg15 p110 ano0 note p111 i/o port 11. 2-bit i/o port. inputs/output can be specified in 1-bit units. input port ano1 note p120 i/o intp0/exlvi p121 x1 p122 x2/exclk p123 xt1 p124 input port 12. 1-bit i/o port and 4-bit input port. for only p120, input/output can be specified in 1-bit units. for only p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2 p130 output port 13. 1-bit output port. output port ? p140 to p147 i/o port 14. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg23 to seg16 p150 ani8/amp2+ note p151 ani9 p152 ani10 p157 i/o port 15. 4-bit i/o port. input/output can be specified in 1-bit units. digital input port ani15/av refm note note anox, amp2+, and av refm apply to pd78f150xa only.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 126 jun 20, 2011 table 4-4. port functions (78k0r/lh3) (1/3) function name i/o function after reset alternate function p00 caph p01 capl p02 i/o port 0. 3-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port v lc3 p10 sck20/scl20 p11 si20/rxd2/sda20/ intp6 p12 so20/txd2/to02 p13 so10/txd1/to04 p14 si10/rxd1/sda10/ intp4 p15 sck10/scl10/intp7 p16 ti05/to05/intp10 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. input of p10, p11, p14 and p15 can be set to ttl buffer. output of p10 to p15 can be set to n-ch open-drain output (v dd tolerance). use of an on-chip pull-up resistor can be specified by a software setting. input port ? p20 ani0/amp0- note 1 p21 ani1/amp0o note 1 p22 ani2/amp0+ note 1 p23 ani3/amp1- note 1 p24 ani4/amp1o note p25 ani5/amp1+ note 1 p26 ani6/amp2- note 1 p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. digital input port ani7/amp2o note 1 p30 ti03/to00/rtc1hz/ intp1 p31 ti00/to03/rtcdiv/ rtccl/pclbuz1/ intp2 p32 ti01/to01/intp5/ pclbuz0 p33 ti07/to07/intp3 p34 i/o port 3. 5-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti06/to06/intp8 p40 note 2 tool0 p41 i/o port 4. 2-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port tool1 notes 1. ampxx applies to pd78f150xa only. 2. if on-chip debugging is enabled by using an option byte, be sure to pull up the p40/tool0 pin externally.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 127 jun 20, 2011 table 4-4. port functi ons (78k0r/lh3) (2/3) function name i/o function after reset alternate function p50 seg53/rxd3 p51 seg52/txd3 p52 seg51/ti02 p53 seg50/ti04 p54 to p57 i/o port 5. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg49 to seg46 p60 scl0 p61 i/o port 6. 2-bit i/o port. output is n-ch open-drain output (6 v tolerance). input/output can be specified in 1-bit units. input port sda0 p70 to p74 kr0 to kr4 p75 kr5/sck01 p76 kr6/si01 p77 i/o port 7. 8-bit i/o port. input/output can be specified in 1-bit units. input of p75 and p76 can be set to ttl buffer. output of p75 and p77 can be set to n-ch open-drain output (v dd tolerance). use of an on-chip pull-up resistor can be specified by a software setting. input port kr7/so01 p80 sck00/intp11 p81 rxd0/si00/intp9 p82 txd0/so00 p83 ? p84 ti10/to10 p85 ti11/to11 p86 ti12/to12 p87 i/o port 8. 8-bit i/o port. inputs/output can be specified in 1-bit units. output of p80 and p82 can be set to n-ch open-drain output (v dd tolerance). use of an on-chip pull-up resistor can be specified by a software setting. input port ti13/to13 p90 to p97 i/o port 9. 8-bit i/o port. inputs/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg45 to seg38 p100 to p102 i/o port 10. 3-bit i/o port. inputs/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg29 to seg27 p110 ano0 note p111 i/o port 11. 2-bit i/o port. inputs/output can be specified in 1-bit units. input port ano1 note p120 i/o intp0/exlvi p121 x1 p122 x2/exclk p123 xt1 p124 input port 12. 1-bit i/o port and 4-bit input port. for only p120, input/output can be specified in 1-bit units. for only p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2 note anox applies to pd78f150xa only.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 128 jun 20, 2011 table 4-4. port functi ons (78k0r/lh3) (3/3) function name i/o function after reset alternate function p130 output port 13. 1-bit output port. output port ? p140 to p147 i/o port 14. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg37 to seg30 p150 ani8/amp2+ note p151 ani9 p152 ani10 p157 i/o port 15. 4-bit i/o port. input/output can be specified in 1-bit units. digital input port ani15/av refm note note amp2+ and av refm apply to pd78f150xa only.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 129 jun 20, 2011 4.2 port configuration ports include the following hardware. table 4-5. port configuration item configuration control registers ? 78k0r/lf3 port mode registers (pmx x) : pm0 to pm5, pm9 to pm12, pm14, pm15 port registers (pxx) : p0 to p5, p9 to p15 pull-up resistor option registers (puxx) : pu0, pu1, pu3 to pu5, pu9, pu10, pu12, pu14 port input mode registers (pim1) port output mode registers (pom1) a/d port configuration register (adpc) port function register (pfall) input switch control register (isc) ? 78k0r/lg3 port mode registers (pmx x) : pm0 to pm6, pm8 to pm12, pm14, pm15 port registers (pxx) : p0 to p6, p8 to p15 pull-up resistor option registers (puxx) : pu0, pu1, pu3 to pu5, pu8 to pu10, pu12, pu14 port input mode registers (pim1) port output mode registers (pom1, pom8) a/d port configuration register (adpc) port function register (pfall) input switch control register (isc) ? 78k0r/lh3 port mode register s (pmxx) : pm0 to pm12, pm14, pm15 port registers (pxx) : p0 to p15 pull-up resistor option registers (puxx) : pu0, pu1, pu3 to pu5, pu7 to pu10, pu12, pu14 port input mode regi sters (pim1, pim7) port output mode registers (pom1, pom7, pom8) a/d port configuration register (adpc) port function register (pfall) input switch control register (isc) port ? 78k0r/lf3: total: 51 (cmos i/o: 46, cmos output: 1, cmos input: 4) ? 78k0r/lg3: total: 67 (cmos i/o: 60, cmos output: 1, cmos input: 4, n-ch open drain i/o: 2) ? 78k0r/lh3: total: 83 (cmos i/o: 76, cmos output: 1, cmos input: 4, n-ch open drain i/o: 2) pull-up resistor ? 78k0r/lf3: total: 36 ? 78k0r/lg3: total: 46 ? 78k0r/lh3: total: 62
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 130 jun 20, 2011 4.2.1 port 0 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p00/caph p01/capl p02/v lc3 port 0 is an i/o port with an output latch. port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (pm0). when the p00 to p02 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (pu0). this port can also be used for connecting a capacitor for l cd controller/driver, and power supply voltage pin for driving the lcd. reset signal generation sets port 0 to input mode. figures 4-1 and 4-2 show block diagrams of port 0. caution to use p00/caph , p01/capl, and p02/v lc3 as a general-purpose port, set bit 5 (mdset1) and bit 4 (mdset0) of lcd mode register (lcdmd) to ?0?, which is the same as their default status setting.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 131 jun 20, 2011 figure 4-1. block diagram of p00 and p01 p00/caph, p01/capl wr pu rd pu0 pm0 wr port wr pm pu00, pu01 output latch (p00, p01) pm00, pm01 ev dd p-ch p0 caph, capl lcdmd mdset1, mdset0 wr lcdmd internal bus selector selector p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 lcdmd: lcd mode register rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 132 jun 20, 2011 figure 4-2. block diagram of p02 p02/v lc3 wr pu rd pu0 pm0 wr port wr pm pu02 output latch (p02) pm02 ev dd p-ch p0 lcdm lcdm0 to lcdm2 v lc3 lcdmd mdset1, mdset0 wr lcdmd wr lcdm selector selector internal bus p0: port register 0 pu0: pull-up resistor option register 0 pm0: port mode register 0 lcdm: lcd display mode register lcdmd: lcd mode register rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 133 jun 20, 2011 4.2.2 port 1 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p10/sck20/scl20 p11/si20/rxd2/sda20/intp6 p12/so20/txd2/to02 p13/so10/txd1/to04 p14/si10/rxd1/sda10/intp4 p15/sck10/scl10/intp7 p16/ti05/to05/intp10 ? p17 ? ? port 1 is an i/o port with an output latch. port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (pm1). when the p10 to p17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (pu1). input to the p10, p11, p14, and p15 pins can be specified through a normal input buffer or a ttl input buffer in 1-bit units using port input mode register 1 (pim1). output from the p10 to p15 pins can be specified as n-ch open-drain output (v dd tolerance) in 1-bit units using port output mode register 1 (pom1). this port can also be used for serial interface clock i/o, data i/o, timer i/o, and external interrupt request input,. reset signal generation sets port 1 to input mode. figures 4-3 to 4-6 show block diagrams of port 1. cautions 1. to use p10/sck20/scl2 0 and p11/si20/rxd2/sda20/intp6 as a general-purpose port, note the serial array unit 1 setting. for de tails, refer to table 14-9 relati onship between register settings and pins (channel 0 of unit 1: csi20, uart2 reception, iic20). 2. to use p12/to02/so20/txd2 as a general-purpose port, set bit 2 (to02) of timer output register 0 (to0) and bit 2 (toe02) of timer output enable re gister 0 (toe0) to ?0?, which is the same as their default status setting. and as a general-pur pose port, note the serial array unit 1 setting. for details of serial array unit 1 setting, refer to table 14-9 relationship between register settings and pins (channel 0 of unit 1: csi20, uart2 reception, iic20). 3. to use p13/to04/so10/txd1 as a general-purpose port, set bit 4 (to04) of timer output register 0 (to0) and bit 4 (toe04) of timer output enable re gister 0 (toe0) to ?0?, which is the same as their default status setting. and as a general-pur pose port, note the serial array unit 0 setting. for details of serial array unit 0 setting, refer to table 14-7 relationship between register settings and pins (channel 2 of unit 0: csi10, uart1 transmission, iic10) 4. to use p14/si10/rxd1/sda10/intp4 and p15/ sck10/scl10/intp7 as a general-purpose port, note the serial array unit 0 setting. for details, refer to table 14- 7 relationship between register settings and pins (channel 2 of unit 0: csi10, uart1 transmission, iic10) 5. to use p16/to05/ti05/intp10 as a general-purpose po rt, set bit 5 (to05) of timer output register 0 (to0) and bit 5 (toe05) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 134 jun 20, 2011 figure 4-3. block diagram of p10, p11, p14, and p15 p10/sck20/scl20, p11/si20/rxd2/sda20/intp6, p14/si10/rxd1/sda10/intp4, p15/sck10/scl10/intp7 wr pu rd wr port pu10, pu11, pu14, pu15 alternate function alternate function output latch (p10, p11, p14, p15) ev dd p-ch pu1 p1 wr pm pm1 pom10, pom11, pom14, pom15 pom1 wr pom pm10, pm11, pm14, pm15 cmos ttl pim1 pim10, pim11, pim14, pim15 wr pim selector internal bus p1: port register 1 pu1: pull-up resistor option register 1 pim1: port input mode register 1 pom1: port output mode register 1 pm1: port mode register 1 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 135 jun 20, 2011 figure 4-4. block diagram of p12 and p13 wr pu rd wr port wr pm pu12, pu13 output latch (p12, p13) pm12, pm13 p12/so20/txd2/to02, p13/so10/txd1/to04 ev dd p-ch pu1 pm1 p1 pom12, pom13 pom1 wr pom alternate function (timer) alternate function (serial interface) selector internal bus p1: port register 1 pu1: pull-up resistor option register 1 pom1: port output mode register 1 pm1: port mode register 1 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 136 jun 20, 2011 figure 4-5. block diagram of p16 p16/ti05/to05/intp10 wr pu rd wr port wr pm ev dd p-ch pu1 pm1 p1 pm16 output latch (p16) pu16 alternate function alternate function selector internal bus p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 137 jun 20, 2011 figure 4-6. block diagram of p17 rd p17 p-ch wr pu wr port wr pm pu17 output latch (p17) pm17 selector ev dd pu1 pm1 p1 internal bus p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 138 jun 20, 2011 4.2.3 port 2 pd78f150xa pd78f151xa 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) p20/ani0/amp0- p20/ani0 p21/ani1/amp0o p20/ani1 p22/ani2/amp0+ p20/ani2 p23/ani3/amp1- p20/ani3 p24/ani4/amp1o p20/ani4 p25/ani5/amp1+ p20/ani5 p26/ani6/amp2- p26/ani6 p26/ani6 p27/ani7/amp2o ? ? p27/ani7 port 2 is an i/o port with an output latch. port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (pm2). this port can also be used for a/d converte r analog input, and oper ational amplifier i/o. to use p20/ani0/amp0- to p27/ani7/amp2o as digital input pins, set them in the digital i/o mode by using the a/d port configuration register (adpc) and in the input mode by using pm2. use t hese pins starting from the lower bit. to use p20/ani0/amp0- to p27/ani7/amp 2o as digital output pins , set them in the digita l i/o mode by using adpc and in the output mode by using pm2. to use p20/ani0/amp0- to p27/ani7/amp2o as analog input pins, set them in the analog input mode by using the a/d port configuration register (adpc) and in the input mode by using pm2. use t hese pins starting from the upper bit. all p20/ani0/amp0- to p27/ani7/amp2o are set in t he digital input mode when the reset signal is generated. figures 4-7 to 4-9 show block diagrams of port 2. caution make the av dd0 pin the same potential as the ev dd or v dd pin when port 2 is used as a digital port.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 139 jun 20, 2011 table 4-6. setting functions of ani0/amp0-/p20, ani 2/amp0+/p22, ani3/amp1-/p2 3, ani5/amp1+/p25, and ani6/amp2-/p26 pins adpc register pm2 registers oaenn bit ads register ani0/amp0-/p20, ani2/amp0+/p22, ani3/amp1- /p23, ani5/amp1+/p25, and ani6/amp2-/p26 pins 0 ? digital input input mode 1 ? setting prohibited 0 ? digital output digital i/o selection output mode 1 ? setting prohibited selects ani. analog input (to be converted) 0 does not select ani. analog input (not to be converted) selects ani. setting prohibited input mode 1 does not select ani. operational amplifier input analog input selection output mode ? ? setting prohibited table 4-7. setting functions of ani1/amp0o/p 21, ani4/amp1o/p24, and ani7/amp2o/p27 pins adpc register pm2 register oaenn bit ads register ani1/amp0o/p21, ani4/amp1o/p24, and ani7/amp2o/p27 pins 0 ? digital input input mode 1 ? setting prohibited 0 ? digital output digital i/o selection output mode 1 ? setting prohibited selects ani. analog input (to be converted) 0 does not select ani. analog input (not to be converted) selects ani. operational amplifier output (to be converted) input mode 1 does not select ani. operational amplifier output (not to be converted) analog input selection output mode ? ? setting prohibited remark 78k0r/lf3: n = 0, 1 78k0r/lg3, 78k0r/lh3: n = 0 to 2
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 140 jun 20, 2011 figure 4-7. block diagra m of p20, p23, and p26 p20/ani0/amp0-, p23/ani3/amp1-, p26/ani6/amp2- rd wr port wr pm output latch (p20, p23, p26) pm20, pm23, pm26 pm2 a/d converter p2 operational amplifier (-) input selector internal bus p2: port register 2 pm2: port mode register 2 rd: read signal wr : write signal figure 4-8. block diagra m of p21, p24, and p27 p21/ani1/amp0o, p24/ani4/amp1o, p27/ani7/amp2o rd wr port wr pm output latch (p21, p24, p27) pm21, pm24, pm27 pm2 a/d converter p2 operational amplifier output internal bus selector p2: port register 2 pm2: port mode register 2 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 141 jun 20, 2011 figure 4-9. block diagram of p22 to p25 p22/ani2/amp0+, p25/ani5/amp1+ rd wr port wr pm output latch (p22, p25) pm22, pm25 pm2 a/d converter p2 operational amplifier (+) input internal bus selector p2: port register 2 pm2: port mode register 2 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 142 jun 20, 2011 4.2.4 port 3 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p30/ti03/to00/rtc1hz/ intp1 p31/ti00/to03/rtcdiv/ rtccl/pclbuz1/intp2 p32/ti01/to01/pclbuz0/ intp5 p33/ti07/to07/intp3 p34/ti06/to06/intp8 ? port 3 is an i/o port with an output latch. port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (pm3). when the p30 to p34 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (pu3). this port can also be used for timer i/o, real-time counter clock output, correction clock output, clock output/buzzer output, and external interrupt request input. reset signal generation sets port 3 to input mode. figure 4-10 shows a block diagram of port 3. cautions 1. to use p30/to00/ti03/rt c1hz/intp1 as a general-purpose port, set bit 5 (rcloe1) of real-time counter control register 0 (rtcc0), bit 0 (to00) of timer output register 0 (to0) and bit 0 (toe00) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting. 2. to use p31/to03/ti00/rtcdi v/rtccl/pclbuz1/intp2 as a general-purpose port, set bit 4 (rcloe0) of real-time counter control register 0 (rtcc0), bit 6 (rcloe2) of real-time counter control register 2 (rtcc2), bit 3 (to03) of timer output register 0 (to0), bit 3 (toe03) of timer output enable register 0 (toe0) and bit 7 of clock output select register 1 (cks1) to ?0?, which is the same as their default status setting. 3. to use p32/to01/ti01/intp5/pcl buz0 as a general-purpose port, set bit 1 (to01) of timer output register 0 (to0), bit 1 (toe01) of timer output en able register 0 (toe0) and bit 7 of clock output select register 0 (cks0) to ?0?, which is the same as their default status setting. 4. to use p33/to07/ti07/intp3 and p34/to06/ti06/intp8 as a gene ral-purpose port, set bit 7, 6 (to07, to06) of timer output regist er 0 (to0), and bit 7, 6 (toe07, toe06) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 143 jun 20, 2011 figure 4-10. block di agram of p30 to p34 p30/ti03/to00/rtc1hz/intp1, p31/ti00/to03/rtcdiv/rtccl/pclbuz1/intp2, p32/ti01/to01/pclbuz0/intp5, p33/ti07/to07/intp3, p34/ti06/to06/intp8 wr pu rd wr port wr pm ev dd p-ch pu3 pm3 p3 pm30 to pm34 output latch (p30 to p34) pu30 to pu34 alternate function alternate function selector internal bus p3: port register 3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 144 jun 20, 2011 4.2.5 port 4 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p40/tool0 p41/tool1 port 4 is an i/o port with an output latch. port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (pm4). when the p40 an d p41 pins are used as an input port, us e of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 2 (pu2) note . this port can also be used for flash memory pr ogrammer/debugger data i/o and debugger clock output. reset signal generation sets port 4 to input mode. figure 4-11 shows a block diagram of port 4. note when a tool is connected, the p40 and p41 pi ns cannot be connected to a pull-up resistor. caution when a tool is connected, th e p40 pin cannot be used as a port pin. when the on-chip debug function is used, p41 pin can be used as follows by the mode setting on the debugger. ? 1-line mode: can be used as a port (p41). ? 2-line mode: used as a tool1 pin and cannot be used as a port (p41).
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 145 jun 20, 2011 figure 4-11. block di agram of p40, p41 p40/tool0, p41/tool1 rd wr port wr pm output latch (p40, p41) pm4 p4 wr pu ev dd p-ch pu4 pm40, pm41 pu40, pu41 alternate function alternate function internal bus selector selector p4: port register 4 pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 146 jun 20, 2011 4.2.6 port 5 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p50/rxd3/segxx (xx = 30) ( xx = 39) ( xx = 53) p51/txd3/segxx ( xx = 29) ( xx = 38) ( xx = 52) p52/ti02/segxx ( xx = 28) ( xx = 37) ( xx = 51) p53/ti04/segxx ( xx = 27) ( xx = 36) ( xx = 50) p54/segxx ( xx = 26) ( xx = 35) ( xx = 49) p55/segxx ( xx = 25) ( xx = 34) ( xx = 48) p56/segxx ( xx = 24) ( xx = 33) ( xx = 47) p57/segxx ( xx = 23) ( xx = 32) ( xx = 46) port 5 is an i/o port with an output latch. port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (pm5). when the p50 to p57 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (pu5). this port can also be used for serial interface data i/o, ti mer input and segment output of lcd controller/driver. reset signal generation sets port 5 to input mode. figures 4-12 to 4-14 show block diagrams of port 5.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 147 jun 20, 2011 figure 4-12. block diagra m of p50, p52, and p53 p50/segxx/rxd3, p52/segxx/ti02, p53/segxx/ti04 rd wr port wr pm pm50, pm52, pm53 pm5 wr pu pu50, pu52, pu53 p-ch pu5 p5 ev dd output latch (p50, p52, p53) pf5l pfall wr pf lcd controller/driver wr isc isc2, isc3, isc4 isc selector selector internal bus alternate function p5: port register 5 pu5: pull-up resistor option register 5 pm5: port mode register 5 pfall: port function register isc: input switch control register rd: read signal wr : write signal remark 78k0r/lf3: p50/seg30/rxd3, p 52/seg28/ti02, p53/seg27/ti04 78k0r/lg3: p50/seg39/rxd3, p 52/seg37/ti02, p53/seg36/ti04 78k0r/lh3: p50/seg53/rxd3, p 52/seg51/ti02, p53/seg50/ti04
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 148 jun 20, 2011 figure 4-13. blo ck diagram of p51 p51/segxx/txd3 rd wr port wr pm pm51 pm5 wr pu pu51 p-ch pu5 p5 ev dd output latch (p51) pf5l pfall wr pf lcd controller/driver selector selector internal bus alternate function p5: port register 5 pu5: pull-up resistor option register 5 pm5: port mode register 5 pfall: port function register rd: read signal wr : write signal remark 78k0r/lf3: p51/seg29/txd3 78k0r/lg3: p51/seg38/txd3 78k0r/lh3: p51/seg52/txd3
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 149 jun 20, 2011 figure 4-14. block di agram of p54 to p57 p54/segxx to p57/segxx rd wr port wr pm pm54 to pm57 pm5 wr pu pu54 to pu57 p-ch pu5 p5 ev dd output latch (p54 to p57) pf5h pfall wr pf lcd controller/driver selector selector internal bus p5: port register 5 pu5: pull-up resistor option register 5 pm5: port mode register 5 pfall: port function register rd: read signal wr : write signal remark 78k0r/lf3: p54/seg26 to p57/seg23 78k0r/lg3: p54/seg35 to p57/seg32 78k0r/lh3: p54/seg53 to p57/seg50
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 150 jun 20, 2011 4.2.7 port 6 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p60/scl0 ? p61/sda0 ? port 6 is an i/o port with an output latch. port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (pm6). the output is n-ch open-drai n output (6 v tolerance). this port can also be used for serial interface data i/o and clock i/o. reset signal generation sets port 6 to input mode. figure 4-15 shows a block diagram of port 6. caution when using p60/scl0 and p61/sda0 as a general-purpose port, stop the operation of serial interface iica. figure 4-15. block diagram of p60 and p61 p60/scl0, p61/sda0 rd wr port wr pm output latch (p60, p61) pm60, pm61 pm6 p6 alternate function alternate function internal bus selector p6: port register 6 pm6: port mode register 6 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 151 jun 20, 2011 4.2.8 port 7 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p70/kr0 ? p71/kr1 ? p72/kr2 ? p73/kr3 ? p74/kr4 ? p75/sck01 ? p76/kr6/si01 ? p77/kr7/so01 ? port 7 is an i/o port with an output latch. port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (pm7). when the p70 to p77 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (pu7). input to the p75 and p76 pins can be specified through a norma l input buffer or a ttl input buffer in 1-bit units using port input mode register 7 (pim7). output from the p75 and p77 pins can be specified as n-ch open-drain output (v dd tolerance) in 1-bit units using port output mode register 7 (pom7). this port can also be used for key return input, serial interfac e clock i/o, and data i/o. reset signal generation sets port 7 to input mode. figures 4-16 to 4-19 show block diagrams of port 7. caution to use p75/sck01/kr5, p76/ si01/kr6, and p77/so01/kr7, as a gene ral-purpose port, note the serial array unit 0 setting. for details, refer to table 14- 6 relationship between regi ster settings and pins (channel 1 of unit 0: csi01, uart0 reception).
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 152 jun 20, 2011 figure 4-16. block di agram of p70 to p74 p70/kr0 to p74/kr4 wr pu rd pu7 pm7 wr port wr pm pu70 to pu74 output latch (p70 to p74) pm70 to pm74 ev dd p-ch p7 internal bus selector alternate function p7: port register 7 pu7: pull-up resistor option register 7 pm7: port mode register 7 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 153 jun 20, 2011 figure 4-17. blo ck diagram of p75 p75/kr5/sck01 wr pu rd wr port pu75 output latch (p75) ev dd p-ch pu7 p7 wr pm pm7 pom75 pom7 wr pom pm75 cmos ttl pim7 pim75 wr pim selector alternate function alternate function internal bus p7: port register 7 pu7: pull-up resistor option register 7 pim7: port input mode register 7 pom7: port output mode register 7 pm7: port mode register 7 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 154 jun 20, 2011 figure 4-18. blo ck diagram of p76 cmos ttl pim7 pim76 wr pim p76/kr6/si01 wr pu rd pu7 pm7 wr port wr pm pu76 output latch (p76) pm76 ev dd p-ch p7 selector internal bus alternate function p7: port register 7 pu7: pull-up resistor option register 7 pim7: port input mode register 7 pm7: port mode register 7 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 155 jun 20, 2011 figure 4-19. blo ck diagram of p77 p77/kr7/so01 rd wr port wr pm pu77 output latch (p77) pm77 ev dd p-ch pu77 pm7 p7 pom77 pom7 wr pom wr pu alternate function alternate function selector internal bus p7: port register 7 pu7: pull-up resistor option register 7 pom7: port output mode register 7 pm7: port mode register 7 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 156 jun 20, 2011 4.2.9 port 8 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p80/sck00/intp11 ? p81/rxd0/si00/intp9 ? p82/txd0/so00 ? p83 ? ? p84/to10/ti10 ? ? p85/to11/ti11 ? ? p86/to12/ti12 ? ? p87/to13/ti13 ? ? port 8 is an i/o port with an output latch. port 8 can be set to the input mode or output mode in 1-bit units using port mode register 8 (pm8). when the p80 to p87 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 8 (pu8). output from the p80 and p82 pins can be specified as n-ch open-drain output (v dd tolerance) in 1-bit units using port output mode register 8 (pom8). this port can also be used for serial interface clock i/o, data i/o, timer i/o, and external interrupt request input. reset signal generation sets port 8 to input mode. figures 4-20 to 4-24 show block diagrams of port 8. caution to use p80/sck00/intp11, p81/rxd0/si00/in tp9, and p82/so00/txd0, as a general-purpose port, note the serial array unit 0 setting. for details, re fer to table 14-5 relationship between register settings and pins (channel 0 of unit 0: csi00, uart0 reception).
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 157 jun 20, 2011 figure 4-20. blo ck diagram of p80 p80/sck00/intp11 rd wr port wr pm pu80 output latch (p80) pm80 ev dd p-ch pu8 pm8 p8 pom80 pom8 wr pom wr pu alternate function alternate function selector internal bus p8: port register 8 pu8: pull-up resistor option register 8 pom8: port output mode register 8 pm8: port mode register 8 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 158 jun 20, 2011 figure 4-21. blo ck diagram of p81 p81/rxd0/si00/intp9 wr pu rd pu8 pm8 wr port wr pm pu81 output latch (p81) pm81 ev dd p-ch p8 internal bus alternate function selector p8: port register 8 pu8: pull-up resistor option register 8 pm8: port mode register 8 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 159 jun 20, 2011 figure 4-22. blo ck diagram of p82 p82/txd0/so00 wr pu rd wr port wr pm pu82 output latch (p82) pm82 ev dd p-ch pu8 pm8 p8 pom82 pom8 wr pom selector alternate function internal bus p8: port register 8 pu8: pull-up resistor option register 8 pom8: port output mode register 8 pm8: port mode register 8 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 160 jun 20, 2011 figure 4-23. blo ck diagram of p83 rd p83 p-ch wr pu wr port wr pm pu83 output latch (p83) pm83 selector ev dd pu8 pm8 p8 internal bus p8: port register 8 pu8: pull-up resistor option register 8 pm8: port mode register 8 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 161 jun 20, 2011 figure 4-24. block di agram of p84 to p87 p84/ti10/to10, p85/ti11/to11, p86/ti12/to12, p87/ti13/to13 wr pu rd wr port wr pm ev dd p-ch pu8 pm8 p8 pm84 to pm87 output latch (p84 to p87) pu84 to pu87 selector alternate function alternate function internal bus p8: port register 8 pu8: pull-up resistor option register 8 pm8: port mode register 8 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 162 jun 20, 2011 4.2.10 port 9 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p90/segxx (xx = 22) (xx = 31) (xx = 45) p91/segxx (xx = 21) (xx = 30) (xx = 44) p92/segxx (xx = 20) (xx = 29) (xx = 43) p93/segxx ? (xx = 28) (xx = 42) p94/segxx ? (xx = 27) (xx = 41) p95/segxx ? (xx = 26) (xx = 40) p96/segxx ? (xx = 25) (xx = 39) p97/segxx ? (xx = 24) (xx = 38) port 9 is an i/o port with an output latch. port 9 can be set to the input mode or output mode in 1-bit units using port mode register 9 (pm9). when the p90 to p97 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 9 (pu9). this port can also be used for segment output. reset signal generation sets port 9 to input mode. figures 4-25 and 4-26 show block diagrams of port 9.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 163 jun 20, 2011 figure 4-25. block di agram of p90 to p93 p90/segxx to p93/segxx rd wr port wr pm pm90 to pm93 pm9 wr pu pu90 to pu93 p-ch pu9 p9 ev dd output latch (p90 to p93) pf9l pfall wr pf lcd controller/driver internal bus selector selector p9: port register 9 pu9: pull-up resistor option register 9 pm9: port mode register 9 pfall: port function register rd: read signal wr : write signal remark 78k0r/lf3: p90/seg22 to p92/seg20 78k0r/lg3: p90/seg31 to p93/seg28 78k0r/lh3: p90/seg45 to p93/seg42
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 164 jun 20, 2011 figure 4-26. block di agram of p94 to p97 p94/segxx to p97/segxx rd wr port wr pm pm94 to pm97 pm9 wr pu pu94 to pu97 p-ch pu9 p9 ev dd output latch (p94 to p97) pf9h pfall wr pf lcd controller/driver internal bus selector selector p9: port register 9 pu9: pull-up resistor option register 9 pm9: port mode register 9 pfall: port function register rd: read signal wr : write signal remark 78k0r/lg3: p94/seg27 to p97/seg24 78k0r/lh3: p94/seg41 to p97/seg38
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 165 jun 20, 2011 4.2.11 port 10 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p100/segxx (xx = 11) (xx = 15) (xx = 29) p101/segxx ? ? (xx = 28) p102/segxx ? ? (xx = 27) port 10 is an i/o port with an output latch. port 10 can be set to the input mode or output mode in 1-bit units using port mode register 10 (pm10). when the p100 to p102 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 10 (pu10). this port can also be used for segment output. reset signal generation sets port 10 to input mode. figure 4-27 shows a block diagram of port 10.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 166 jun 20, 2011 figure 4-27. block di agram of p100 to p102 p100/segxx to p102/segxx rd wr port wr pm pm100 to pm102 pm10 wr pu pu100 to pu102 p-ch pu10 p10 ev dd output latch (p100 to p102) pf10 pfall wr pf lcd controller/driver selector selector internal bus p10: port register 10 pu10: pull-up resistor option register 10 pm10: port mode register 10 pfall: port function register rd: read signal wr : write signal remark 78k0r/lf3: p100/seg11 78k0r/lg3: p100/seg15 78k0r/lh3: p100/seg29 to p102/seg27
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 167 jun 20, 2011 4.2.12 port 11 pd78f150xa pd78f151xa 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) p110/ano0 p110 p111/ano1 p111 port 11 is an i/o port with an output latch. port 11 can be set to the input mode or output mode in 1-bit units using port mode register 11 (pm11). this port can also be used for d/a converter analog output. reset signal generation sets port 11 to input mode. figure 4-28 shows a block diagram of port 11. caution make the av dd1 pin the same potential as the ev dd or v dd pin when port 11 is used as a digital port. figure 4-28. block di agram of p110, p111 p110/ano0, p111/ano1 rd wr port wr pm output latch (p110, p111) pm110, pm111 pm11 p11 d/a converter output dace0, dace1 dam wr dam internal bus selector selector p11: port register 11 pm11: port mode register 11 dam: d/a converter mode register rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 168 jun 20, 2011 4.2.13 port 12 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p120/intp0/exlvi p121/x1 p122/x2/exclk p123/xt1 p124/xt2 p120 is a 1-bit i/o port with an output latc h. port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (pm12). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). p121 to p124 are 4-bit input ports. this port can also be used for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonat or for subsystem clock, and external clock input for main system clock. reset signal generation sets port 12 to input mode. figures 4-29 to 4-31 show block diagrams of port 12. caution the function setting on p121 to p124 is available only once after the reset release. the port once set for connection to an oscillator cannot be used as an input port unless th e reset is performed.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 169 jun 20, 2011 figure 4-29. blo ck diagram of p120 p120/intp0/exlvi wr pu rd wr port wr pm pu120 output latch (p120) pm120 ev dd p-ch pu12 pm12 p12 selector internal bus alternate function p12: port register 12 pu12: pull-up resistor option register 12 pm12: port mode register 12 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 170 jun 20, 2011 figure 4-30. block di agram of p121 and p122 p122/x2/exclk rd exclk, oscsel cmc oscsel cmc clock generator p121/x1 rd internal bus cmc: clock operation m ode control register rd: read signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 171 jun 20, 2011 figure 4-31. block di agram of p123 and p124 p124/xt2 rd oscsels cmc oscsels cmc p123/xt1 rd clock generator internal bus cmc: clock operation m ode control register rd: read signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 172 jun 20, 2011 4.2.14 port 13 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p130 p130 is a port dedicated to 1-bit output and is provided with an output latch. figure 4-32 shows a block diagram of port 13. figure 4-32. blo ck diagram of p130 rd output latch (p130) wr port p130 p13 internal bus p13: port register 13 rd: read signal wr : write signal remark the p130 pin outputs a low level when it is used as a port function pin and a reset is effected. if p130 is set to output a high level before reset is effected, the output signal of p130 can be dummy-output as the cpu reset signal. p130 set by software reset signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 173 jun 20, 2011 4.2.15 port 14 78k0r/lf3 (80 pins: pd78f15x0a, 78f1501a, 78f15x2a) 78k0r/lg3 (100 pins: pd78f15x3a, 78f1504a, 78f15x5a) 78k0r/lh3 (128 pins: pd78f15x6a, 78f1507a, 78f15x8a) p140/segxx (xx = 19) (xx = 23) (xx = 37) p141/segxx (xx = 18) (xx = 22) (xx = 36) p142/segxx (xx = 17) (xx = 21) (xx = 35) p143/segxx (xx = 16) (xx = 20) (xx = 34) p144/segxx (xx = 15) (xx = 19) (xx = 33) p145/segxx (xx = 14) (xx = 18) (xx = 32) p146/segxx (xx = 13) (xx = 17) (xx = 31) p147/segxx (xx = 12) (xx = 16) (xx = 30) port 14 is an i/o port with an output latch. port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (pm14). when the p140 to p147 pin is used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (pu14). this port can also be used for segment output. reset signal generation sets port 14 to input mode. figures 4-33 and 4-34 show block diagrams of port 14.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 174 jun 20, 2011 figure 4-33. block di agram of p140 to p143 p140/segxx to p143/segxx rd wr port wr pm pm140 to pm143 pm14 wr pu pu140 to pu143 p-ch pu14 p14 ev dd output latch (p140 to p143) pf14l pfall wr pf lcd controller/driver internal bus selector selector p14: port register 14 pu14: pull-up resistor option register 14 pm14: port mode register 14 pfall: port function register rd: read signal wr : write signal remark 78k0r/lf3: p140/seg19 to p143/seg16 78k0r/lg3: p140/seg23 to p143/seg20 78k0r/lh3: p140/seg37 to p143/seg34
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 175 jun 20, 2011 figure 4-34. block di agram of p144 to p147 p144/segxx to p147/segxx rd wr port wr pm pm144 to pm147 pm14 wr pu pu144 to pu147 p-ch pu14 p14 ev dd output latch (p144 to p147) pf14h pfall wr pf lcd controller/driver internal bus selector selector p14: port register 14 pu14: pull-up resistor option register 14 pm14: port mode register 14 pfall: port function register rd: read signal wr : write signal remark 78k0r/lf3: p144/seg15 to p147/seg12 78k0r/lg3: p144/seg19 to p147/seg16 78k0r/lh3: p144/seg33 to p147/seg30
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 176 jun 20, 2011 4.2.16 port 15 pd78f150xa pd78f151xa 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) p150/ani8/amp2+ ? ? p150/ani8 p151/ani9 ? ? p152/ani10 ? ? p157/ani15/av refm p157/ani15 port 15 is an i/o port with an output latch. port 15 can be set to the input mode or output mode in 1-bit units using port mode register 15 (pm15). this port can also be used for a/d converter analog input, reference voltage input, and operational amplifier input. to use p150/ani8/amp2+ to p152/ani10, p157/ani15/av refm as digital input pins, set them in the digital i/o mode by using the a/d port configuration register (adpc) and in the input mode by using pm 15. use these pins starting from the lower bit. to use p150/ani8/amp2+ to p152/ani10, p157/ani15/av refm as digital output pins, set them in the digital i/o mode by using adpc and in the output mode by using pm15. all p150/ani8/amp2+ to p152/ani10, p157/ani15/av refm are set in the digital input mode when the reset signal is generated. figures 4-35 to 4-37 show block diagrams of port 15. caution make the av dd0 pin the same potential as the ev dd or v dd pin when port 15 is used as a digital port. table 4-8. setting function s of ani8/amp2+/p150 pins adpc register pm2 and pm15 registers oaenn bit ads register ani8/amp2+/p150 pins 0 ? digital input input mode 1 ? setting prohibited 0 ? digital output digital i/o selection output mode 1 ? setting prohibited selects ani. analog input (to be a/d converted) 0 does not select ani. analog input (not to be a/d converted) selects ani. setting prohibited input mode 1 does not select ani. operational amplifier input analog input selection output mode ? ? setting prohibited
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 177 jun 20, 2011 table 4-9. setting functions of ani9/p151 and ani10/am152 pins adpc register pm15 register ads register ani9/p151 and ani10/am152 pins input mode ? digital input digital i/o selection output mode ? digital output selects ani. analog input (to be a/d converted) input mode does not select ani. analog input (not to be a/d converted) analog input selection output mode ? setting prohibited table 4-10. setting functions of ani15/av refm /p157 pin adpc register pm15 register adref bit ads register ani15/av refm /p157 pin 0 ? digital input input mode 1 ? setting prohibited 0 ? digital output digital i/o selection output mode 1 ? setting prohibited selects ani. analog input (to be converted) 0 does not select ani. analog input (not to be converted) input mode 1 ? negative reference voltage input of a/d converter analog input selection output mode ? ? setting prohibited
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 178 jun 20, 2011 figure 4-35. blo ck diagram of p150 p150/ani8/amp2+ rd wr port wr pm output latch (p150) pm150 pm15 a/d converter p15 operational amplifier (+) input internal bus selector p15: port register 15 pm15: port mode register 15 rd: read signal wr : write signal figure 4-36. block di agram of p151, p152 p151/ani9, p152/ani10 rd wr port wr pm output latch (p151, p152) pm151, pm152 pm15 a/d converter p15 internal bus selector p15: port register 15 pm15: port mode register 15 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 179 jun 20, 2011 figure 4-37. blo ck diagram of p157 p157/ani15/av refm rd wr port wr pm output latch (p157) pm157 pm15 a/d converter p15 operational amplifier (-) input internal bus selector p15: port register 15 pm15: port mode register 15 rd: read signal wr : write signal
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 180 jun 20, 2011 4.3 registers controlling port function port functions are controlled by the following eight types of registers. ? port mode registers (pmxx) ? port registers (pxx) ? pull-up resistor option registers (puxx) ? port input mode registers (pimx) ? port output mode registers (pomx) ? a/d port configuration register (adpc) ? port function register (pfall) ? input switch control register (isc) (1) port mode registers (pmxx) these registers specify input or output mode for the port in 1-bit units. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 181 jun 20, 2011 figure 4-38 format of port mode register (78k0r/lf3) symbol 7 6 5 4 3 2 1 0 address after reset r/w pm0 1 1 1 1 1 pm02 pm01 pm00 fff20h ffh r/w pm1 1 1 pm15 pm14 pm13 pm12 pm11 pm10 fff21h ffh r/w pm2 1 pm26 pm25 pm24 pm23 pm22 pm21 pm20 fff22h ffh r/w pm3 1 1 1 1 pm33 pm32 pm31 pm30 fff23h ffh r/w pm4 1 1 1 1 1 1 pm41 pm40 fff24h ffh r/w pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 fff25h ffh r/w pm9 1 1 1 1 1 pm92 pm91 pm90 fff29h ffh r/w pm10 1 1 1 1 1 1 1 pm100 fff2ah ffh r/w pm11 1 1 1 1 1 1 pm111 pm110 fff2bh ffh r/w pm12 1 1 1 1 1 1 1 pm120 fff2ch ffh r/w pm14 pm147 pm146 pm145 pm144 pm143 pm142 pm141 pm140 fff2eh feh r/w pm15 pm157 1 1 1 1 1 1 1 fff2fh ffh r/w pmmn pmn pin i/o mode selection (m = 0 to 5, 9 to 12, 14, 15; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) caution be sure to set bits 3 to 7 of pm0, bits 6, 7 of pm1, bit 7 of pm2, bits 4 to 7 of pm3, bits 2 to 7 of pm4, bits 3 to 7 of pm9, bits 1 to 7 of pm10, bits 2 to 7 of pm11, bits 1 to 7 of pm12, and bits 0 to 6 of pm15 to 1.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 182 jun 20, 2011 figure 4-39 format of port mode register (78k0r/lg3) symbol 7 6 5 4 3 2 1 0 address after reset r/w pm0 1 1 1 1 1 pm02 pm01 pm00 fff20h ffh r/w pm1 1 pm16 pm15 pm14 pm13 pm12 pm11 pm10 fff21h ffh r/w pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 fff22h ffh r/w pm3 1 1 1 pm34 pm33 pm32 pm31 pm30 fff23h ffh r/w pm4 1 1 1 1 1 1 pm41 pm40 fff24h ffh r/w pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 fff25h ffh r/w pm6 1 1 1 1 1 1 pm61 pm60 fff26h ffh r/w pm8 1 1 1 1 1 pm82 pm81 pm80 fff28h ffh r/w pm9 pm97 pm96 pm95 pm94 pm93 pm92 pm91 pm90 fff29h ffh r/w pm10 1 1 1 1 1 1 1 pm100 fff2ah ffh r/w pm11 1 1 1 1 1 1 pm111 pm110 fff2bh ffh r/w pm12 1 1 1 1 1 1 1 pm120 fff2ch ffh r/w pm14 pm147 pm146 pm145 pm144 pm143 pm142 pm141 pm140 fff2eh feh r/w pm15 pm157 1 1 1 1 pm152 pm151 pm150 fff2fh ffh r/w pmmn pmn pin i/o mode selection (m = 0 to 6, 8 to 12, 14, 15; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) caution be sure to set bits 3 to 7 of pm0, bit 7 of pm1, bits 5 to 7 of pm3, bits 2 to 7 of pm4, bits 2 to 7 of pm6, bits 3 to 7 of pm8, bits 1 to 7 of pm10, bits 2 to 7 of pm11, bits 1 to 7 of pm12, and bits 3 to 6 of pm15 to 1.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 183 jun 20, 2011 figure 4-40 format of port mode register (78k0r/lh3) symbol 7 6 5 4 3 2 1 0 address after reset r/w pm0 1 1 1 1 1 pm02 pm01 pm00 fff20h ffh r/w pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 fff21h ffh r/w pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 fff22h ffh r/w pm3 1 1 1 pm34 pm33 pm32 pm31 pm30 fff23h ffh r/w pm4 1 1 1 1 1 1 pm41 pm40 fff24h ffh r/w pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 fff25h ffh r/w pm6 1 1 1 1 1 1 pm61 pm60 fff26h ffh r/w pm7 pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 fff27h ffh r/w pm8 pm87 pm86 pm85 pm84 pm83 pm82 pm81 pm80 fff28h ffh r/w pm9 pm97 pm96 pm95 pm94 pm93 pm92 pm91 pm90 fff29h ffh r/w pm10 1 1 1 1 1 pm102 pm101 pm100 fff2ah ffh r/w pm11 1 1 1 1 1 1 pm111 pm110 fff2bh ffh r/w pm12 1 1 1 1 1 1 1 pm120 fff2ch ffh r/w pm14 pm147 pm146 pm145 pm144 pm143 pm142 pm141 pm140 fff2eh feh r/w pm15 pm157 1 1 1 1 pm152 pm151 pm150 fff2fh ffh r/w pmmn pmn pin i/o mode selection (m = 0 to 12, 14, 15; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) caution be sure to set bits 3 to 7 of pm0, bits 5 to 7 of pm3, bits 2 to 7 of pm4, bits 2 to 7 of pm6, bits 3 to 7 of pm10, bits 2 to 7 of pm11, bits 1 to 7 of pm12, and bits 3 to 6 of pm15 to 1.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 184 jun 20, 2011 (2) port registers (pxx) these registers write the data t hat is output from the chip when data is output from a port. if the data is read in the input mode, the pin level is read. if it is read in the output mode, the output latch value is read note . these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. note it is always 0 and never a pin level that is read out if a port is read during the input mode when p2 and p15 are set to function as an analog input for a a/d converter , and p11 are set to function as an analog input for a d/a converter.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 185 jun 20, 2011 figure 4-41. format of port register (78k0r/lf3) symbol 7 6 5 4 3 2 1 0 address after reset r/w p0 0 0 0 0 0 p02 p01 p00 fff00h 00h (output latch) r/w p1 0 0 p15 p14 p13 p12 p11 p10 fff01h 00h (output latch) r/w p2 0 p26 p25 p24 p23 p22 p21 p20 fff02h 00h (output latch) r/w p3 0 0 0 0 p33 p32 p31 p30 fff03h 00h (output latch) r/w p4 0 0 0 0 0 0 p41 p40 fff04h 00h (output latch) r/w p5 p57 p56 p55 p54 p53 p52 p51 p50 fff05h 00h (output latch) r/w p9 0 0 0 0 0 p92 p91 p90 fff09h 00h (output latch) r/w p10 0 0 0 0 0 0 0 p100 fff0ah 00h (output latch) r/w p11 0 0 0 0 0 0 p111 p110 fff0bh 00h (output latch) r/w p12 0 0 0 p124 p123 p122 p121 p120 fff0ch undefined r/w note p13 0 0 0 0 0 0 0 p130 fff0dh 00h (output latch) r/w p14 p147 p146 p145 p144 p143 p142 p141 p140 fff0eh 00h (output latch) r/w p15 p157 0 0 0 0 0 0 0 fff0fh 00h (output latch) r/w m = 0 to 5, 9 to 15 ; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level note p121 to p124 are read-only.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 186 jun 20, 2011 figure 4-42. format of port register (78k0r/lg3) symbol 7 6 5 4 3 2 1 0 address after reset r/w p0 0 0 0 0 0 p02 p01 p00 fff00h 00h (output latch) r/w p1 0 p16 p15 p14 p13 p12 p11 p10 fff01h 00h (output latch) r/w p2 p27 p26 p25 p24 p23 p22 p21 p20 fff02h 00h (output latch) r/w p3 0 0 0 p34 p33 p32 p31 p30 fff03h 00h (output latch) r/w p4 0 0 0 0 0 0 p41 p40 fff04h 00h (output latch) r/w p5 p57 p56 p55 p54 p53 p52 p51 p50 fff05h 00h (output latch) r/w p6 0 0 0 0 0 0 p61 p60 fff06h 00h (output latch) r/w p8 0 0 0 0 0 p82 p81 p80 fff08h 00h (output latch) r/w p9 p97 p96 p95 p94 p93 p92 p91 p90 fff09h 00h (output latch) r/w p10 0 0 0 0 0 0 0 p100 fff0ah 00h (output latch) r/w p11 0 0 0 0 0 0 p111 p110 fff0bh 00h (output latch) r/w p12 0 0 0 p124 p123 p122 p121 p120 fff0ch undefined r/w note p13 0 0 0 0 0 0 0 p130 fff0dh 00h (output latch) r/w p14 p147 p146 p145 p144 p143 p142 p141 p140 fff0eh 00h (output latch) r/w p15 p157 0 0 0 0 p152 p151 p150 fff0fh 00h (output latch) r/w m = 0 to 6, 8 to 15 ; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level note p121 to p124 are read-only.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 187 jun 20, 2011 figure 4-43. format of port register (78k0r/lh3) symbol 7 6 5 4 3 2 1 0 address after reset r/w p0 0 0 0 0 0 p02 p01 p00 fff00h 00h (output latch) r/w p1 p17 p16 p15 p14 p13 p12 p11 p10 fff01h 00h (output latch) r/w p2 p27 p26 p25 p24 p23 p22 p21 p20 fff02h 00h (output latch) r/w p3 0 0 0 p34 p33 p32 p31 p30 fff03h 00h (output latch) r/w p4 0 0 0 0 0 0 p41 p40 fff04h 00h (output latch) r/w p5 p57 p56 p55 p54 p53 p52 p51 p50 fff05h 00h (output latch) r/w p6 0 0 0 0 0 0 p61 p60 fff06h 00h (output latch) r/w p7 p77 p76 p75 p74 p73 p72 p71 p70 fff07h 00h (output latch) r/w p8 p87 p86 p85 p84 p83 p82 p81 p80 fff08h 00h (output latch) r/w p9 p97 p96 p95 p94 p93 p92 p91 p90 fff09h 00h (output latch) r/w p10 0 0 0 0 0 p102 p101 p100 fff0ah 00h (output latch) r/w p11 0 0 0 0 0 0 p111 p110 fff0bh 00h (output latch) r/w p12 0 0 0 p124 p123 p122 p121 p120 fff0ch undefined r/w note p13 0 0 0 0 0 0 0 p130 fff0dh 00h (output latch) r/w p14 p147 p146 p145 p144 p143 p142 p141 p140 fff0eh 00h (output latch) r/w p15 p157 0 0 0 0 p152 p151 p150 fff0fh 00h (output latch) r/w m = 0 to 15 ; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level note p121 to p124 are read-only.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 188 jun 20, 2011 (3) pull-up resistor option registers (puxx) these registers specify whether the on-ch ip pull-up resistors are to be used or not. on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in these registers. on-chip pull-up resistor s cannot be connected to bits set to output mode and bits used as alternate-function output pins, regardl ess of the settings of these registers. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 4-44. format of pull-up resist or option register (78k0r/lf3) symbol 7 6 5 4 3 2 1 0 address after reset r/w pu0 0 0 0 0 0 pu02 pu01 pu00 f0030h 00h r/w pu1 0 0 pu15 pu14 pu13 pu12 pu11 pu10 f0031h 00h r/w pu3 0 0 0 0 pu33 pu32 pu31 pu30 f0033h 00h r/w pu4 0 0 0 0 0 0 pu41 pu40 f0034h 00h r/w pu5 pu57 pu56 pu55 pu54 pu53 pu52 pu51 pu50 f0035h 00h r/w pu9 0 0 0 0 0 pu92 pu91 pu90 f0039h 00h r/w pu10 0 0 0 0 0 0 0 pu100 f003ah 00h r/w pu12 0 0 0 0 0 0 0 pu120 f003ch 00h r/w pu14 pu147 pu146 pu145 pu144 pu143 pu142 pu141 pu140 f003eh 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 5, 9, 10, 12, 14 ; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 189 jun 20, 2011 figure 4-45. format of pull-up resist or option register (78k0r/lg3) symbol 7 6 5 4 3 2 1 0 address after reset r/w pu0 0 0 0 0 0 pu02 pu01 pu00 f0030h 00h r/w pu1 0 pu16 pu15 pu14 pu13 pu12 pu11 pu10 f0031h 00h r/w pu3 0 0 0 pu34 pu33 pu32 pu31 pu30 f0033h 00h r/w pu4 0 0 0 0 0 0 pu41 pu40 f0034h 00h r/w pu5 pu57 pu56 pu55 pu54 pu53 pu52 pu51 pu50 f0035h 00h r/w pu8 0 0 0 0 0 pu82 pu81 pu80 f0038h 00h r/w pu9 pu97 pu96 pu95 pu94 pu93 pu92 pu91 pu90 f0039h 00h r/w pu10 0 0 0 0 0 0 0 pu100 f003ah 00h r/w pu12 0 0 0 0 0 0 0 pu120 f003ch 00h r/w pu14 pu147 pu146 pu145 pu144 pu143 pu142 pu141 pu140 f003eh 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 5, 8 to 10, 12, 14 ; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 190 jun 20, 2011 figure 4-46. format of pull-up resist or option register (78k0r/lh3) symbol 7 6 5 4 3 2 1 0 address after reset r/w pu0 0 0 0 0 0 pu02 pu01 pu00 f0030h 00h r/w pu1 pu17 pu16 pu15 pu14 pu13 pu12 pu11 pu10 f0031h 00h r/w pu3 0 0 0 pu34 pu33 pu32 pu31 pu30 f0033h 00h r/w pu4 0 0 0 0 0 0 pu41 pu40 f0034h 00h r/w pu5 pu57 pu56 pu55 pu54 pu53 pu52 pu51 pu50 f0035h 00h r/w pu7 pu77 pu76 pu75 pu74 pu73 pu72 pu71 pu70 f0037h 00h r/w pu8 pu87 pu86 pu85 pu84 pu83 pu82 pu81 pu80 f0038h 00h r/w pu9 pu97 pu96 pu95 pu94 pu93 pu92 pu91 pu90 f0039h 00h r/w pu10 0 0 0 0 0 pu102 pu101 pu100 f003ah 00h r/w pu12 0 0 0 0 0 0 0 pu120 f003ch 00h r/w pu14 pu147 pu146 pu145 pu144 pu143 pu142 pu141 pu140 f003eh 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 5, 7 to 10, 12, 14 ; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 191 jun 20, 2011 (4) port input mode registers (pimx) pim1 and pim7 registers set the input buffer of p10, p11, p14, p15, p75, or p76 in 1-bit units. ttl input buffer can be selected during serial communication with an external device of the different potential. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 4-47. format of port input mode register ? 78k0r/lf3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pim1 0 0 pim15 pim14 0 0 pim11 pim10 f0041h 00h r/w ? 78k0r/lg3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pim1 0 0 pim15 pim14 0 0 pim11 pim10 f0041h 00h r/w ? 78k0r/lh3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pim1 0 0 pim15 pim14 0 0 pim11 pim10 f0041h 00h r/w pim7 0 pim76 pim75 0 0 0 0 0 f0047h 00h r/w pimmn pmn pin input buffer selection (m = 1 and 7; n = 0, 1, 4 to 6) 0 normal input buffer 1 ttl input buffer
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 192 jun 20, 2011 (5) port output mode registers (pomx) these registers set the output mode of p10 to p15, p75, p77, p80, or p82 in 1-bit units. n-ch open drain output (v dd tolerance) mode can be selected during se rial communication with an external device of the different potential, and for the sd a10, sda20 pin during simplified i 2 c communication with an external device of the same potential. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 4-48. format of port output mode register ? 78k0r/lf3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pom1 0 0 pom15 pom14 pom13 po m12 pom11 pom10 f0051h 00h r/w ? 78k0r/lg3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pom1 0 0 pom15 pom14 pom13 po m12 pom11 pom10 f0051h 00h r/w pom8 0 0 0 0 0 pom82 0 pom80 f0058h 00h r/w ? 78k0r/lh3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pom1 0 0 pom15 pom14 pom13 po m12 pom11 pom10 f0051h 00h r/w pom7 pom77 0 pom75 0 0 0 0 0 f0057h 00h r/w pom8 0 0 0 0 0 pom82 0 pom80 f0058h 00h r/w pommn pmn pin output mode selection (m = 1, 7, and 8; n = 0 to 5 and 7) 0 normal output mode 1 n-ch open-drain output (v dd tolerance) mode
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 193 jun 20, 2011 (6) a/d port configuration register (adpc) this register switches the ani0/amp0-/p20 to ani7/amp2o/p27, ani8/amp2+/p150 to ani10/p152, ani15/av refm /p157 pins to analog input or digital i/o of port. adpc can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 10h. figure 4-49. format of a/d port configuration register (adpc) address: f0017h after reset: 10h r/w symbol 7 6 5 4 3 2 1 0 adpc 0 0 0 adpc4 adpc3 adpc2 adpc1 adpc0 analog input (a)/digita l i/o (d) switching port 15 port 2 adp c4 adp c3 adp c2 adp c1 adp c0 ani15 /av refm /p157 ani10 /p152 ani9 /p151 ani8 /amp2+ /p150 ani7 /amp2o /p27 ani6 /amp2- /p26 ani5 /amp1+ /p25 ani4 /amp1o /p24 ani3 /amp1- /p23 ani2 /amp0+ /p22 ani1 /amp0o /p21 ani0 /amp0- /p20 0 0 0 0 0 a a a a a a a a a a a a 0 0 0 0 1 a a a a a a a a a a a d 0 0 0 1 0 a a a a a a a a a a d d 0 0 0 1 1 a a a a a a a a a d d d 0 0 1 0 0 a a a a a a a a d d d d 0 0 1 0 1 a a a a a a a d d d d d 0 0 1 1 0 a a a a a a d d d d d d 0 0 1 1 1 a a a a a d d d d d d d 0 1 0 0 0 a a a a d d d d d d d d 0 1 0 0 1 a a a d d d d d d d d d 0 1 0 1 0 a a d d d d d d d d d d 0 1 1 1 1 a d d d d d d d d d d d 1 0 0 0 0 d d d d d d d d d d d d other than the above setting prohibited note this setting is prohibited for 78k0r/lf3. cautions 1. set a channel to be u sed for a/d conversion in the input mode by us ing port mode registers 2 and 15 (pm2, pm15). 2. do not set the pin that is set by adpc as digital i/o by analog input channel specification register (ads). note note note note
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 194 jun 20, 2011 (7) port function register (pfall) this register sets whether to use pins p50 to p57, p90 to p97, p100 to p102, and p140 to p147 as port pins (other than segment output pins) or segment output pins. pfall is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pfall to 00h. remark the port pins to be used alternatively with the segment output pins vary, depending on the product. ? 78k0r/lf3: p50 to p57, p90 to p92, p100, p140 to p147 ? 78k0r/lg3: p50 to p57, p90 to p97, p100, p140 to p147 ? 78k0r/lh3: p50 to p57, p90 to p97, p100 to p102, p140 to p147 figure 4-50. format of port func tion register (pfall) (1/2) address: f0080h after reset : 00h r/w symbol 7 6 5 4 3 2 1 0 pfall 0 pf14h pf14l pf10 pf9h note pf9l pf5h pf5l pf14h port/segment outputs specification of the p144 to p147 pins 0 used the p144 to p147 pins as port (other than segment output) 1 used the p144 to p147 pins as segment output pf14l port/segment outputs specification of the p140 to p143 pins 0 used the p140 to p143 pins as port (other than segment output) 1 used the p140 to p143 pins as segment output pf10 port/segment outputs specification of the p100 to p102 pins 0 used the p100 to p102 pins as port (other than segment output) 1 used the p100 to p102 pins as segment output pf9h port/segment outputs specification of the p94 to p97 pins 0 used the p94 to p97 pins as port (other than segment output) 1 used the p94 to p97 pins as segment output pf9l port/segment outputs specification of p90 to p93 pins 0 used the p90 to p93 pins as port (other than segment output) 1 used the p90 to p93 pins as segment output note 78k0r/lg3, 78k0r/lh3 only
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 195 jun 20, 2011 figure 4-50. format of port func tion register (pfall) (2/2) pf5h port/segment outputs specification of the p54 to p57 pins 0 used the p54 to p57 pins as port (other than segment output) 1 used the p54 to p57 pins as segment output pf5l port/segment outputs specification of p50 to p53 pins 0 used the p50 to p53 pins as port (other than segment output) 1 used the p50 to p53 pins as segment output caution for 78k0r/lf3, bits 3 and 7 must be set to 0. for 78k0r/lg3 and 78k0r/lh3, bit 7 must be set to 0. (8) input switch control register (isc) bits 0 and 1 of isc are used for linking with an external in terrupt or a timer array unit when performing a lin-bus communication operation with uart3. when bit 0 is set to 1, the input signal of the serial data input (r x d3) pin is selected as an external interrupt (intp0) that can be used to detect a wakeup signal. when bit 1 is set to 1, the input signal of the serial data input (r x d3) pin is selected as a timer input, so that the pulse widths of a sync break field and a sync field can be measured by the timer. bits 2 to 4 of isc are used to prevent through cu rrent from entering when using the ti04/segxx/p53, ti02/segxx/p52, and rxd3/segxx/ p50 pins as segment outputs or port outputs. the segment output pins to be used al ternatively with the ti04, ti02, and rxd3 pins are internally connected with a schmitt trigger buffer. when using these pins as segment outputs or port outputs, bits 2 to 4 of isc must be set to 0 (prohibiting input to schmitt trigger buffers) in order to prevent through current from entering. isc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark the segment output pins to be used alternatively with the ti02, ti04, and rxd3 pins vary, depending on the product. ? 78k0r/lf3: ti04/seg27/p53, ti02/seg28/p52, rxd3/seg30/p50 ? 78k0r/lg3: ti04/seg36/p53, ti02/seg37/p52, rxd3/seg39/p50 ? 78k0r/lh3: ti04/seg50/p53, ti02/seg51/p52, rxd3/seg53/p50
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 196 jun 20, 2011 figure 4-51. format of input s witch control register (isc) address: fff3ch after reset : 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 isc4 isc3 isc2 isc1 isc0 isc4 ti04/segxx/p53 schmitt trigger buffer control 0 disables input 1 enables input isc3 ti02/segxx/p52 schmitt trigger buffer control 0 disables input 1 enables input isc2 rxd3/segxx/p50 schmitt trigger buffer control 0 disables input 1 enables input isc1 switching channel 7 input of timer array unit 0 uses the input signal of the ti07 pin as a timer input (normal operation). 1 input signal of r x d3 pin is used as timer i nput (wakeup signal detection). isc0 switching external interrupt (intp0) input 0 uses the input signal of the intp0 pin as an external interrupt (normal operation). 1 uses the input signal of the r x d3 pin as an external interrupt (to measure the pulse widths of t he sync break field and sync field). caution be sure to clea r bits 5 to 7 to ?0?. to use the ti04/segxx/p53, ti02/segxx/ p52, and rxd3/segxx/p50 pins, set the pf5l and iscn (n = 2 to 4) bits as follows, according to the function to be used. pf5l iscn pin function 0 0 port output (default) 0 1 port input, timer input, or serial data input 1 0 segment output 1 1 setting prohibited
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 197 jun 20, 2011 4.4 port function operations port operations differ depending on whether the inpu t or output mode is set, as shown below. 4.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruct ion, and the output latch conten ts are output from the pin. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. 4.4.2 reading from i/o port (1) output mode the output latch contents ar e read by a transfer instruction. t he output latch content s do not change. (2) input mode the pin status is read by a transfer instruct ion. the output latch c ontents do not change. 4.4.3 operations on i/o port (1) output mode an operation is performed on the output latc h contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. (2) input mode the pin level is read and an operation is performed on its contents. the result of the operation is written to the output latch, but since the output buffer is off, the pin status does not change. the data of the output latch is clear ed when a reset signal is generated.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 198 jun 20, 2011 4.4.4 connecting to external device with di fferent power potential (2.5 v, 3 v) when parts of ports 1, 7, and 8 operate with v dd = 4.0 v to 5.5 v, i/o connections wit h an external devic e that operates on a 2.5v or 3 v power supply voltage are possible. regarding inputs, cmos/ttl switching is possible on a bit-by -bit basis by port input mode registers (pim1 and pim7). moreover, regarding outputs, different power potentials can be supported by switching t he output buffer to the n-ch open drain (v dd withstand voltage) by the port output m ode registers (pom1, pom7 and pom8). (1) setting procedure when using i/o pins of uart1, uart2 csi00, csi01, csi10, and csi20 functions (a) use as 2.5v or 3 v input port <1> after reset release, the port mode is the input mode (hi-z). <2> if pull-up is needed, externally pull up the pin to be used (on-chip pull-up resistor cannot be used). in case of uart1: p14 in case of uart2: p11 in case of csi01: p75, p76 in case of csi10: p15, p14 in case of csi20: p10, p11 <3> set the corresponding bit of the pimn register to 1 to switch to the ttl input buffer. <4> v ih /v il operates on a 2.5v or 3 v operating voltage. remark n = 1, 7 (b) use as 2.5v or 3 v output port <1> after reset release, the port mode changes to the input mode (hi-z). <2> pull up externally the pin to be used ( on-chip pull-up resistor cannot be used). in case of uart1: p13 in case of uart2: p12 in case of csi00: p80, p82 in case of csi01: p75, p77 in case of csi10: p15, p13 in case of csi20: p10, p12 <3> set the output latch of the corresponding port to 1. <4> set the corresponding bit of the pomn regi ster to 1 to set the n-ch open drain output (v dd withstand voltage) mode. <5> set the output mode by mani pulating the pmn register. at this time, the output data is high level, so the pin is in the hi-z state. <6> operation is done only in the low level accordi ng to the operating status of the serial array unit. remark n = 1, 7, 8
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 199 jun 20, 2011 (2) setting procedure when using i/o pi ns of simplified iic10, iic20 functions <1> after reset release, the port mode is the input mode (hi-z). <2> externally pull up the pin to be used (o n-chip pull-up resistor cannot be used). in case of simplified iic10: p14, p15 in case of simplified iic20: p11, p10 <3> set the output latch of the corresponding port to 1. <4> set the corresponding bit of the pom1 regist er to 1 to set the n-ch open drain output (v dd withstand voltage) mode. <5> set the corresponding bit of the pm 1 register to the output mode (data i/o is possible in the output mode). at this time, the output data is high level, so the pin is in the hi-z state. <6> enable the operation of the serial arra y unit and set the mode to the simplified i 2 c mode.
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 200 jun 20, 2011 4.5 settings of port mode register and output latch when using alternate function to use the alternate function of a por t pin, set the port mode register and output latch as shown in table 4-11. table 4-11. settings of port mode register a nd output latch when using alternate function (1/5) alternate function lf3 lg3 lh3 pin name function name i/o pfall (pfxxx) isc (iscx) pm p p00 caph output ? ? p01 capl output ? ? p02 v lc3 i/o ? ? input ? ? 1 sck20 output ? ? 0 1 p10 scl20 i/o ? ? 0 1 si20 input ? ? 1 rxd2 input ? ? 1 sda20 i/o ? ? 0 1 p11 intp6 input ? ? 1 so20 output ? ? 0 1 txd2 output ? ? 0 1 p12 to02 output ? ? 0 0 so10 output ? ? 0 1 txd1 output ? ? 0 1 p13 to04 output ? ? 0 0 si10 input ? ? 1 rxd1 input ? ? 1 sda10 i/o ? ? 0 1 p14 intp4 input ? ? 1 input ? ? 1 sck10 output ? ? 0 1 scl10 i/o ? ? 0 1 p15 intp7 input ? ? 1 ti05 input ? ? 1 to05 output ? ? 0 0 ? p16 intp10 input ? ? 1 remark : don?t care ? : not applicable pfall: port function register isc: input switch control register pm : port mode register p : port output latch
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 201 jun 20, 2011 table 4-11. settings of port mode register a nd output latch when using alternate function (2/5) alternate function lf3 lg3 lh3 pin name function name i/o pfall (pfxxx) isc (iscx) pm p ani0-ani5 input ? ? 1 amp0-, amp0+, amp1-, amp1+ input ? ? 1 p20 to 25 note amp0o, amp1o output ? ? 1 ani6 input ? ? 1 ? p26 note amp2- input ? ? 1 ani7 input ? ? 1 ? p27 note amp2o output ? ? 1 ti03 input ? ? 1 to00 output ? ? 0 0 rtc1hz output ? ? 0 0 p30 intp1 input ? ? 1 ti00 input ? ? 1 to03 output ? ? 0 0 rtcdiv output ? ? 0 0 rtccl output ? ? 0 0 pclbuz1 output ? ? 0 0 p31 intp2 input ? ? 1 ti01 input ? ? 1 to01 output ? ? 0 0 intp5 input ? ? 1 p32 pclbuz0 output ? ? 0 0 ti07 input ? isc1=0 1 to07 output ? ? 0 0 p33 intp3 input ? ? 1 ti06 input ? ? 1 to06 output ? ? 0 0 ? p34 intp8 input ? ? 1 note the function of the p20/ani0/amp0-, p21/an i1/amp0o, p22/ani2/amp0+, p23/ani3/amp1-, p24/ani4/amp1o, p25/ani5/amp1+, p26/ani6 pins c an be selected by using t he a/d port configuration register (adpc), port mode register 2 (pm2), analo g input channel specification register (ads), and operational amplifier control register (oac). refer to 4.2.3 port 2 . remark : don?t care ? : not applicable pfall: port function register isc: input switch control register pm : port mode register p : port output latch
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 202 jun 20, 2011 table 4-11. settings of port mode register a nd output latch when using alternate function (3/5) alternate function lf3 lg3 lh3 pin name function name i/o pfall (pfxxx) isc (iscx) pm p p40 tool0 i/o ? ? p41 tool1 output ? ? p50 note 1 rxd3 input isc2=1 note 2 1 p51 note 1 txd3 output ? 0 1 p52 note 1 ti02 input isc3=1 1 p53 note 1 ti04 input pf5l=0 isc4=1 1 ? p60 scl0 i/o ? ? 0 0 ? p61 sda0 i/o ? ? 0 0 ? ? p70 to p74 kr0 to kr4 input ? ? 1 kr5 input ? ? 1 input ? ? 1 ? ? p75 sck01 output ? ? 0 1 kr6 input ? ? 1 ? ? p76 si01 input ? ? 1 kr7 input ? ? 1 ? ? p77 so01 output ? ? 0 1 input ? ? 1 sck00 output ? ? 0 1 ? p80 intp11 input ? ? 1 rxd0 input ? ? 1 si00 input ? ? 1 ? p81 intp9 input ? ? 1 txd0 output ? ? 0 1 ? p82 so00 output ? ? 0 1 ti10 input ? ? 1 ? ? p84 to10 output ? ? 0 0 ti11 input ? ? 1 ? ? p85 to11 output ? ? 0 0 notes 1. refer to table 4-11 settings of port mode register and output latch when using alternate function (5/5) about the segment output (segxx). 2. the rxd3 input can be set as the input source of an ex ternal interrupt input (intp0) by setting isc0 = 1. the rxd3 input can be set as the inpu t source of a timer input (ti07) by setting isc1 = 1. remark : don?t care ? : not applicable pfall: port function register isc: input switch control register pm : port mode register p : port output latch
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 203 jun 20, 2011 table 4-11. settings of port mode register a nd output latch when using alternate function (4/5) alternate function lf3 lg3 lh3 pin name function name i/o pfall (pfxxx) isc (iscx) pm p ti12 input ? ? 1 ? ? p86 to12 output ? ? 0 0 ti13 input ? ? 1 ? ? p87 to13 output ? ? 0 0 p110, p111 ano0, ano1 output ? ? 0 intp0 note 1 input ? isc0 = 0 1 p120 exlvi note 1 input ? ? 1 p121 x1 note 1 ? ? ? x2 note 1 ? ? ? p122 exclk note 1 input ? ? p123 xt1 note 1 ? ? ? p124 xt2 note 1 ? ? ? ani8 input ? ? 1 ? p150 note 2 amp2+ input ? ? 1 ? p151, p152 note 2 ani9, ani10 input ? ? 1 ani15 input ? ? 1 p157 note 2 av refm input ? ? 1 notes 1. to use the p121 to p124 pins for main system clo ck resonator connection (x1, x2), subsystem clock resonator connection (xt1, xt2), or main system cloc k external clock input (exclk), the x1 oscillation mode, xt1 oscillation mode, or external clock input m ode must be set, respectively, by using the clock operation mode control register (cmc). cmc can be wri tten only once after reset release (for details, refer to 5.3 (1) clock operation mode control register (cmc) ). the reset value of cmc is 00h (both p121 to p124 are input port pins). 2. the p150/ani8/amp2+, p151/ani9 , p152/ani10, p157/ani15/av refm pins are as shown below depending on the settings of the a/d port conf iguration register (adpc), port m ode register 2 (pm2), analog input channel specification register (ads ), operational amplifier control r egister (oac), and analog reference voltage control register (advrc). refer to 4.2.16 port 15 . remark : don?t care ? : not applicable pfall: port function register isc: input switch control register pm : port mode register p : port output latch
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 204 jun 20, 2011 table 4-11. settings of port mode register a nd output latch when using alternate function (5/5) alternate function lf3 lg3 lh3 pin name function name i/o pfall (pfxxx) isc (iscx) pm p p50 note seg30 output pf5l=1 isc2 = 0 p51 note seg29 output pf5l=1 ? p52 note seg28 output pf5l=1 isc3 = 0 p53 note seg27 output pf5l=1 isc4 = 0 p54 to 57 seg26 to seg23 output pf5h=1 ? p90 to 92 seg22 to seg20 output pf9l=1 ? p140 to 143 seg19 to seg16 output pf14l=1 ? p144 to 147 seg15 to seg12 output pf14h=1 ? ? ? p100 seg11 output pf10=1 ? p50 note seg39 output pf5l=1 isc2 = 0 p51 note seg38 output pf5l=1 ? p52 note seg37 output pf5l=1 isc3 = 0 p53 note seg36 output pf5l=1 isc4 = 0 p54 to 57 seg35 to seg32 output pf5h=1 ? p90 to 93 seg31 to seg28 output pf9l=1 ? p94 to 97 seg27 to seg24 output pf9h=1 ? p140 to 143 seg23 to seg20 output pf14l=1 ? p144 to 147 seg19 to seg16 output pf14h=1 ? ? ? p100 seg15 output pf10=1 ? p50 note seg53 output pf5l=1 isc2 = 0 p51 note seg52 output pf5l=1 ? p52 note seg51 output pf5l=1 isc3 = 0 p53 note seg50 output pf5l=1 isc4 = 0 p54 to 57 seg49 to seg46 output pf5h=1 ? p90 to 93 seg45 to seg42 output pf9l=1 ? p94 to 97 seg41 to seg38 output pf9h=1 ? p140 to 143 seg37 to seg34 output pf14l=1 ? p144 to 147 seg33 to seg30 output pf14h=1 ? ? ? p100 to 102 seg29 to seg27 output pf10=1 ? note for alternate function other than the segment output (segxx), refer to table 4-11 settings of port mode register and output latch when using alternate function (3/5). remark : don?t care ? : not applicable pfall: port function register isc: input switch control register pm : port mode register p : port output latch
78k0r/lx3 chapter 4 port functions r01uh0004ej0501 rev.5.01 205 jun 20, 2011 4.6 cautions on 1-bit manipulation in struction for port register n (pn) when a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to mani pulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. when p10 is an output port, p11 to p17 are input ports (all pin statuses are high level), and the port latch value of port 1 is 00h, if the output of output port p10 is changed from low level to high level via a 1-bit manipulation instruction, the output latch value of port 1 is ffh. explanation: the targets of writing to and reading from the pn register of a port whose pmnm bit is 1 are the output latch and pin status, respectively. a 1-bit manipulation instruction is executed in t he following order in the 78k0r/lx3 microcontrollers. <1> the pn register is read in 8-bit units. <2> the targeted one bit is manipulated. <3> the pn register is written in 8-bit units. in step <1>, the output latch value (0) of p10, which is an output port, is read, while the pin statuses of p11 to p17, which are input ports, are read. if the pin statuses of p11 to p17 are high level at this time, the read value is feh. the value is changed to ffh by the manipulation in <2>. ffh is written to the output la tch by the manipulation in <3>. figure 4-52. bit manipu lation instruction (p10) low-level output 1-bit manipulation instruction (set1 p1.0) is executed for p10 bit. pin status: high-level p10 p11 to p17 port 1 output latch 00000000 high-level output pin status: high-level p10 p11 to p17 port 1 output latch 11111111 1-bit manipulation instruction for p10 bit <1> port register 1 (p1) is read in 8-bit units. ? in the case of p10, an output port, the value of the port output latch (0) is read. ? in the case of p11 to p17, input ports, the pin status (1) is read. <2> set the p10 bit to 1. <3> write the results of <2> to the output latch of port register 1 (p1) in 8-bit units.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 206 jun 20, 2011 chapter 5 clock generator 5.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following three kinds of system clo cks and clock oscillators are selectable. (1) main system clock <1> x1 oscillator this circuit oscillates a clock of f x = 2 to 20 mhz by connecting a resonator to x1 and x2. oscillation can be stopped by executing the stop inst ruction or setting of msto p (bit 7 of the clock operation status control register (csc)). <2> internal high-speed oscillator note this circuit oscillates clocks of f ih = 1 mhz (typ.) or f ih = 8 mhz (typ.). after a reset release, the cpu always starts operating with this internal high-spe ed oscillation clock. oscillation can be stopped by executing the stop instruction or setting hiostop (bit 0 of csc). <3> 20 mhz internal high-sp eed oscillation clock oscillator note this circuit oscillates a clock of f ih20 = 20 mhz (typ.). oscillation can be started by setting bit 0 (dscon) of the 20 mhz internal high-speed oscillation control register (dscctl) to 1 with v dd 2.7 v. oscillation can be stopped by setting dscon to 0. note to use the internal high-speed oscillation clock, use the option byte to set the frequency (1 mhz, 8 mhz, or 20 mhz) in advance (for details, see chapter 26 option byte ). also, the internal high- speed oscillator automatically star ts oscillating after reset release. to use the 20 mhz internal high- speed oscillator to operate the microcontroller, osc illation is started by setting bit 0 (dscon) of the 20 mhz internal high-speed oscillation control register (dscctl) to 1. an external main system clock (f ex = 2 to 20 mhz) can also be supplied from the exclk/x2/p122 pin. an external main system clock input can be di sabled by executing the stop in struction or setting of mstop. as the main system clock, a high-speed system clock (x1 clock or external main system clock) or internal high- speed oscillation clock can be selected by setting of mcm0 (bit 4 of the syst em clock control register (ckc)). remark f x : x1 clock oscillation frequency f ih : internal high-speed oscillation clock frequency f ih20 : 20 mhz internal high-speed oscillation clock frequency f ex : external main system clock frequency
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 207 jun 20, 2011 (2) subsystem clock ? xt1 clock oscillator this circuit oscillates a clock of f sub = 32.768 khz by connecting a 32.768 khz resonator to xt1 and xt2. oscillation can be stopped by se tting xtstop (bit 6 of csc). (3) internal low-speed oscillation clock (clock for watchdog timer) ? internal low-speed oscillator this circuit oscillates a clock of f il = 30 khz (typ.). the internal low-speed oscillation clock cannot be used as the cpu clock. the only hardware that operates with the internal low-speed oscillation clock is the watchdog timer. oscillation is stopped when the watchdog timer stops. remarks 1. f sub : subsystem clock frequency f il : internal low-speed oscillation clock frequency 2. the watchdog timer stops in the following cases. ? when bit 4 (wdton) of an option byte (000c0h) = 0 ? if the halt or stop instructi on is executed when bit 4 (wdton) of an option byte (000c0h) = 1 and bit 0 (wdstbyon) = 0 5.2 configuration of clock generator the clock generator includes the following hardware. table 5-1. configuration of clock generator item configuration control registers clock operation mode control register (cmc) clock operation status control register (csc) oscillation stabilization time counter status register (ostc) oscillation stabilization time select register (osts) system clock control register (ckc) 20 mhz internal high-speed oscilla tion control register (dscctl) peripheral enable registers 0 (per0) operation speed mode control register (osmc) oscillators x1 oscillator xt1 oscillator internal high-speed oscillator internal low-speed oscillator
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 208 jun 20, 2011 figure 5-1. block diag ram of clock generator xt1/p123 xt2//p124 f sub f clk css cls osts1 osts0 osts2 3 most 18 most 17 most 15 most 13 most 11 mstop stop mode signal exclk oscsel amph 3 f mx f xt x1/p121 x2/exclk /p122 f x f ex mcm0 mcs md iv2 md iv1 md iv0 cpu f main /2 5 f main /2 4 f main /2 3 f main /2 2 f main /2 f main sdiv most 10 most 9 most 8 sau1 en iica en dac en rtc en f sub /2 xtstop hiostop cls f ih f main option byte(000c1h) frqsel2, frqsel1 f ih1 f ih8 option byte(000c0h) wdton wdstbyon f il halt/stop mode signal standby control circuit (see chapter 24) halt mode stop mode normal operation mode f sub f subc f mainc adc en sau0 en tau0 en tau1 en f subc /2 internal bus clock operation mode control register (cmc) high-speed system clock oscillator crystal/ceramic oscillation external input clock internal high-speed oscillator internal high-speed oscillation (1 mhz (typ.)) internal high-speed oscillation (8 mhz (typ.)) internal low-speed oscillator internal low-speed oscillation (30 khz (typ.)) subsystem clock oscillator crystal oscillation clock operation mode control register (cmc) clock operation status control register (csc) internal bus watchdog timer real-time counter, clock output/buzzer output main system clock source selection clock output/ buzzer output prescaler prescaler selector selector selection of cpu clock and peripheral hardware clock source timer array unit 0 controller timer array unit 1 serial array unit 0 timer array unit 0 serial array unit 1 serial interface iica a/d converter, operational amplifiers, voltage reference d/a converter real-time counter peripheral enable register 0 (per0) system clock control register (ckc) oscillation stabilization time select register (osts) x1 oscillation stabilization time counter oscillation stabilization time counterstatus register (ostc) clock operation status control register (csc) sdiv oscsels amphs0 amphs1 20 mhz internal high-speed oscillation control register (dscctl) dscs dscon seldsc f ih20 20 mhz internal high-speed oscillator i nternal high-speed oscillation (20 mhz (typ.)) f ih20
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 209 jun 20, 2011 remark f x : x1 clock oscillation frequency f ih : internal high-speed oscillation clock frequency f ih1 : 1 mhz internal high-speed oscillation clock frequency f ih8 : 8 mhz internal high-speed oscillation clock frequency f ih20 : 20 mhz internal high-speed oscillation clock frequency f ex : external main system clock frequency f mx : high-speed system clock frequency f main : main system clock frequency f mainc : main system selection clock frequency f xt : xt1 clock oscillation frequency f sub : subsystem clock frequency f subc : subsystem selection clock frequency f clk : cpu/peripheral hardware clock frequency f il : internal low-speed oscillation clock frequency 5.3 registers controlling clock generator the following eight registers are us ed to control the clock generator. ? clock operation mode control register (cmc) ? clock operation status control register (csc) ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) ? system clock control register (ckc) ? 20 mhz internal high-speed oscillation control register (dscctl) ? peripheral enable register 0 (per0) ? operation speed mode control register (osmc) (1) clock operation mode control register (cmc) this register is used to set the operation mode of t he x1/p121, x2/exclk/p122, xt1/ p123, and xt2/p124 pins, and to select a gain of the oscillator. cmc can be written only once by an 8-bit memory manipulation instruction after reset release. this register can be read by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 210 jun 20, 2011 figure 5-2. format of clock operat ion mode control register (cmc) address: fffa0h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 cmc exclk oscsel 0 oscsels 0 amphs1 amphs0 amph exclk oscsel high-speed system clock pin operation mode x1/p121 pin x2/exclk/p122 pin 0 0 input port mode input port 0 1 x1 oscillation mode crystal/ceramic resonator connection 1 0 input port mode input port 1 1 external clock input mode input port external clock input oscsels subsystem clock pin operat ion mode xt1/p123 pin xt2/p124 pin 0 input port mode input port 1 xt1 oscillation mode crystal resonator connection amphs1 amphs0 xt1 oscillator oscillation mode selection 0 0 low-consumption oscillation 0 1 normal oscillation 1 0 1 1 super-low-consumption oscillation amph control of high-speed system clock oscillation frequency 0 2 mhz f mx 10 mhz 1 10 mhz < f mx 20 mhz remark f mx : high-speed system clock frequency cautions 1. cmc can be written only once after reset release, by an 8- bit memory manipulation instruction. 2. after reset release, set cmc before x1 or xt1 oscilla tion is started as set by the clock operation status control register (csc). 3. be sure to set amph to 1 if the x1 clock oscillation fr equency exceeds 10 mhz. 4. to use cmc with its initial value (00h), be su re to set it to 00h a fter releasing reset in order to prevent malfunction when a program loop occurs. 5. the xt1 oscillator is designed as a low-gain circuit for achieving low-power consumption. note the following poin ts when designing the xt1 oscillator. ? the pins and circuit board include parasi tic capacitance. therefore, confirm that there are no problems by performing osc illation evaluation on the circuit board to be actually used. ? when low-consumption oscillation or super-low-consumpt ion oscillation is selected, lower power consumption than when selecting normal oscillation can be achieved. however, in this case, the xt1 oscillati on margin is reduced, so perform sufficient oscillation evaluation of the resonator to be used for xt1 oscillation before usi ng the resonator. (cautions are continued on the next page.)
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 211 jun 20, 2011 ? keep the wiring length between the xt1 and xt2 pins and resonator as short as possible and parasitic capacitance and wire resistance as small as possible. this is particularly impor tant when super-low- consumption oscillation (amphs1 = 1) is selected. ? configure the circuit board by using ma terial with little par asitic capacitance and wire resistance. ? place a ground pattern that h as the same potential as v ss (if possible) around the xt1 oscillator. ? do not cross the signal lines between the xt1 and xt2 pins and the resonator with other signal lines. do not route the signal lines near a signal line through which a high fluctuating current flows. ? moisture absorption by the circuit boa rd and condensation on the board in a highly humid environment may cause th e impedance between the xt1 and xt2 pins to drop and disable oscillation. wh en using the circuit board in such an environment, prevent the circuit board from absorbing moisture by taking measures such as coating the circuit board. ? coat the surface of the ci rcuit board by using materi al that does not generate capacitance or leakage between the xt1 and xt2 pins. (2) clock operation status control register (csc) this register is used to control the operations of the high-speed system clock, internal high-speed oscillation clock, and subsystem clock (except the 20 mhz internal high-speed oscillation clock and internal low-speed oscillation clock). csc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to c0h. figure 5-3. format of clock operati on status control register (csc) address: fffa1h after reset: c0h r/w symbol <7> <6> 5 4 3 2 1 <0> csc mstop xtstop 0 0 0 0 0 hiostop high-speed system clock operation control mstop x1 oscillation mode external clock input mode input port mode 0 x1 oscillator operating external clock from exclk pin is valid 1 x1 oscillator stopped external clock from exclk pin is invalid ? subsystem clock operation control xtstop xt1 oscillation mode input port mode 0 xt1 oscillator operating 1 xt1 oscillator stopped ? hiostop internal high-speed oscillation clock operation control 0 internal high-speed oscillator operating 1 internal high-speed oscillator stopped caution 1. after reset release, set the clock operation mode control register (cmc) before starting x1 oscillation as set by mstop or xt1 oscillation as set by xtstop.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 212 jun 20, 2011 cautions 2. to start x1 oscillati on as set by mstop, check the osc illation stabilization time of the x1 clock by using the oscillation stabilizat ion time counter stat us register (ostc). 3. do not stop the cl ock selected for the cpu pe ripheral hardware clock (f clk ) with the osc register. 4. the setting of the flags of the register to stop clock oscillation (invalidate the external clock input) and the condition before clock o scillation is to be stopped are as follows. table 5-2. condition before stoppin g clock oscillation and flag setting clock condition befo re stopping clock (invalidating external clock input) setting of csc register flags x1 clock external main system clock cpu and peripheral hardware cl ocks operate with a clock other than the high-speed system clock. ? cls = 0 and mcs = 0 ? cls = 1 mstop = 1 subsystem clock cpu and peripheral hardware cl ocks operate with a clock other than the subsystem clock. (cls = 0) xtstop = 1 internal high-speed oscillation clock cpu and peripheral hardware cl ocks operate with a clock other than the internal high-speed oscillator clock and 20 mhz internal high-speed oscillation clock. ? cls = 0 and mcs = 1 ? cls = 1 hiostop = 1 (3) oscillation stabilization time c ounter status register (ostc) this is the register that indicates the count status of the x1 clock osci llation stabilization time counter. the x1 clock oscillation stabilization time can be checked in the following case, ? if the x1 clock starts oscillation while the internal hi gh-speed oscillation clock or subsystem clock is being used as the cpu clock. ? if the stop mode is entered and then re leased while the internal high-speed oscillation clock is being used as the cpu clock with the x1 clock oscillating. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset signal is generated, the stop instruction and mstop (bit 7 of csc register) = 1 clear ostc to 00h. remark the oscillation stabilization time counter starts counting in the following cases. ? when oscillation of the x1 clock starts (exclk, oscsel = 0, 1 mstop = 0) ? when the stop mode is released
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 213 jun 20, 2011 figure 5-4. format of oscillation stabilizati on time counter status register (ostc) address: fffa2h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc most 8 most 9 most 10 most 11 most 13 most 15 most 17 most 18 oscillation stabilization time status most 8 most 9 most 10 most 11 most 13 most 15 most 17 most 18 f x = 10 mhz f x = 20 mhz 0 0 0 0 0 0 0 0 2 8 /f x max. 25.6 s max. 12.8 s max. 1 0 0 0 0 0 0 0 2 8 /f x min. 25.6 s min. 12.8 s min. 1 1 0 0 0 0 0 0 2 9 /f x min. 51.2 s min. 25.6 s min. 1 1 1 0 0 0 0 0 2 10 /f x min. 102.4 s min. 51.2 s min. 1 1 1 1 0 0 0 0 2 11 /f x min. 204.8 s min. 102.4 s min. 1 1 1 1 1 0 0 0 2 13 /f x min. 819.2 s min. 409.6 s min. 1 1 1 1 1 1 0 0 2 15 /f x min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 1 1 0 2 17 /f x min. 13.11 ms min. 6.55 ms min. 1 1 1 1 1 1 1 1 2 18 /f x min. 26.21 ms min. 13.11 ms min. cautions 1. after the above time has elapsed, the bits are set to 1 in order from most8 and remain 1. 2. the oscillation stabilization time count er counts up to the oscillation stabilization time set by osts. in the following cases, set the oscillation stabilization time of osts to the value greater than the count value which is to be checked by the ostc register after the oscillation starts. ? if the x1 clock starts oscillation while th e internal high-speed oscillation clock or subsystem clock is being used as the cpu clock. ? if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cp u clock with the x1 clock oscillating. (note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after th e stop mode is released.) 3. the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 214 jun 20, 2011 (4) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillation stabilization wait time when the stop mode is released. when the x1 clock is selected as the cpu clock, the operat ion automatically waits for the time set using osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confi rm with ostc that the desired oscillation stabilization time has elapsed after the stop m ode is released. the oscillati on stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets osts to 07h.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 215 jun 20, 2011 figure 5-5. format of oscillation stabiliz ation time select register (osts) address: fffa3h after reset: 07h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 oscillation stabilization time selection osts2 osts1 osts0 f x = 10 mhz f x = 20 mhz 0 0 0 2 8 /f x 25.6 s setting prohibited 0 0 1 2 9 /f x 51.2 s 25.6 s 0 1 0 2 10 /f x 102.4 s 51.2 s 0 1 1 2 11 /f x 204.8 s 102.4 s 1 0 0 2 13 /f x 819.2 s 409.6 s 1 0 1 2 15 /f x 3.27 ms 1.64 ms 1 1 0 2 17 /f x 13.11 ms 6.55 ms 1 1 1 2 18 /f x 26.21 ms 13.11 ms cautions 1. to set the stop mode when the x1 clock is used as the cp u clock, set the osts register before executing the stop instruction. 2. setting the oscillation stabilization time to 20 s or less is prohibited. 3. to change the setting of the osts regist er, be sure to confirm that the counting operation of the ostc register has been completed. 4. do not change the value of the osts register during the x1 clock oscillation stabilization time. 5. the oscillation stabilization time count er counts up to the oscillation stabilization time set by osts. in the following cases, set the oscillation stabilization time of osts to the value greater than the count value which is to be checked by the ostc register after the oscillation starts. ? if the x1 clock starts oscillation while th e internal high-speed oscillation clock or subsystem clock is being used as the cpu clock. ? if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cp u clock with the x1 clock oscillating. (note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after th e stop mode is released.) 6. the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 216 jun 20, 2011 (5) system clock control register (ckc) this register is used to select a cpu/per ipheral hardware clock and a division ratio. ckc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 09h. figure 5-6. format of system clock control register (ckc) address: fffa4h after reset: 09h r/w note 1 symbol <7> <6> <5> <4> 3 2 1 0 ckc cls css mcs mcm0 sdiv mdiv2 mdiv1 mdiv0 cls status of cpu/peripheral hardware clock (f clk ) 0 main system clock (f main ) 1 subsystem clock (f sub ) mcs status of main system clock (f main ) 0 internal high-speed oscillation clock (f ih ) or 20 mhz internal high-speed oscillation clock (f ih20 ) 1 high-speed system clock (f mx ) css mcm0 sdiv mdiv2 mdiv1 mdiv0 selection of cpu/peripheral hardware clock (f clk ) 0 0 0 f ih 0 0 1 f ih /2 (default) 0 1 0 f ih /2 2 0 1 1 f ih /2 3 1 0 0 f ih /2 4 note 2 0 0 1 0 1 f ih /2 5 note 2 0 0 0 f mx 0 0 1 f mx /2 0 1 0 f mx /2 2 0 1 1 f mx /2 3 1 0 0 f mx /2 4 0 1 1 0 1 f mx /2 5 note 3 0 f sub 1 note 4 note 4 1 f sub /2 other than above setting prohibited notes 1. bits 7 and 5 are read-only. 2. setting is prohibited when f ih = 1 mhz. 3. setting is prohibited when f mx < 4 mhz. 4. changing the value of the mcm0 bit is prohibited while css is set to 1. ( remarks and cautions are listed on the next page.)
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 217 jun 20, 2011 remarks 1. f ih : internal high-speed oscillation clock frequency f ih20 : 20 mhz internal high-speed oscillation clock frequency f mx : high-speed system clock frequency f sub subsystem clock frequency 2. : don?t care cautions 1. the clock set by css, mcm0, sdiv, and mdiv2 to mdiv0 is supplied to the cpu and peripheral hardware. if the cpu clock is changed, therefore, the clock supplied to peripheral hardware (excep t the real-time counter, timer array unit (when f sub /2, f sub /4, the valid edge of ti0mn inpu t, or the valid edge of in trtci is selected as the count clock), clock output/buzzer output, and watc hdog timer) is also changed at the same time. consequently, stop each periphe ral function when changing the cpu/peripheral operati ng hardware clock. 2. if the peripheral hardware clock is used as th e subsystem clock, the operations of the a/d converter and iica are not guaranteed . for the operating characteristics of the peripheral hardware, refer to the ch apters describing the various peripheral hardware as well as chapter 31 electrical specifications. the fastest instruction can be executed in 1 clock of the cpu clock in the 78k0r /lx3 microcontrollers. therefore, the relationship between the cpu clock (f clk ) and the minimum instruction execution time is as shown in table 5-3. table 5-3. relationship between cpu clo ck and minimum instruction execution time minimum instruction execution time: 1/f clk main system clock (css = 0) high-speed system clock (mcm0 = 1) internal high-speed oscillation clock (mcm0 = 0) subsystem clock (css = 1) cpu clock (value set by the sdiv, and mdiv2 to mdiv0 bits) at 10 mhz operation at 20 mhz operation at 8 mhz (typ.) operation at 20 mhz (typ.) operation at 32.768 khz operation f main 0.1 s 0.05 s 0.125 s (typ.) 0.05 s (typ.) ? f main /2 0.2 s 0.1 s 0.25 s (typ.) (default) 0.1 s (typ.) ? f main /2 2 0.4 s 0.2 s 0.5 s (typ.) 0.2 s (typ.) ? f main /2 3 0.8 s 0.4 s 1.0 s (typ.) 0.4 s (typ.) ? f main /2 4 1.6 s 0.8 s 2.0 s (typ.) 0.8 s (typ.) ? f main /2 5 3.2 s 1.6 s 4.0 s (typ.) 1.6 s (typ.) ? f sub ? ? 30.5 s f sub /2 ? ? 61 s remark f main : main system clock frequency (f ih ,f ih20 , or f mx ) f sub : subsystem clock frequency
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 218 jun 20, 2011 (6) 20 mhz internal high-speed osc illation control register (dscctl) this register controls the 20 mhz internal high-speed oscillation clock (dsc) function. it can be used to select whether to use the 20 mhz internal high-speed oscillation clock (f ih20 ) as a peripheral hardware clock that supports 20 mhz. dscctl can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 5-7. format of 20 mhz internal high-sp eed oscillation control register (dscctl) address: f00f6h after reset: 00h r/w note symbol 7 6 5 4 <3> <2> 1 <0> dscctl 0 0 0 0 dscs seldsc 0 dscon dscs 20 mhz internal high-speed oscillation supply status flag 0 not supplied 1 supplied seldsc selection of 20 mhz internal high-speed oscillation for cpu/peripheral hardware clock (f clk ) 0 does not select 20 mhz inter nal high-speed oscillation (clock selected by ckc register is supplied to f clk ) 1 selects 20 mhz internal high-speed oscillati on (20 mhz internal hi gh-speed oscillation is supplied to f clk ) dscon 20 mhz internal hi gh-speed oscillation clock (f ih20 ) operation enable/disable 0 disables operation. 1 enables operation. note bit 3 is read-only. cautions 1. 20 mhz internal osc illation can only be used if v dd 2.7 v. 2. set seldsc when 100 s have elapsed after h aving set dscon with v dd 2.7 v. 3. the internal high-speed oscillator must be operated (hiostop = 0) when dscon = 1.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 219 jun 20, 2011 (7) peripheral enable register 0 (per0) this register is used to enable or dis able use of each peripheral hardware macr o. clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears theses registers to 00h. figure 5-8. format of peripheral en able register 0 (per0) (1/2) address: f00f0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> per0 rtcen dacen adcen iicaen note 1 sau1en sau0en tau1en tau0en rtcen control of real-time counter (rtc) input clock note 2 0 stops input clock supply. ? sfr used by the real-time counter (rtc) cannot be written. ? the real-time counter (rtc) is in the reset status. 1 supplies input clock. ? sfr used by the real-time counter (rtc) can be read and written. dacen control of d/a converter input clock 0 stops input clock supply. ? sfr used by the d/a converter cannot be written. ? the d/a converter is in the reset status. 1 supplies input clock. ? sfr used by the d/a converter can be read and written. adcen control of a/d converter, operational amplifier, and voltage reference input clock 0 stops input clock supply. ? sfr used by the a/d converter, operational amplifier, and voltage reference cannot be written. ? the a/d converter, operational amplifier, and voltage reference is in the reset status. 1 supplies input clock. ? sfr used by the a/d converter, operational amplifier, and voltage reference can be read and written. iicaen control of serial interface iica input clock 0 stops input clock supply. ? sfr used by the serial interface iica cannot be written. ? the serial interface iica is in the reset status. 1 supplies input clock. ? sfr used by the serial interface iica can be read and written. notes 1. 78k0r/lg3, 78k0r/lh3 only 2. by using rtcen, can supply and stop the clock that is used when accessing the real-time counter (rtc) from the cpu. rtcen cannot control supply of the operating clock (f sub ) to rtc.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 220 jun 20, 2011 figure 5-8. format of peripheral en able register 0 (per0) (2/2) sau1en control of serial array unit 1 input clock 0 stops input clock supply. ? sfr used by the serial array unit 1 cannot be written. ? the serial array unit is in the reset status. 1 supplies input clock. ? sfr used by the serial array unit 1 can be read and written. sau0en control of serial array unit 0 input clock 0 stops input clock supply. ? sfr used by the serial array unit 0 cannot be written. ? the serial array unit 0 is in the reset status. 1 supplies input clock. ? sfr used by the serial array unit 0 can be read and written. tau1en control of timer array unit 1 input clock 0 stops input clock supply. ? sfr used by timer array unit 1 cannot be written. ? timer array unit 1 is in the reset status. 1 supplies input clock. ? sfr used by timer array unit 1 can be read and written. tau0en control of timer array unit 0 input clock 0 stops input clock supply. ? sfr used by timer array unit 0 cannot be written. ? timer array unit 0 is in the reset status. 1 supplies input clock. ? sfr used by timer array unit 0 can be read and written.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 221 jun 20, 2011 (8) operation speed mode c ontrol register (osmc) this register is used to control the step-up circui t of the flash memory for high-speed operation. if the microcontroller operates at a lo w speed with a system clock of 10 mhz or less, the power c onsumption can be lowered by setting this register to the default value, 00h. osmc can be set by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 5-9. format of operation speed mode control register (osmc) address: f00f3h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 osmc rtclpc 0 0 0 0 0 flpc fsel rtclpc setting in subsystem clock halt mode 0 enables subsystem clock s upply to peripheral functions. (see table 21-1 operating statuses in halt mode (2/3) for the peripheral functions whose operations are enabled.) 1 stops subsystem clock supply to peripheral functions exce pt real-time counter, clock output/buzzer output, and lcd controller/driver. flpc fsel f clk frequency selection 0 0 operates at a frequency of 10 mhz or less (default). 0 1 operates at a frequency higher than 10 mhz. 1 0 operates at a frequency of 1 mhz. 1 1 setting prohibited cautions 1. write ?1? to fsel before the following two operations. ? changing the clock prior to dividing f clk to a clock other than f ih . ? operating the dma controller. 2. the cpu waits (140.5 clock (f clk )) when ?1? is written to the fsel bit. interrupt requests issued during a wait will be suspended. however, counting the oscillati on stabilization time of f x can continue even while the cpu is waiting. 3. to increase f clk to 10 mhz or higher, set f sel to ?1?, then change f clk after two or more clocks have elapsed. 4. confirm that the clock is operating at 10 mhz or less before setting fsel = 0. 5. to shift to stop mode while v dd 2.7 v, set fsel = 0 after setting f clk to 10 mhz or less. 6. the halt mode current when operating on the subsystem clock can be reduced by setting rtclpc to 1. howeve r, the clock cannot be suppl ied to peripheral functions except the real-time counter in the subsyst em clock halt mode. set bit 7 (rtcen) of per0 to 1 and bits 0 to 6 of per0 to 0 before setting the subsystem clock halt mode. 7. once flpc has been set from 0 to 1, setting it back to 0 fr om 1 other than by reset is prohibited. 8. when setting fsel to ?1?, do so while rmc = 00h. when setting flpc to ?1?, do so while rmc = 5ah.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 222 jun 20, 2011 5.4 system clock oscillator 5.4.1 x1 oscillator the x1 oscillator oscillates with a cryst al resonator or ceramic resonator (2 to 20 mhz) connected to the x1 and x2 pins. an external clock can also be input. in this case, input the clock signal to the exclk pin. to use the x1 oscillator, set bits 7 and 6 (exclk, oscsel ) of the clock operation mode control register (cmc) as follows. ? crystal or ceramic oscillation: exclk, oscsel = 0, 1 ? external clock input: exclk, oscsel = 1, 1 when the x1 oscillator is not used, set the input port mode (exclk, oscsel = 0, 0). when the pins are not used as input port pins, either, see table 2-2 to 2-4 connection of unused pins . figure 5-10 shows an example of the exte rnal circuit of the x1 oscillator. figure 5-10. example of extern al circuit of x1 oscillator (a) crystal or ceramic osc illation (b) external clock v ss x1 x2 crystal resonator or ceramic resonator exclk external clock cautions are listed on the next page. 5.4.2 xt1 oscillator the xt1 oscillator oscillates with a crystal resonator (standard: 32.768 khz) connected to the xt1 and xt2 pins. to use the xt1 oscillator, set bit 4 (oscsels) of t he clock operation mode control register (cmc) to 1. when the xt1 oscillator is not used, set the input port mode (oscsels = 0). when the pins are not used as input port pins, either, see table 2-2 to 2-4 connection of unused pins . figure 5-11 shows an example of the exte rnal circuit of the xt1 oscillator. figure 5-11. example of external circuit of xt1 oscillator (crystal oscillation) xt2 v ss xt1 32.768 khz cautions are listed on the next page.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 223 jun 20, 2011 caution 1. when using the x1 oscillator and xt1 osc illator, wire as follows in the area enclosed by the broken lines in the figures 5-10 and 5-11 to avoid an adverse e ffect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. note that the xt1 oscillator is designed as a low-gain circuit fo r achieving low-power consumption. note the following points when designing the xt1 oscillator. ? the pins and circuit board include parasitic cap acitance. therefore, c onfirm that there are no problems by performing oscillation evaluation on the circuit board to be actually used. ? when low-consumption oscilla tion or super-low-consumption oscillation is selected, lower power consumption than when selecting normal o scillation can be achieved. however, in this case, the xt1 oscillation margin is reduced, so perform suffici ent oscillation evaluation of the resonator to be used for xt1 oscilla tion before using the resonator. ? keep the wiring length between the xt1 and xt 2 pins and resonator as short as possible and parasitic capacitance and wire resi stance as small as possible. th is is particularly important when super-low-consum ption oscillation (amphs1 = 1) is selected. ? configure the circuit board by using mate rial with little parasitic capacitance and wire resistance. ? place a ground pattern that h as the same potential as v ss (if possible) around the xt1 oscillator. ? do not cross the signal lines between the xt1 and xt2 pins an d the resonator with other signal lines. do not route the signal lines near a si gnal line through which a high fluctuating current flows. ? moisture absorption by the circuit board and condensation on the board in a highly humid environment may cause the impe dance between the xt1 and xt2 pins to drop and disable oscillation. when using the ci rcuit board in such an envir onment, prevent the circuit board from absorbing moisture by taking measu res such as coating the circuit board. ? coat the surface of the circuit board by using material that does not generate capacitance or leakage between the xt1 and xt2 pins. figure 5-12 shows examples of incorrect resonator connection.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 224 jun 20, 2011 figure 5-12. examples of incorr ect resonator connection (1/2) (a) too long wiring (b) crossed signal line x2 v ss x1 x1 ng ng ng v ss x2 port (c) signal lines of x1 and x2 cross (d) power supply/gnd pattern ex ists underneath x1 and x2 wiring x2 v ss x1 x1 power supply/gnd pattern v ss x2 note note do not place a power supply/gnd pattern underneath the wir ing section (in broken lines above) of the x1 and x2 pins and resonator in the multilayer board and double-sided board. do not configure a layout that ma y cause capacitance elements and affe ct the oscillation characteristics. remark when using the subsystem clock, replace x1 and x2 wi th xt1 and xt2, respectively. also, insert resistors in series on the xt2 side.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 225 jun 20, 2011 figure 5-12. examples of incorr ect resonator connection (2/2) (e) wiring near high alternating current (f) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 v ss x1 x2 ab c pmn v dd high current high current (g) signals are fetched v ss x1 x2 remark when using the subsystem clock, replace x1 and x2 wi th xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. caution 2. when x2 and xt1 are wired in parallel, the crosstalk noise of x2 may in crease with xt1, resulting in malfunctioning.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 226 jun 20, 2011 5.4.3 internal hi gh-speed oscillator the internal high-speed oscillator is incorporated in the 78k0r/lx3 (1, 8 and 20 mhz (typ.)). oscillation can be controlled by bit 0 (hiostop) of the clock operation status control register (csc) and bit 0 (dscon) of the 20 mhz internal high-speed oscillation control register (dscctl). caution to use the 1, 8, or 20 mhz inte rnal high-speed oscillati on clock, use the option byte to set the frequency in advance (for details, see chapter 26 option byte). also, the internal high-speed oscillator automatically starts oscillating a fter reset release. (if 8 mhz or 20 mh z is selected by using the option byte, the microcontroller operates using the 8 mhz in ternal high-speed oscilla tor.) to use the 20 mhz internal high-speed oscillator to operate the microcontroller, oscilla tion is started by setting bit 0 (dscon) of the dscctl register to 1 with v dd 2.7 v. 5.4.4 internal low-speed oscillator the internal low-speed oscillator is incorpor ated in the 78k0r/lx3 microcontrollers. the internal low-speed oscillation clock is used only as the watchdog timer clock. the internal low-speed oscillation clock cannot be used as the cpu clock. after a reset release, the internal low-speed oscillator autom atically starts oscillation, an d the watchdog timer is driven (30 khz (typ.)) if the watchdog timer oper ation is enabled by the option byte. the internal low-speed oscillator c ontinues oscillation except when the wa tchdog timer stops. when the watchdog timer operates, the internal low-speed oscillation clo ck does not stop, even in case of a program loop. 5.4.5 prescaler the prescaler generates a cp u/peripheral hardware cl ock by dividing the main system clock and subsystem clock.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 227 jun 20, 2011 5.5 clock generator operation the clock generator generates the follo wing clocks and controls the operation modes of the cpu, such as standby mode (see figure 5-1 ). ? main system clock f main ? high-speed system clock f mx x1 clock f x external main system clock f ex ? internal high-speed oscillation clock f ih 1 mhz internal high-speed oscillation clock f ih1 8 mhz internal high-speed oscillation clock f ih8 ? 20 mhz internal high-speed oscillation clock f ih20 ? subsystem clock f sub ? subsystem selection clock f subc ? internal low-speed oscillation clock f il ? cpu/peripheral hardware clock f clk the cpu starts operation when the internal high-speed o scillator starts outputting after a reset release in the 78k0r/lx3 microcontrollers, thus enabling the following. (1) enhancement of security function when the x1 clock is set as the cpu clock by the defaul t setting, the device cannot operate if the x1 clock is damaged or badly connected and t herefore does not operate after reset is rel eased. however, the start clock of the cpu is the internal high-speed oscillat ion clock, so the device c an be started by the inter nal high-speed oscillation clock after a reset release. as a re sult, reset sources can be detected by so ftware and the minimum amount of safety processing can be done during anomalies to ens ure that the system terminates safely. (2) improvement of performance because the cpu can be start ed without waiting for the x1 clock oscillat ion stabilization time, the total performance can be improved. when the power supply voltage is turned on, the clock gen erator operation is shown in figure 5-13 and figure 5-14.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 228 jun 20, 2011 figure 5-13. clock generator operation wh en power supply voltage is turned on (when lvi default start function stoppe d is set (option byte: lvioff = 1)) seldsc = 1 0 v 1.61 v (typ.) 1.8 v 0.5 v/ms (min.) note 1 power supply voltage (v dd ) internal reset signal cpu clock internal high-speed oscillation clock (f ih ) high-speed system clock (f mx ) (when x1 oscillation selected) 20 mhz internal high-speed oscillation clock (f ih20 ) subsystem clock (f sub ) (when xt1 oscillation selected) reset processing (2.12 to 5.84 ms) switched by software subsystem clock high-speed system clock 1 or 8 mhz internal high- speed oscillation clock 20 mhz internal high- speed oscillation clock 1 or 8 mhz internal high- speed oscillation clock x1 clock oscillation stabilization time note 2 starting x1 oscillation is specified by software. starting xt1 oscillation is specified by software. 20 mhz internal high-speed oscillation clock oscillation stabilization time : 100 s dscon = 1 is set by software. <4> <4> <4> <5> <5> <5> <1> <2> <3> <1> when the power is turned on, an internal reset signal is generated by the power-on-clear (poc) circuit. <2> when the power supply voltage exc eeds 1.61 v (typ.), the reset is rel eased and the internal high-speed oscillator automatically starts oscillation. <3> the cpu starts operation on the internal high-speed oscillation clock note 3 after a reset processing such as waiting for the voltage of the power supply or regulator to stabilize has been performed after reset release. <4> set the start of oscillation of the x1 or xt1 clock via software (see (1) in 5.6.1 example of controlling high- speed system clock and (1) in 5.6.3 example of cont rolling subsystem clock) . <5> when switching the cpu clock to the x1 or xt1 clock, wait for the clock oscillatio n to stabilize, and then set switching via software (see (3) in 5.6.1 example of controlli ng high-speed system clock and (2) in 5.6.3 example of controlling subsystem clock ). switch to the 20 mhz internal high-speed oscillation clock by setting the dscon bit (bit 0 of the 20 mhz internal high-speed oscillation control regist er (dscctl)), waiting for 100 s, and then setting the seldsc bit to 1 by using software note 4 . ( notes and cautions are listed on the next page.)
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 229 jun 20, 2011 notes 1. the internal reset processing time includes the oscill ation accuracy stabilization time of the internal high- speed oscillation clock. 2. when releasing a reset, confirm the oscillation stabiliz ation time for the x1 clock using the oscillation stabilization time counter st atus register (ostc). 3. the microcontroller operates on the 8 mhz internal high-speed oscillation clock if 8 mhz or 20 mhz is selected for the internal high-speed oscillator by usi ng the option byte or on the 1 mhz internal high-speed oscillation clock if 1 mhz is selected. 4. if the internal high-speed oscillator is set to 1 mhz by using the option byte, the 20 mhz internal high-speed oscillation clock cannot be used. cautions 1. if the voltage rises with a slope of l ess than 0.5 v/ms (min.) from power application until the voltage reaches 1.8 v, input a lo w level to the reset pin from pow er application until the voltage reaches 1.8 v, or set the lvi default start functi on stopped by using the option byte (lvioff = 0) (see figure 5-14). by doing so, the cpu operat es with the same timing as <2> and thereafter in figure 5-13 after reset rel ease by the reset pin. 2. it is not necessary to wait for the oscillation stabilization time when an external clock input from the exclk pin is used.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 230 jun 20, 2011 figure 5-14. clock generator operation wh en power supply voltage is turned on (when lvi default start function enable d is set (option byte: lvioff = 0)) seldsc = 1 0 v 2.07 v note 1 power supply voltage (v dd ) internal reset signal cpu clock internal high-speed oscillation clock (f ih ) high-speed system clock (f mx ) (when x1 oscillation selected) 20 mhz internal high-speed oscillation clock (f ih20 ) subsystem clock (f sub ) (when xt1 oscillation selected) reset processing (195 to 341 s) switched by software subsystem clock high-speed system clock 1 or 8 mhz internal high- speed oscillation clock 20 mhz internal high- speed oscillation clock 1 or 8 mhz internal high- speed oscillation clock x1 clock oscillation stabilization time note 2 starting x1 oscillation is specified by software. starting xt1 oscillation is specified by software. 20 mhz internal high-speed oscillation clock oscillation stabilization time : 100 s dscon = 1 is set by software. <4> <4> <4> <5> <5> <5> <1> <2> <3> <1> when the power is turned on, an internal reset signal is generated by the low-voltage detector (lvi) circuit. <2> when the power supply voltage exc eeds 2.07 v (typ.), the reset is rel eased and the internal high-speed oscillator note 3 automatically starts oscillation. <3> after the reset is released and reset processing is perfo rmed, the cpu starts operation on the internal high-speed oscillation clock note 3 . <4> set the start of oscillation of the x1 or xt1 clock via software (see (1) in 5.6.1 example of controlling high- speed system clock and (1) in 5.6.3 example of controlling subsystem clock ). switch to oscillation using the 20 mhz internal high-spee d oscillation clock after setting the dscon bit to 1 by using software. <5> when switching the cpu clock to the x1 or xt1 clock, wait for the clock oscillatio n to stabilize, and then set switching via software (see (3) in 5.6.1 example of controllin g high-speed system clock and (2) in 5.6.3 example of controlling subsystem clock ). switch to the 20 mhz internal high-speed oscillation cloc k after confirming that the power supply voltage is at least 2.7 v, setting the dscon bit (bit 0 of the 20 mhz inte rnal high-speed oscillation control register (dscctl)), waiting for 100 s, and then setting the seldsc bit to 1 by using software note 4 . ( notes and cautions are listed on the next page.)
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 231 jun 20, 2011 notes 1. the internal reset processing time includes the oscill ation accuracy stabilization time of the internal high- speed oscillation clock. 2. when releasing a reset, confirm the oscillation stabiliz ation time for the x1 clock using the oscillation stabilization time counter st atus register (ostc). 3. the microcontroller operates on the 8 mhz internal high-speed oscillation clock if 8 mhz or 20 mhz is selected for the internal high-speed oscillator by usi ng the option byte or on the 1 mhz internal high-speed oscillation clock if 1 mhz is selected. 4. if the internal high-speed oscillator is set to 1 mhz by using the option byte, the 20 mhz internal high-speed oscillation clock cannot be used. cautions 1. a voltage stabilization time (about 2.12 to 5.84 ms) is required afte r the supply voltage reaches 1.61 v (typ.). if the time for the supply voltage to rise from 1. 61 v (typ.) to 2.07 v (typ.) is shorter than the voltage stab ilization time, reset processing is entered after the voltage stabilization time elapses. 2. it is not necessary to wait fo r the oscillation stabilization time when an external clock input from the exclk pin is used.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 232 jun 20, 2011 5.6 controlling clock 5.6.1 example of control ling high-speed system clock the following two types of high-s peed system clocks are available. ? x1 clock: crystal/ceramic resonator is connected to the x1 and x2 pins. ? external main system clock: exter nal clock is input to the exclk pin. when the high-speed system clock is not used, the x1/p121 and x2/exclk/p122 pi ns can be used as input port pins. caution the x1/p121 and x2/exclk/p122 pins are in the input port mode after a reset release. the following describes examples of setti ng procedures for the following cases. (1) when oscillating x1 clock (2) when using external main system clock (3) when using high-speed system clo ck as cpu/peripheral hardware clock (4) when stopping high-speed system clock (1) example of setting procedure when oscillating the x1 clock <1> setting p121/x1 and p122/x2/exclk pins and setting oscillation frequency (cmc register) ? 2 mhz f x 10 mhz exclk oscsel 0 oscsels 0 amphs1 amphs0 amph 0 1 0 0/1 0 0/1 0/1 0 ? 10 mhz < f x 20 mhz exclk oscsel 0 oscsels 0 amphs1 amphs0 amph 0 1 0 0/1 0 0/1 0/1 1 remarks 1. f x : x1 clock oscillation frequency 2. for setting of the p123/xt1 and p124/xt2 pins, see 5.6.3 example of controlling subsystem clock . <2> controlling oscillation of x1 clock (csc register) if mstop is cleared to 0, the x1 oscillator starts oscillating. <3> waiting for the stabilization of the oscillation of x1 clock check the ostc register and wait for the necessary time. during the wait time, other software processing can be executed with the internal high-speed oscillation clock. cautions 1. the cmc register can be written on ly once after reset release, by an 8-bit memory manipulation instruction. therefore, it is necessary to also set the val ue of the oscsels bit at the same time. for oscsels bit, see 5.6.3 example of controlling subsystem clock. 2. set the x1 clock after the supply voltage has reached the opera ble voltage of the clock to be used (see chapter 31 el ectrical specifications).
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 233 jun 20, 2011 (2) example of setting procedure when using the external main system clock <1> setting p121/x1 and p122/x2/exclk pins (cmc register) exclk oscsel 0 oscsels 0 amphs1 amphs0 amph 1 1 0 0/1 0 0/1 0/1 0/1 remark for setting of the p123/xt 1 and p124/xt2 pins, see 5.6.3 (1) example of setting procedure when oscillating the subsystem clock . <2> controlling external main syst em clock input (csc register) when mstop is cleared to 0, the input of the external main system clock is enabled. cautions 1. the cmc register can be written on ly once after reset release, by an 8-bit memory manipulation instruction. therefore, it is necessary to also set the value of the oscsels bits at the same time. for oscsels bits, see 5.6.3 example of controlling subsystem clock. 2. set the external main system clock after th e supply voltage has reac hed the operable voltage of the clock to be used (see chapte r 31 electrical specifications). (3) example of setting procedure wh en using high-speed system clock as cpu/peripheral hardware clock <1> setting high-speed system clock oscillation note (see 5.6.1 (1) example of setting proce dure when oscillating the x1 clock and (2) example of setting procedure when using the ext ernal main system clock. ) note the setting of <1> is not necessary when hi gh-speed system clock is already operating. <2> setting the high-speed system clock as the source clock of the cpu/peripheral hardware clock and setting the division ratio of the set clock (ckc register) mcm0 mdiv2 mdiv1 mdiv0 selection of cpu/peripheral hardware clock (f clk ) 0 0 0 f mx 0 0 1 f mx /2 0 1 0 f mx /2 2 0 1 1 f mx /2 3 1 0 0 f mx /2 4 1 1 0 1 f mx /2 5 note note setting is prohibited when f mx < 4 mhz.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 234 jun 20, 2011 <3> if some peripheral hardware macros are not used, s upply of the input clock to each hardware macro can be stopped. (per0 register) rtcen dacen adcen iicaen sau1en sau0en tau1en tau0en xxxen input clock control 0 stops input clock supply. 1 supplies input clock. remark rtcen: control of the r eal-time counter input clock dacen: control of the d/a converter input clock adcen: control of the a/d converte r and operational amplifier input clock iicaen: control of the serial interface iica input clock sau1en: control of the serial array unit 1 unit input clock sau0en: control of the serial array unit 0 unit input clock tau1en: control of the ti mer array unit 1 input clock tau0en: control of the ti mer array unit 0 input clock (4) example of setting procedure when stopping the high-speed system clock the high-speed system clock can be stopped (disabling clock i nput if the external clock is used) in the following two ways. ? executing the stop instruction ? setting mstop to 1 (a) to execute a stop instruction <1> setting to stop peripheral hardware stop peripheral hardware that cannot be used in the stop mode (for peripheral hardware that cannot be used in stop mode, see chapter 21 standby function ). <2> setting the x1 clock oscillation stabilization time after stop mode is released if the x1 clock oscillates before the stop mode is en tered, set the value of the osts register before executing the stop instruction. <3> executing the stop instruction when the stop instruction is exec uted, the system is placed in t he stop mode and x1 oscillation is stopped (the input of the exte rnal clock is disabled).
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 235 jun 20, 2011 (b) to stop x1 oscillation (disabling exter nal clock input) by setting mstop to 1 <1> confirming the cpu clock status (ckc register) confirm with cls and mcs that the cpu is operating on a clock other than the high-speed system clock. when cls = 0 and mcs = 1, the high-speed system clo ck is supplied to the cpu, so change the cpu clock to the subsystem clock or inte rnal high-speed o scillation clock. cls mcs cpu clock status 0 0 internal high-speed oscillation cl ock or 20 mhz internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> setting of x1 clock oscillation stabilizatio n time after restart of x1 clock oscillation note prior to setting "1" to mstop, set the osts regist er to a value greater than the count value to be confirmed with the osts register afte r x1 clock oscillation is restarted. <3> stopping the high-speed system clock (csc register) when mstop is set to 1, x1 oscillation is stopp ed (the input of the external clock is disabled). note this setting is required to resume the x1 clock osc illation when the high-speed system clock is in the x1 oscillation mode. this setting is not required in the external clock input mode. caution be sure to confirm that mcs = 0 or cls = 1 when setting mstop to 1. in addition, stop peripheral hardware that is operating on the high-speed system clock. 5.6.2 example of controlling inte rnal high-speed oscillation clock the following describes examples of clock setting procedures for the following cases. (1) when restarting oscillation of the internal high-speed oscillation clock (2) when using internal high-speed oscillation clock as cpu/peripheral hardware clock (3) when stopping the internal high-speed oscillation clock (1) example of setting procedure wh en restarting oscillation of the in ternal high-speed oscillation clock note <1> setting restart of oscillation of the intern al high-speed oscillation clock (csc register) when hiostop is cleared to 0, the internal hi gh-speed oscillation clock restarts oscillation. note after a reset release, the internal high-speed oscillat or automatically starts oscillating and the internal high- speed oscillation clock is selected as the cpu/peripheral hardware clock. (2) example of setting procedure when using intern al high-speed oscillation clock as cpu/peripheral hardware clock <1> restarting oscillation of the internal high-speed oscillation clock note (see 5.6.2 (1) example of setting pr ocedure when restarting internal high-speed oscillation clock ). note the setting of <1> is not necessary when the intern al high-speed oscillation clock is operating.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 236 jun 20, 2011 <2> setting the internal high-speed oscillation clock as the source clock of the cp u/peripheral hardware clock and setting the division ratio of the set clock (ckc register) mcm0 mdiv2 mdiv1 mdiv0 selection of cpu/peripheral hardware clock (f clk ) 0 0 0 f ih 0 0 1 f ih /2 0 1 0 f ih /2 2 0 1 1 f ih /2 3 1 0 0 f ih /2 4 note 0 1 0 1 f ih /2 5 note note setting is prohibited when f ih = 1 mhz. caution if switching the cpu/peri pheral hardware clock from th e high-speed system clock to the internal high-speed oscillation clock after restarting the in ternal high-speed oscillation clock, do so after 10 s or more have elapsed. if the switching is made immediately after the internal high-speed oscillation clock is restarted, the accuracy of the internal high-speed oscillat ion cannot be guaranteed for 10 s. (3) example of setting procedure when stop ping the internal high-speed oscillation clock the internal high-speed oscillation clock can be stopped in the following two ways. ? executing the stop instruction ? setting hiostop to 1 (a) to execute a stop instruction <1> setting of peripheral hardware stop peripheral hardware that cannot be used in the stop mode (for peripheral hardware that cannot be used in stop mode, see chapter 21 standby function ). <2> setting the x1 clock oscillation stabilization time after stop mode is released if the x1 clock oscillates before the stop mode is en tered, set the value of the osts register before executing the stop instruction. <3> executing the stop instruction when the stop instruction is exec uted, the system is placed in the stop mode and internal high-speed oscillation clock is stopped.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 237 jun 20, 2011 (b) to stop internal high-speed osc illation clock by setting hiostop to 1 <1> confirming the cpu clock status (ckc register) confirm with cls and mcs that the cpu is operatin g on a clock other than the internal high-speed oscillation clock. when cls = 0 and mcs = 0, the internal high-speed osci llation clock is supplied to the cpu, so change the cpu clock to the high-speed syst em clock or subsystem clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clo ck or 20 mhz internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the internal high-speed oscillation clock (csc register) when hiostop is set to 1, internal high-speed oscillation clock is stopped. caution be sure to confirm that mcs = 1 or cls = 1 when setting hiostop to 1. in addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock. 5.6.3 example of cont rolling subsystem clock the subsystem clock can be oscillated by connecti ng a crystal resonator to the xt1 and xt2 pins. when the subsystem clock is not us ed, the xt1/p123 and xt2/p124 pins can be used as input port pins. caution the xt1/p123 and xt2/p124 pins are in the input port mode after a reset release. the following describes examples of setti ng procedures for the following cases. (1) when oscillating subsystem clock (2) when using subsystem clock as cpu clock (3) when stopping subsystem clock caution when the subsystem clock is used as the cpu cl ock, the subsystem clock is also supplied to the peripheral hardware (except the real-ti me counter, timer array unit (when f sub /2, f sub /4, the valid edge of ti0mn input, or the valid e dge of intrtci is selected as the count clock), clock output/buzzer output, and watchdog timer). at this time, the operations of the a/d converter and iica are not guaranteed. for the operating ch aracteristics of the peripheral ha rdware, refer to the chapters describing the various periphera l hardware as well as chapter 31 electrical specifications. (1) example of setting procedure wh en oscillating the subsystem clock <1> setting p123/xt1 and p124/xt2 pins (cmc register) exclk oscsel 0 oscsels 0 amphs1 amphs0 amph 0/1 0/1 0 1 0 0/1 0/1 0/1 remark for setting of the p121/x1 and p122/x2 pins, see 5.6.1 example of controlling high-speed system clock . <2> controlling oscillation of subsystem clock (csc register) if xtstop is cleared to 0, the xt1 oscillator starts oscillating.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 238 jun 20, 2011 <3> waiting for the stabilization of the subsystem clock oscillation wait for the oscillation stabilization time of the subsystem clock by software, using a timer function. caution the cmc register can be wr itten only once after reset release, by an 8-bit memory manipulation instruction. therefore, it is necessary to al so set the value of the exclk and oscsel bits at the same time. for exclk and oscsel bits, see 5.6.1 (1) exampl e of setting procedure when oscillating the x1 clock or 5.6.1 (2) example of setting procedur e when using the externa l main system clock. (2) example of setting procedure when us ing the subsystem cl ock as the cpu clock <1> setting subsystem clock oscillation note (see 5.6.3 (1) example of setting procedur e when oscillating the subsystem clock .) note the setting of <1> is not necessary when while the subsystem clock is operating. <2> setting the subsystem clock as the source clo ck of the cpu/peripheral hardware clock and setting the division ratio of the set clock (ckc register) css sdiv selection of cpu/peripheral hardware clock (f clk ) 0 f sub 1 1 f sub /2 caution when the subsystem clock is used as the cpu cl ock, the subsystem clock is also supplied to the peripheral hardware (except the real-ti me counter, timer array unit (when f sub /2, f sub /4, the valid edge of ti0mn input, or the valid edge of intrtci is selected as th e count clock), clock output/buzzer output, and watchdog timer). at this time, the operations of the a/d converter and iica are not guaranteed. for the operating character istics of the peripheral hardware, refer to the chapters describing the various peripheral hardware as well as chapter 31 electrical specifications. (3) example of setting procedure wh en stopping the subsystem clock <1> confirming the cpu clock status (ckc register) confirm with cls and mcs that the cpu is operat ing on a clock other than the subsystem clock. when cls = 1, the subsystem clock is supplied to t he cpu, so change the cpu clock to the internal high- speed oscillation clock or high-speed system clock. cls mcs cpu clock status 0 0 internal high-speed oscillation cl ock or 20 mhz internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the subsystem clock (csc register) when xtstop is set to 1, subsystem clock is stopped. cautions 1. be sure to confirm th at cls = 0 when setting xtstop to 1. in addition, stop the peripheral hardware if it is operati ng on the subsystem clock. 2. the subsystem clock oscillation cannot be stopped using the stop instruction.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 239 jun 20, 2011 5.6.4 example of controlling in ternal low-speed oscillation clock the internal low-speed oscillation clock cannot be used as the cpu clock. used only as the watchdog timer clock. the internal low-speed oscillat or automatically starts oscillation after a re set release, and the watchdog timer is driven (30 khz (typ.)) if the watchdog timer oper ation is enabled by the option byte. the internal low-speed oscillator c ontinues oscillation except when the wa tchdog timer stops. when the watchdog timer operates, the internal low-speed oscillation clo ck does not stop even in case of a program loop. (1) example of setting procedure when stoppi ng the internal low-speed oscillation clock the internal low-speed oscillation clock can be stopped in the following two ways. ? stop the watchdog timer in the halt/stop mode by the option byte (bit 0 (wdstbyon) of 000c0h = 0), and execute the halt or stop instruction. ? stop the watchdog timer by the option byte (bit 4 (wdton) of 000c0h = 0). (2) example of setting procedure when restarting o scillation of the internal low-speed oscillation clock the internal low-speed oscillation clock can be restarted as follows. ? release the halt or stop mode (only when the watchdog timer is stopped in the halt/sto p mode by the option byte (bit 0 (wdstbyon) of 000c0h) = 0) and when the watchdog timer is stopped as a result of execution of the halt or stop instruction).
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 240 jun 20, 2011 5.6.5 cpu clock stat us transition diagram figure 5-15 shows the cpu clock status transition diagram of this product. figure 5-15. cpu clock stat us transition diagram internal high-speed oscillation: woken up x1 oscillation/exclk input: stops (input port mode) xt1 oscillation: stops (input port mode) dsc oscillation: stops internal high-speed oscillation: operating x1 oscillation/exclk input: stops (input port mode) xt1 oscillation: stops (input port mode) dsc oscillation: stops v dd 1.61 v 0.09 v dd 1.8 v v dd < 1.61 v 0.09 cpu: internal high- speed oscillation stop cpu: internal high- speed oscillation halt cpu: x1 oscillation/exclk input stop internal high-speed oscillation: stops x1 oscillation/exclk input: stops xt1 oscillation: oscillatable dsc oscillation: stops internal high-speed oscillation: operating x1 oscillation/exclk input: oscillatable xt1 oscillation: oscillatable dsc oscillation: stops internal high-speed oscillation: stops x1 oscillation/exclk input: stops xt1 oscillation: oscillatable dsc oscillation: stops internal high-speed oscillation: oscillatable x1 oscillation/exclk input: operating xt1 oscillation: oscillatable dsc oscillation: stops cpu: operating with internal high- speed oscillation cpu: operating with x1 oscillation or exclk input cpu: x1 oscillation/exclk input halt power on reset release internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: operating xt1 oscillation: selectable by cpu dsc oscillation: stops internal high-speed oscillation: operating x1 oscillation/exclk input: selectable by cpu xt1 oscillation: selectable by cpu dsc oscillation: selectable by cpu cpu: operating with dsc oscillation cpu: dsc oscillation halt internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: cannot be selected by cpu xt1 oscillation: cannot be selected by cpu dsc oscillation: operating internal high-speed oscillation: oscillatable x1 oscillation/exclk input: oscillatable xt1 oscillation: oscillatable dsc oscillation: operating (g) (k) (d) (j) (c) (f) (i) (e) (h) (b) (a) cpu: operating with xt1 oscillation cpu: xt1 oscillation halt internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: selectable by cpu xt1 oscillation: operating dsc oscillation: stops internal high-speed oscillation: oscillatable x1 oscillation/exclk input: oscillatable xt1 oscillation: operating dsc oscillation: stops note 1 notes 2, 3 notes 1. after reset release, an operation at one of the fo llowing operating frequencies is started, because f clk = f ih /2 has been selected by setting the system cl ock control register (ckc) to 09h. ? when 1 mhz has been selected by using the option byte: 500 khz (1 mhz/2) ? when 8 mhz or 20 mhz has been selected by using the option byte: 4 mhz (8 mhz/2) 2. specify 20 mhz internal oscillation after checking that v dd is at least 2.7 v. 3. 20 mhz internal oscillation cannot be used if 1 mhz internal oscillation is selected by using the option byte. remarks 1. if the low-power-supply detector (lvi) is set to on by default by the option bytes, the reset will not be released until the power supply voltage (v dd ) exceeds 2.07 v 0.2 v. after the reset operation, the status will shift to (b) in the above figure. 2. dsc: 20 mhz internal high-speed oscillation clock
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 241 jun 20, 2011 table 5-4 shows transition of the cpu clock and examples of setting the sfr registers. table 5-4. cpu clock transition a nd sfr register setting examples (1/6) (1) cpu operating with internal high-speed oscillation clock (b) a fter reset release (a) status transition sfr register setting (a) (b) sfr registers do not have to be se t (default status after reset release). (2) cpu operating with high-speed system clock (c) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) cmc register note 1 csc register osmc register ckc register setting flag of sfr register status transition exclk oscsel amph mstop fsel ostc register mcm0 (a) (b) (c) (x1 clock: 2 mhz f x 10 mhz) 0 1 0 0 0 must be checked 1 (a) (b) (c) (x1 clock: 10 mhz < f x 20 mhz) 0 1 1 0 1 note 2 must be checked 1 (a) (b) (c) (external main clock) 1 1 0 0/1 note 2 must not be checked 1 notes 1. the clock operation mode control register (c mc) can be written only once by an 8-bit memory manipulation instruction after reset release. 2. fsel = 1 when f clk > 10 mhz if a divided clock is selected and f clk 10 mhz, use with fsel = 0 is possible even if f x > 10 mhz. caution set the clock after the suppl y voltage has reached the operable volt age of the clock to be set (see chapter 31 electrical specifications). (3) cpu operating with subsystem cl ock (d) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) cmc register note csc register ckc register setting flag of sfr register status transition oscsels amphs1 amphs0 xtstop waiting for oscillation stabilization css (a) (b) (d) 1 0/1 0/1 0 necessary 1 note the cmc register can be written only once by an 8-bit memory manipulation instru ction after reset release. remark (a) to (k) in table 5-4 correspond to (a) to (k) in figure 5-15.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 242 jun 20, 2011 table 5-4. cpu clock transition a nd sfr register setting examples (2/6) (4) cpu operating with 20 mhz internal high-speed oscillation clock (j) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) dscctl register note dscctl register setting flag of sfr register status transition dscon waiting for oscillation stabilization seldsc (a) (b) (j) 1 necessary (100 s) 1 note check that v dd 2.7 v and set dscon = 1. (5) cpu clock changing from inte rnal high-speed oscillation clock (b) to high-speed system clock (c) (setting sequence of sfr registers) cmc register note 1 csc register osmc register ckc regi ster setting flag of sfr register status transition exclk oscsel amph osts register mstop fsel ostc register mcm0 (b) (c) (x1 clock: 2 mhz fx 10 mhz) 0 1 0 note 2 0 0 must be checked 1 (b) (c) (x1 clock: 10 mhz < fx 20 mhz) 0 1 1 note 2 0 1 note 3 must be checked 1 (b) (c) (external main clock) 1 1 note 2 0 0/1 must not be checked 1 unnecessary if these registers are already set unnecessary if the cpu is operating with the high-speed system clock notes 1. the cmc register can be changed only once after reset release. this setting is not necessary if it has already been set. 2. set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts 3. fsel = 1 when f clk > 10 mhz if a divided clock is selected and f clk 10 mhz, use with fsel = 0 is possible even if f x > 10 mhz. caution set the clock after the suppl y voltage has reached the operable volt age of the clock to be set (see chapter 31 electrical specifications). remarks 1. : don?t care 2. (a) to (k) in table 5-4 correspond to (a) to (k) in figure 5-15.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 243 jun 20, 2011 table 5-4. cpu clock transition a nd sfr register setting examples (3/6) (6) cpu clock changing from in ternal high-speed oscillation cl ock (b) to subsystem clock (d) (setting sequence of sfr registers) cmc register note csc register ckc register setting flag of sfr register status transition oscsels xtstop waiting for oscillation stabilization css (b) (d) 1 0 necessary 1 unnecessary if the cpu is operating with the subsystem clock note the cmc register can be written only once by an 8-bit memory manipulation instru ction after reset release. (7) cpu clock changing from internal high-speed oscillation clock (b) to 20 mhz internal high-speed oscillation clock (j) (setting sequence of sfr registers) dscctl register note dscctl register setting flag of sfr register status transition dscon waiting for oscillation stabilization seldsc (b) (j) 1 necessary (100 s) 1 unnecessary if the cpu is operating with the 20 mhz internal high-speed oscillation clock note check that v dd 2.7 v and set dscon = 1. (8) cpu clock changing from high- speed system clock (c) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) csc register ckc register setting flag of sfr register status transition hiostop oscillation accuracy stabilization time mcm0 (c) (b) 0 10 s 0 unnecessary if the cpu is operating with the internal high- speed oscillation clock remark (a) to (k) in table 5-4 correspond to (a) to (k) in figure 5-15.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 244 jun 20, 2011 table 5-4. cpu clock transition a nd sfr register setting examples (4/6) (9) cpu clock changing from high-speed system clock (c) to subsystem clock (d) (setting sequence of sfr registers) csc register ckc register setting flag of sfr register status transition xtstop waiting for oscillation stabilization css (c) (d) 0 necessary 1 unnecessary if the cpu is operating with the subsystem clock (10) cpu clock changing from subsystem clock (d) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) csc register ckc register setting flag of sfr register status transition hiostop mcm0 css (d) (b) 0 0 0 unnecessary if the cpu is operating with the internal high-speed oscillation clock unnecessary if this register is already set remark (a) to (k) in table 5-4 correspond to (a) to (k) in figure 5-15.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 245 jun 20, 2011 table 5-4. cpu clock transition a nd sfr register setting examples (5/6) (11) cpu clock changing from subsystem clock (d) to high-sp eed system clock (c) (setting sequence of sfr registers) csc register osmc register ckc register setting flag of sfr register status transition osts register mstop fsel ostc register mcm0 css (d) (c) (x1 clock: 2 mhz f x 10 mhz) note 1 0 0 must be checked 1 0 (d) (c) (x1 clock: 10 mhz < f x 20 mhz) note 1 0 1 note 2 must be checked 1 0 (d) (c) (external main clock) note 1 0 0/1 must not be checked 1 0 unnecessary if the cpu is operating with the high-speed system clock unnecessary if these registers are already set notes 1. set the oscillation stabili zation time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts 2. fsel = 1 when f clk > 10 mhz if a divided clock is selected and f clk 10 mhz, use with fsel = 0 is possible even if f x > 10 mhz. caution set the clock after the suppl y voltage has reached the operable volt age of the clock to be set (see chapter 31 electrical specifications). (12) cpu clock changing from 20 mhz internal high-speed oscillation clock (j) to in ternal high-speed oscillation clock (b) (setting sequence of sfr registers) dscctl register setting flag of sfr register status transition seldsc dscon (j) (b) 0 0 remark (a) to (k) in table 5-4 correspond to (a) to (k) in figure 5-15.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 246 jun 20, 2011 table 5-4. cpu clock transition a nd sfr register setting examples (6/6) (13) ? halt mode (e) set while cpu is operating wit h internal high-speed oscillation clock (b) ? halt mode (f) set while cpu is ope rating with high-speed system clock (c) ? halt mode (g) set while cpu is operating with subsystem clock (d) ? halt mode (k) set while cpu is operating with 20 mhz internal high-speed oscillation clock (j) status transition setting (b) (e) (c) (f) (d) (g) (j) (k) executing halt instruction (14) ? stop mode (h) set while cp u is operating with internal hi gh-speed oscillation clock (b) ? stop mode (i) set while cpu is ope rating with high-speed system clock (c) (setting sequence) status transition setting (b) (h) ? in x1 oscillation sets the osts register (c) (i) external main system clock stopping peripheral functions that cannot operate in stop mode ? executing stop instruction remark (a) to (k) in table 5-4 correspond to (a) to (k) in figure 5-15.
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 247 jun 20, 2011 5.6.6 condition before changing cpu clo ck and processing after changing cpu clock condition before changing the cpu clock and processing after changing the cpu clock are shown below. table 5-5. changing cpu clock (1/2) cpu clock before change after change condition before change processing after change x1 clock stabilization of x1 oscillation ? oscsel = 1, exclk = 0, mstop = 0 ? after elapse of oscillation stabilization time external main system clock enabling input of ex ternal clock from exclk pin ? oscsel = 1, exclk = 1, mstop = 0 operating current can be reduced by stopping internal high-speed oscillator (hiostop = 1). subsystem clock stabilization of x1 oscillation ? oscsels = 1, xtstop = 0 ? after elapse of oscillation stabilization time ? internal high- speed oscillation clock 20 mhz internal high-speed oscillation clock stabilization of dsc oscillation with 20 mhz set by using the option byte ? v dd 2.7 v ? after elapse of oscillation stabilization time (100 s) after setting to dscon = 1 ? seldsc = 1 ? internal high- speed oscillation clock oscillation of internal high-speed oscillator ? hiostop = 0 x1 oscillation can be stopped (mstop = 1). external main system clock transition not possible (to change the clock, set it again after executing reset once.) ? subsystem clock stabilization of xt1 oscillation ? oscsels = 1, xtstop = 0 ? after elapse of oscillation stabilization time x1 oscillation can be stopped (mstop = 1). x1 clock 20 mhz internal high-speed oscillation clock transition cannot be performed unless the clock is changed to the internal high-speed oscillation clock once. ? internal high- speed oscillation clock oscillation of internal high-speed oscillator ? hiostop = 0 external main syst em clock input can be disabled (mstop = 1). x1 clock transition not possible (to change the clock, set it again after executing reset once.) ? subsystem clock stabilization of xt1 oscillation ? oscsels = 1, xtstop = 0 ? after elapse of oscillation stabilization time external main syst em clock input can be disabled (mstop = 1). external main system clock 20 mhz internal high-speed oscillation clock transition cannot be performed unless the clock is changed to the internal high-speed oscillation clock once. ?
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 248 jun 20, 2011 table 5-5. changing cpu clock (2/2) cpu clock before change after change condition before change processing after change internal high- speed oscillation clock oscillation of internal high-speed oscillator and selection of internal high-speed oscillation clock as main system clock ? hiostop = 0, mcs = 0 x1 clock stabilization of x1 oscillation and selection of high-speed system clock as main system clock ? oscsel = 1, exclk = 0, mstop = 0 ? after elapse of oscillation stabilization time ? mcs = 1 external main system clock enabling input of ex ternal clock from exclk pin and selection of high-speed system clock as main system clock ? oscsel = 1, exclk = 1, mstop = 0 ? mcs = 1 xt1 oscillation can be stopped (xtstop = 1) subsystem clock 20 mhz internal high-speed oscillation clock transition cannot be performed unless the clock is changed to the internal high-speed oscillation clock once. ? internal high- speed oscillation clock ? seldsc = 0 (set when changing the clock.) 20 mhz internal high-speed oscillation clock can be stopped (dscon = 0) x1 clock transition cannot be performed unless the clock is changed to the internal high-speed oscillation clock once. ? external main system clock transition cannot be performed unless the clock is changed to the internal high-speed oscillation clock once. ? 20 mhz internal high-speed oscillation clock subsystem clock transition cannot be performed unless the clock is changed to the internal high-speed oscillation clock once. ?
78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 249 jun 20, 2011 5.6.7 time required for switchover of cpu clock and main system clock by setting bits 0 to 2, 4, and 6 (mdiv0 to mdiv2, sdiv, mc m0, css) of the system clock control register (ckc), the cpu clock can be switched (between the main system clock and the subsystem clock), main system clock can be switched (between the internal high-speed oscillation clock and the high-speed system clock), and the division ratio of the main system clock can be changed. the actual switchover operat ion is not performed immediately after rewrit ing to ckc; operatio n continues on the pre- switchover clock for several clo cks (see table 5-6 to table 5-9). whether the cpu is operating on the main system clock or t he subsystem clock can be ascertained using bit 7 (cls) of ckc. whether the main system clock is operating on the high-speed system clock or internal high-speed oscillation clock can be ascertained using bit 5 (mcs) of ckc. when the cpu clock is switched, the perip heral hardware clock is also switched. internal high-speed oscillation clock table 5-6. maximum time required for main system clock switchover clock a switching directions clock b remark f mainc f mainc f subc (changing the division ratio) f subc see table 5-7 f ih f mx see table 5-8 f mainc f subc see table 5-9 table 5-7. maximum number of clocks required in f mainc ? f mainc (changing the division ratio), f subc ? f subc (changing the division ratio) set value after switchover set value before switchover clock a clock b clock a 1 + f a /f b clock clock b 1 + f b /f a clock table 5-8. maximum number of clocks required in f ih ? f mx set value before switchover set value after switchover mcm0 mcm0 0 (f main = f ih ) 1 (f main = f mx ) f mx f ih 1 + f ih /f mx clock 0 (f main = f ih ) f mx 78k0r/lx3 chapter 5 clock generator r01uh0004ej0501 rev.5.01 250 jun 20, 2011 table 5-9. maximum number of clocks required in f mainc ? f subc set value before switchover set value after switchover css css 0 (f clk = f mainc ) 1 (f clk = f subc ) 0 (f clk = f mainc ) f mainc >f subc 1 + 2f mainc /f subc clock 1 (f clk = f subc ) f mainc >f subc 2 + f subc /f mainc clock remarks 1. the number of clocks listed in table 5-7 to table 5-9 is the number of cpu clocks before switchover. 2. calculate the number of clocks in table 5-7 to table 5-9 by removing the decimal portion. example when switching the main system clock from t he internal high-speed oscillation clock to the high-speed system clock (@ oscillation with f ih = 8 mhz, f mx = 10 mhz) 1 + f ih /f mx = 1 + 8/10 = 1 + 0.8 = 1.8 2 clocks 5.6.8 conditions before cl ock oscillation is stopped the following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. table 5-10. conditions before the clo ck oscillation is stopped and flag settings clock conditions before clock oscillation is stopped (external clock input disabled) flag settings of sfr register internal high-speed oscillation clock mcs = 1 or cls = 1 (the cpu is operating on a clock ot her than the internal high-speed oscillation clock) hiostop = 1 x1 clock external main system clock mcs = 0 or cls = 1 (the cpu is operating on a clock other than the high-speed system clock) mstop = 1 subsystem clock cls = 0 (the cpu is operating on a clock other than the subsystem clock) xtstop = 1 20 mhz internal high-speed oscillation clock seldsc = 0 (the main system clock is operat ing on a clock other than the 20 mhz internal high-speed oscillation clock.) dscon = 0
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 251 jun 20, 2011 chapter 6 timer array unit 78k0r/lf3 78k0r/lg3 78k0r/lh3 item 80 pins 100 pins 128 pins 0 8 ch (pwm output: 5) 8 ch (pwm output: 7) 8 ch (pwm output: 7) timer array unit 1 4 ch (pwm output: 0) 4 ch (pwm output: 0) 4 ch (pwm output: 3) the 78k0r/lx3 is provided with two timer array units. time array unit 0 is provided with eight 16-bit timers and timer array unit 1 is provided with four 16-bit timers. each 16- bit timer is called a channel and can be used as an independent timer. in addition, two or more ?channels? can be used to create a high-accuracy timer. independent operation function combination operation function ? interval timer ? square wave output ? external event counter ? divider function ? input pulse interval measurement ? measurement of high-/low-l evel width of input signal ? pwm output ? one-shot pulse output ? multiple pwm output channel 7 of timer array unit 0 can be used to realize lin-bu s reception processing in combination with uart3 of serial array unit 1. cautions 1. channel 5 of timer array unit 0 of the 78k0r/lf3 can be used only as an interval timer. 2. channel 6 of timer array unit 0 of the 78k0r/lf3 can be used on ly as an interval timer, for pwm output (master channel), and for one-shot pulse ou tput (master channel when software trigger start is selected). 3. channels 0 to 3 of timer array unit 1 of the 78k0r/lf3 and 78k0r/lg3 can be used only as interval timers. 4. channels 1, 5 to 7 of timer array unit 0 and ch annels 0 to 3 of timer array unit 1 cannot be used as frequency dividers.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 252 jun 20, 2011 whether each chan nel of the timer array unit is provided with timer i/o pins differs depending on t he product. timer i/o pins of each product timer array unit n channel m input (tipq) / output (topq) 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) input ti00/to03/p31/rtcdiv/rtccl/pclbuz1/intp2 0 output to00/ti03/p30rtc1hz/intp1 1 i/o ti01/to01/p32/pclbuz0/intp5 input ti02/p52/segxx (78k0r/lf3: xx = 28, 78k0r/lg3: xx = 37, 78k0r/lh3: xx = 51) 2 output to02/p12/so02/txd2 input ti03/to00/p30rtc1hz/intp1 3 output to03/ti00/p31/rtcdiv/rtccl/pclbuz1/intp2 input ti04/p53/segxx (78k0r/lf3: xx = 27, 78k0r/lg3: xx = 36, 78k0r/lh3: xx = 50) 4 output to04/p13/so10/txd1 5 i/o ti05/to05/p16/intp10 6 i/o ? ti06/to06/p34/intp8 0 7 i/o ti07/to07/p33/intp3 0 i/o ti10/to10/p84 1 i/o ti11/to11/p85 2 i/o ti12/to12/p86 1 3 i/o ? ti13/to13/p87
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 253 jun 20, 2011 6.1 functions of timer array unit the timer array unit has the following functions. 6.1.1 functions of each channel when it operates independently independent operation functions are those functions that can be used for any channel regardless of the operation mode of the other channel (for details, refer to 6.6.1 overview of single-operation function and combination operation function ). (1) interval timer each timer of a unit can be used as a reference timer t hat generates an interrupt (in ttmmn) at fixed intervals. (2) square wave output a toggle operation is performed each time inttmpq is gener ated and a square wave with a duty factor of 50% is output from a timer output pin (topq). (3) external event counter each timer of a unit can be used as an event counter t hat generates an interrupt wh en the number of the valid edges of a signal input to the timer input pin (tipq) has reached a specific value. (4) divider function a clock input from a timer input pin (tipq) is divided and output from an output pin (topq). (5) input pulse inte rval measurement counting is started by the valid edge of a pulse signal input to a timer input pin (tipq). the count value of the timer is captured at the valid edge of the next pulse. in this way, the interval of the input pulse can be measured. (6) measurement of high-/low-l evel width of input signal counting is started by a single edge of t he signal input to the timer input pin (tipq), and the count value is captured at the other edge. in this way, the high-level or low-level width of the input signal can be measured. remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07 78k0r/lg3: mn = 00 to 07, 10 to 13, pq = 00 to 07 78k0r/lh3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 254 jun 20, 2011 6.1.2 functions of each channel when it operates with another channel combination operation functions are t hose functions that are attained by us ing the master channel (mostly the reference timer that controls cycles) and the slave channel s (timers that operate followi ng the master channel) in combination (for details, refer to 6.6.1 overview of single -operation function and combination operation function ). (1) pwm (pulse width modulator) output two channels are used as a set to generate a pulse with a specified period and a specified duty factor. (2) one-shot pulse output two channels are used as a set to generate a one-shot pul se with a specified delay time and a specified pulse width. (3) multiple pwm (pulse width modulator) output by extending the pwm function and using one master cha nnel and two or more slave channels, up to seven types of pwm signals that have a specific period and a specified duty factor can be generated. 6.1.3 lin-bus supporting function (channel 7 of timer array unit 0 only) (1) detection of wakeup signal the timer starts counting at the falling edge of a signal input to the serial data input pin (rxd3) of uart3 and the count value of the timer is captured at the rising edge. in this way, a low-level width can be measured. if the low- level width is greater than a specific valu e, it is recognized as a wakeup signal. (2) detection of sync break field the timer starts counting at the fallin g edge of a signal input to the serial data input pin (rxd3) of uart3 after a wakeup signal is detected, an d the count value of the timer is captured at the rising edge. in this way, a low-level width is measured. if the low-level width is greater than a specific value, it is recognized as a sync break field. (3) measurement of pulse width of sync field after a sync break field is detected, the low-level width a nd high-level width of the signa l input to the serial data input pin (rxd3) of uart3 are measured. from the bit inte rval of the sync field measured in this way, a baud rate is calculated.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 255 jun 20, 2011 6.2 configuration of timer array unit the timer array unit includes the following hardware. table 6-1. configuration of timer array unit item configuration timer/counter timer counter register mn (tcrmn) register timer data register mn (tdrmn) timer input tipq pin, rxd3 pin (for lin-bus) timer output topq pins, output controller ? peripheral enable register 0 (per0) ? timer clock select register m (tpsm) ? timer channel enable status register m (tem) ? timer channel start register m (tsm) ? timer channel stop register m (ttm) ? timer input select regi sters 0, 1 (tis0, tis1) ? timer output enable register p (toep) ? timer output register p (top) ? timer output level register p (tolp) ? timer output mode register p (tomp) control registers ? timer mode register mn (tmrmn) ? timer status register pq (tsrpq) ? input switch control register (isc) (channel 7 of timer array unit 0 only) ? noise filter enable registers 1, 2 (nfen1, nfen2) ? port mode registers 1, 3, 5, 8 (pm1, pm3, pm5, pm8) ? port registers 1, 3, 5, 8 (p1, p3, p5, p8) remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 0, pq = 00 to 04, 07 78k0r/lg3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 0, pq = 00 to 07 78k0r/lh3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 0, 1, pq = 00 to 07, 10 to 13 figures 6-1 and 6-2 show block diagrams.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 256 jun 20, 2011 figure 6-1. block diagram of timer array unit 0 to07 to03 to06 to05 to04 to02 to01 to00 te07 te03 te06 te05 te04 te02 te01 te00 toe07 toe03 toe06 toe05 toe04 toe02 toe01 toe00 ts07 ts03 ts06 ts05 ts04 ts02 ts01 ts00 tt07 tt03 tt06 tt05 tt04 tt02 tt01 tt00 tol07 tol03 tol06 tol05 tol04 tol02 tol01 tol00 tom07 tom03 tom06 tom05 tom04 tom02 tom01 tom00 tnfen 07 tnfen 06 tnfen 05 tnfen 04 tnfen 03 tnfen 02 tnfen 01 tnfen 00 tis07 tis03 tis06 tis05 tis04 tis02 tis01 tis00 channel 0 rxd3 ti02 ti03 ti05 ti06 to00 to02 to03 to04 to05 to06 inttm00 inttm02 inttm03 inttm04 inttm05 inttm06 inttm07 isc1 ti07 to07 pm32 cks01 ccs01 mas ter01 sts012 sts011 sts010 md012 cis011 cis010 md013 md011 md010 ovf 01 ck00 ck01 mck tclk tis01 tnfen01 f subc /2 ti00 rtc interval interrupt (intrtci) : f xt /2 6 to f xt /2 12 f subc /2 noise elimination enabled/disabled ti04 rtc interval interrupt (intrtci) : f xt /2 6 to f xt /2 12 f subc /2 0 0 rtcis 04 rtcis 00 tis00, rtcis00, sdiv tis04, rtcis04, sdiv 3 bits 0 to 3 are used by timer array unit 1 channel 1 of the d/a converter (damd1 = 1 setting) channel 0 of the d/a converter (damd0 = 1 setting) a/d converter (adtmd = 1, adtrs = 0 setting) a/d converter (adtmd = 1, adtrs = 1 setting) timer channel enable status register 0 (te0) timer channel stop register 0 (tt0) timer channel start register 0 (ts0) timer input select register 0 (tis0) timer input select register 1 (tis1) timer output register 0 (to0) timer output enable register 0 (toe0) timer output level register 0 (tol0) timer output mode register 0 (tom0) noise filter enable register 1 (nfen1) slave/master controller trigger signal to slave channel clock signal to slave channel interrupt signal to slave channel count clock selection selector selector selector edge detection noise elimination enabled/disabled operating clock selection trigger selection slave/master controller channel 1 ti01 (timer input pin) channel 2 channel 3 (serial input pin) channel 7 (lin-bus supported) selector channel 6 channel 5 channel 4 selector noise elimination enabled/disabled timer controller mode selection timer data register 01 (tdr01) timer counter register 01 (tcr01) timer status register 01 (tsr01) overflow interrupt controller output controller output latch (p32) to01 (timer output pin) inttm01 (timer interrupt) timer mode register 01 (tmr01) timer clock select register 0 (tps0) 4 4 f clk f clk /2 0 to f clk /2 15 selector f clk /2 0 to f clk /2 15 selector tau0en peripheral enable register 0 (per0) prescaler prs013 prs003 prs012 prs011 prs010 prs002 prs001 prs000 3 remark channels 5 and 6 of the 78k0r/lf3 are not pr ovided with timer i/o pins (ti05/to05, ti06/to06).
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 257 jun 20, 2011 figure 6-2. block diagram of timer array unit 1 timer clock select register 1 (tps1) prs113 4 prs103 prs112 prs111 prs110 prs102 prs101 prs100 4 f clk tau1en channel 0 ti10 ti12 ti13 to10 to12 to13 inttm10 inttm12 inttm13 pm85 cks11 ccs11 mas ter11 sts112 sts111 sts110 md112 cis111 cis110 md113 md111 md110 ovf 11 ck10 ck11 mck tclk output latch ( p85) tis11 tnfen11 to13 to12 to11 to10 te13 te12 te11 te10 toe13 toe12 toe11 toe10 ts13 ts12 ts11 ts10 tt13 tt12 tt11 tt10 tol13 tol12 tol11 tol10 tom13 tom12 tom11 tom10 tnfen 13 tnfen 12 tnfen 11 tnfen 10 tis13 tis12 tis11 tis10 f subc /2 timer output register 1 (to1) timer output enable register 1 (toe1) timer channel enable status register 1 (te1) timer channel stop register 1 (tt1) timer channel start register 1 (ts1) timer output level register 1 (tol1) timer output mode register 1 (tom1) noise filter enable register 2 (nfen2) timer input select register 1 (tis1) peripheral enable register 0 (per0) f clk /2 0 to f clk /2 15 selector f clk /2 0 to f clk /2 15 selector prescaler slave/master controller trigger signal to slave channel clock signal to slave channel interrupt signal to slave channel edge detection selector count clock selection trigger selection slave/master controller channel 1 ti11 (timer input pin) noise elimination enabled/disabled operating clock selection channel 2 channel 3 timer counter register 11 (tcr11) overflow timer data register 11 (tdr11) timer status register 11 (tsr11) interrupt controller output controller timer controller mode selection to11 (timer output pin) inttm11 (timer interrupt) timer mode register 11 (tmr11) remark for the channels 0 to 3 of 78k0r/lf3 and 78k0r/lg3, the timer i/o pins (ti10/ to10 to ti13/to13) are not mounted.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 258 jun 20, 2011 (1) timer/counter register mn (tcrmn) tcrmn is a 16-bit read-only register and is used to count clocks. the value of this counter is increment ed or decremented in synchronization with the rising edge of a count clock. whether the counter is incr emented or decremented depends on the opera tion mode that is selected by the mdmn3 to mdmn0 bits of tmrmn. figure 6-3. format of timer/ counter register mn (tcrmn) address: f0180h, f0181h (tcr00) to f018eh, f018fh (tcr07) after reset: ffffh r f01c0h, f01c1h (tcr10) to f01c6h, f01c7h (tcr13) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tcrmn the count value can be re ad by reading tcrmn. the count value is set to ffffh in the following cases. ? when the reset signal is generated ? when the tau0en bit (tau0) and tau1en bit (tau1) of peripheral enable register 0 (per0) is cleared the count value is cleared to 0000h in the following cases. ? when the start trigger is input in the capture mode ? when capturing has been completed in the capture mode ? when counting of the slave channel has been completed in the pwm output mode ? when counting of the master/slave channel has been completed in the one-shot pulse output mode ? when counting of the slave channel has been completed in the multiple pwm output mode caution the count value is not captured to tdrmn even when tcrmn is read. remark mn: unit number + channel number mn = 00 to 07, 10 to 13 f0181h (tcr00) f0180h (tcr00)
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 259 jun 20, 2011 the tcrmn register read value differs as follows according to operation mode changes and the operating status. table 6-2. tcrmn register read value in various operation modes tcrmn register read value note operation mode count mode operation mode change after reset operation mode change after count operation paused (ttmn = 1) operation restart after count operation paused (ttmn = 1) during start trigger wait status after one count interval timer mode count down ffffh undefined stop value ? capture mode count up 0000h undefined stop value ? event counter mode count down ffffh undefined stop value ? one-count mode count down ffffh undefined stop value ffffh capture & one- count mode count up 0000h undefined stop value capture value of tdrmn register + 1 note the read values of the tcrmn regi ster when tsmn has been set to "1" while temn = 0 are shown. the read value is held in the tcrmn register unt il the count operation starts. remark mn: unit number + channel number mn = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 260 jun 20, 2011 (2) timer data register mn (tdrmn) this is a 16-bit register from which a capture function and a compare function can be selected. the capture or compare function can be switched by sele cting an operation mode by using the mdmn3 to mdmn0 bits of tmrmn. the value of tdrmn can be changed at any time. this register can be read or written in 16-bit units. reset signal generation clears this register to 0000h. figure 6-4. format of timer data register mn (tdrmn) address: fff18h, fff19h (tdr00), fff1ah, fff1bh (tdr01), after reset: 0000h r/w fff64h, fff65h (tdr02) to fff6eh, fff6fh (tdr07) fff70h, fff71h (tdr10) to fff76h, fff77h (tdr13) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tdrmn (i) when tdrmn is used as compare register counting down is started from the value set to tdrmn. when the count value reaches 0000h, an interrupt signal (inttmmn) is generated. tdrmn ho lds its value until it is rewritten. caution tdrmn does not perform a captu re operation even if a capture trigger is input, when it is set to the compare function. (ii) when tdrpq is u sed as capture register the count value of tcrpq is captured to tdrpq when the capture trigger is input. a valid edge of the tipq pin can be selected as the c apture trigger. this selection is made by tmrpq. remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07 78k0r/lg3: mn = 00 to 07, 10 to 13, pq = 00 to 07 78k0r/lh3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13 fff19h (tdr00) fff18h (tdr00)
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 261 jun 20, 2011 6.3 registers controlling timer array unit timer array unit is controlled by the following registers. ? peripheral enable register 0 (per0) ? timer clock select register m (tpsm) ? timer mode register mn (tmrmn) ? timer status register pq (tsrpq) ? timer channel enable status register m (tem) ? timer channel start register m (tsm) ? timer channel stop register m (ttm) ? timer input select regi sters 0, 1 (tis0, tis1) ? timer output enable register p (toep) ? timer output register p (top) ? timer output level register p (tolp) ? timer output mode register p (tomp) ? input switch control register (isc) ? noise filter enable registers 1, 2 (nfen1, nfen2) ? port mode registers 1, 3, 5, 8 (pm1, pm3, pm5, pm8) ? port registers1, 3, 5, 8 (p1, p3, p5, p8) remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: m = 0, 1, mn = 00 to 07, 10 to 13, p = 0, pq = 00 to 04, 07 78k0r/lg3: m = 0, 1, mn = 00 to 07, 10 to 13, p = 0, pq = 00 to 07 78k0r/lh3: m = 0, 1, mn = 00 to 07, 10 to 13, p = 0, 1, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 262 jun 20, 2011 (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to r educe the power consumption and noise. when the timer array unit 0 is used, be sure to set bit 0 (tau0en) of this register to 1. when the timer array unit 1 is used, be sure to set bit 1 (tau1en) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. caution when setting the timer array uni t, be sure to set taumen to 1 first. if taumen = 0, writing to a control register of the timer array unit is i gnored, and all read values are default values. figure 6-5. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> per0 rtcen dacen adcen iicaen note sau1en sau0en tau1en tau0en taumen control of timer array unit m input clock 0 stops supply of input clock. ? sfr used by the timer array unit m cannot be written. ? the timer array unit m is in the reset status. 1 supplies input clock. ? sfr used by the timer array unit m can be read/written. note 78k0r/lg3, 78k0r/lh3 only (2) timer clock select register m (tpsm) tpsm is a 16-bit register that is used to select tw o types of operation clocks (ckm0, ckm1) that are commonly supplied to each channel. ckm1 is selected by bits 7 to 4 of tpsm, and ckm0 is selected by bits 3 to 0. rewriting of tpsm during timer operation is possible only in the following cases. rewriting of prsm00 to prsm03 bits: possible only when all the channels set to cksmn = 0 are in the operation stopped state (temn = 0) rewriting of prsm10 to prsm13 bits: possible only when all the channels set to cksmn = 1 are in the operation stopped state (temn = 0) tpsm can be set by a 16-bit memory manipulation instruction. the lower 8 bits of tpsm can be set with an 8-bi t memory manipulation instruction with tpsml. reset signal generation clears this register to 0000h. remark mn: unit number + channel number m = 0, 1, mn = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 263 jun 20, 2011 figure 6-6. format of timer clock select register m (tpsm) address: f01b6h, f01b7h (tps0) after reset: 0000h r/w f01deh, f01dfh (tps1) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tpsm 0 0 0 0 0 0 0 0 prs m13 prs m12 prs m11 prs m10 prs m03 prs m02 prs m01 prs m00 selection of operation clock (ckmk) notes 1,2 prs mk3 prs mk2 prs mk1 prs mk0 f clk = 2 mhz f clk = 5 mhz f clk = 10 mhz f clk = 20 mhz 0 0 0 0 f clk 2 mhz 5 mhz 10 mhz 20 mhz 0 0 0 1 f clk /2 1 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 0 f clk /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f clk /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f clk /2 4 125 khz 312.5 khz 625 khz 1.25 mhz 0 1 0 1 f clk /2 5 62.5 khz 156.2 khz 312.5 khz 625 khz 0 1 1 0 f clk /2 6 31.25 khz 78.1 khz 156.2 khz 312.5 khz 0 1 1 1 f clk /2 7 15.62 khz 39.1 khz 78.1 khz 156.2 khz 1 0 0 0 f clk /2 8 7.81 khz 19.5 khz 39.1 khz 78.1 khz 1 0 0 1 f clk /2 9 3.91 khz 9.76 khz 19.5 khz 39.1 khz 1 0 1 0 f clk /2 10 1.95 khz 4.88 khz 9.76 khz 19.5 khz 1 0 1 1 f clk /2 11 976 hz 2.44 khz 4.88 khz 9.76 khz 1 1 0 0 f clk /2 12 488 hz 1.22 khz 2.44 khz 4.88 khz 1 1 0 1 f clk /2 13 244 hz 610 hz 1.22 khz 2.44 khz 1 1 1 0 f clk /2 14 122 hz 305 hz 610 hz 1.22 khz 1 1 1 1 f clk /2 15 61 hz 153 hz 305 hz 610 hz notes 1. when changing the clock selected for f clk (by changing the system clock c ontrol register (ckc) value), stop the timer array unit (tt0 = 00ffh, tt1 = 000fh). 2. only in the case of sdiv=0, ccsmn=1 and tismn=1, continuously use of taum is allowed, even when changing cpu clock. however, the following limitation is existing. ? when changing cpu clock, source clock decrease/increase occurs as follows. main clock subsystem clock (css = 0 1): ? 1 clock subsystem clock main clock (css = 1 0): +1 clock caution be sure to clear bits 15 to 8 to ?0?. remarks 1. f clk : cpu/peripheral hardware clock frequency 2. k = 0, 1 3. mn: unit number + channel number m = 0, 1, mn = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 264 jun 20, 2011 (3) timer mode register mn (tmrmn) tmrmn sets an operation mode of channel n of timer array uni t m. it is used to select an operation clock (mck), a count clock, whether the timer operates as the master or a slave, a start trigger and a capture trigger, the valid edge of the timer input, and an operation mode (interval, capture, event counter, one-count, or capture & one- count). rewriting tmrmn is prohibited when the register is in oper ation (when tem = 1). however, bits 7 and 6 (cismn1, cismn0) can be rewritten even while the register is oper ating with some functions (when tem = 1) (for details, see 6.7 operation of timer array unit as independent channel and 6.8 operation of plural channels of timer array unit ). tmrmn can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 6-7. format of timer m ode register mn (tmrmn) (1/4) address: f0190h, f0191h (tmr00) to f019eh, f019fh (tmr07) after reset: 0000h r/w f01c8h, f01c9h (tmr10) to f01ceh, f01cfh (tmr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrmn cks mn 0 0 ccs mn mast ermn sts mn2 sts mn1 sts mn0 cis mn1 cis mn0 0 0 md mn3 md mn2 md mn1 md mn0 cks mn selection of operation cl ock (mck) of channel n 0 operation clock ckm0 set by tpsm register 1 operation clock ckm1 set by tpsm register operation clock mck is used by the edge detector. a count clock (tclk) and a sampling clock are generated depending on the setting of the ccsmn bit. ccs mn selection of count clock (tclk) of channel n 0 operation clock mck specified by cksmn bit 1 valid edge of input signal input from tipq pin, f sub /2, f sub/ 4, or intrtc1 (the timer input used with channel x is selected by using tism register). count clock tclk is used for the timer/counter, output controller, and interrupt controller. if ccsmn = 1, use the count clock under the following condition. ? the frequency of the operating clock selected by using cksmn the frequency of the clock selected by using tismn 2 caution be sure to clear bits 14, 13, 5, and 4 to ?0?. remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07 78k0r/lg3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07 78k0r/lh3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 265 jun 20, 2011 figure 6-7. format of timer m ode register mn (tmrmn) (2/4) address: f0190h, f0191h (tmr00) to f019eh, f019fh (tmr07) after reset: 0000h r/w f01c8h, f01c9h (tmr10) to f01ceh, f01cfh (tmr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrmn cks mn 0 0 ccs mn mast ermn sts mn2 sts mn1 sts mn0 cis mn1 cis mn0 0 0 md mn3 md mn2 md mn1 md mn0 mas ter mn selection of slave/master of channel n 0 operates as slave channel with combination operation function. 1 operates as master channel with combination operation function. only the even channel can be set as a master channel (mastermn = 1). be sure to use the odd channel as a slave channel (mastermn = 0). clear mastermn to 0 for a channel that is used with the independent operation function. sts mn2 sts mn1 sts mn0 setting of start trigger or capture trigger of channel n 0 0 0 only software trigger start is valid (other trigger sources are unselected). 0 0 1 valid edge of tipq pin input signal, f sub /2, f sub/ 4, or intrtc1 is used as both the start trigger and capture trigger. 0 1 0 both the edges of tipq pin input signal, f sub /2, f sub/ 4, or intrtc1 are used as a start trigger and a capture trigger. 1 0 0 interrupt signal of the master channel is us ed (when the channel is used as a slave channel with the combination operation function). other than above setting prohibited cis mn1 cis mn0 selection of valid edge of tipq pin input signal , f sub /2, f sub/ 4, or intrtc1 (the timer input used with channel x is selected by using tism register). 0 0 falling edge 0 1 rising edge 1 0 both edges (when low-level width is measured) start trigger: falling edge, capture trigger: rising edge 1 1 both edges (when high-level width is measured) start trigger: rising edge, capture trigger: falling edge if both the edges are specified when the value of the st smn2 to stsmn0 bits is other than 010b, set the cismn1 to cismn0 bits to 10b. caution be sure to clear bits 14, 13, 5, and 4 to ?0?. remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07 78k0r/lg3: mn = 00 to 07, 10 to 13, pq = 00 to 07 78k0r/lh3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 266 jun 20, 2011 figure 6-7. format of timer m ode register mn (tmrmn) (3/4) address: f0190h, f0191h (tmr00) to f019eh, f019fh (tmr07) after reset: 0000h r/w f01c8h, f01c9h (tmr10) to f01ceh, f01cfh (tmr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrmn cks mn 0 0 ccs mn mast ermn sts mn2 sts mn1 sts mn0 cis mn1 cis mn0 0 0 md mn3 md mn2 md mn1 md mn0 md mn3 md mn2 md mn1 md mn0 operation mode of channel n count operation of tcr independent operation 0 0 0 1/0 interval timer mode counting down possible 0 1 0 1/0 capture mode counting up possible 0 1 1 0 event counter mode counting down possible 1 0 0 1/0 one-count mode counting down impossible 1 1 0 0 capture & one-count mode counting up possible other than above setting prohibited the operation of mdmn0 bits varies depending on each operation mode (see following table). cautions 1. be sure to clear bits 14, 13, 5, and 4 to ?0?. 2. channel 5 of timer array unit 0 and channels 0 to 3 of timer array unit 1 of the 78k0r/lf3 can be set only to the interval mode. 3. channel 6 of timer array unit 0 of the 78k0r /lf3 can be set only to the interval mode and one-count mode (when using as master). 4. channels 0 to 3 of timer array unit 1 of th e 78k0r/lg3 can be set only to the interval mode. remark mn: unit number + channel number mn = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 267 jun 20, 2011 figure 6-7. format of timer m ode register mn (tmrmn) (4/4) operation mode (value set by the mdmn3 to mdmn1 bits (see table above)) md mn0 setting of starting counting and interrupt 0 timer interrupt is not generated when counting is started (timer output does not change, either). ? interval timer mode (0, 0, 0) ? capture mode (0, 1, 0) 1 timer interrupt is generated when counting is started (timer output also changes). ? event counter mode (0, 1, 1) 0 timer interrupt is not generated when counting is started (timer output does not change, either). 0 start trigger is invalid during counting operation. at that time, interrupt is not generated, either. ? one-count mode (1, 0, 0) 1 start trigger is valid during counting operation note . at that time, interrupt is also generated. ? capture & one-count mode (1, 1, 0) 0 timer interrupt is not generated when counting is started (timer output does not change, either). start trigger is invalid during counting operation. at that time interrupt is not generated, either. other than above setting prohibited note if the start trigger (tsmn = 1) is issued during op eration, the counter is cleared, an interrupt is generated, and recounting is started. remark mn: unit number + channel number mn = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 268 jun 20, 2011 (4) timer status register pq (tsrpq) tsrpq indicates the overflow status of the counter of channel n. tsrpq is valid only in the capture mode (mdpq3 to mdpq1 = 010b) and capture & one-count mode (mdpq3 to mdpq1 = 110b). it will not be set in any other mode. see table 6-3 for the operation of the ovfpq bit in each operation mode and set/clear conditions. tsrpq can be read by a 16-bit memory manipulation instruction. the lower 8 bits of tsrpq can be set with an 8-bi t memory manipulation instruction with tsrpql. reset signal generation clears this register to 0000h. figure 6-8. format of timer status register pq (tsrpq) address: f01a0h, f01a1h (tsr00) to f01aeh, f01afh (tsr07) after reset: 0000h r f01d0h, f01d1h (tsr10) to f01d6h, f01d7h (tsr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tsrpq 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ovf pq ovf pq counter overflow status of channel q 0 overflow does not occur. 1 overflow occurs. when ovfpq = 1, this flag is clea red (ovfpq = 0) when the next va lue is captured without overflow. remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13 table 6-3. ovfpq bit operation and set/cl ear conditions in each operation mode timer operation mode ovf pq set/clear conditions clear when no overflow has occurred upon capturing ? capture mode ? capture & one-count mode set when an overflow has occurred upon capturing clear ? interval timer mode ? event counter mode ? one-count mode set ? (use prohibited, not set/cleared) remark the ovfpq bit does not change immediately after the counter has overflowed, but changes upon the subsequent capture.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 269 jun 20, 2011 (5) timer channel enable status register m (tem) tem is used to enable or stop the timer operation of each channel. when a bit of timer channel start register m (tsm) is set to 1, the corresponding bit of this register is set to 1. when a bit of timer channel stop register m (ttm) is set to 1, the corresponding bit of this register is cleared to 0. tem can be read by a 16-bit memory manipulation instruction. the lower 8 bits of tem can be set with a 1-bit or 8-bit memory manipulation instruction with teml. reset signal generation clears this register to 0000h. figure 6-9. format of timer channe l enable status register m (tem) address: f01b0h, f01b1h after reset: 0000h r symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 te0 0 0 0 0 0 0 0 0 te07 te06 te05 te04 te03 te02 te01 te00 address: f01d8h, f01d9h after reset: 0000h r symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 te1 0 0 0 0 0 0 0 0 0 0 0 0 te13 te12 te11 te10 te mn indication of operation enable/stop status of channel n 0 operation is stopped. 1 operation is enabled. remark mn: unit number + channel number m = 0, 1, mn = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 270 jun 20, 2011 (6) timer channel start register m (tsm) tsm is a trigger register that is used to clear a ti mer counter (tcrmn) and start the counting operation of each channel. when a bit (tsmn) of this register is set to 1, the corresponding bit (temn) of timer channel enable status register m (tem) is set to 1. tsmn is a trigger bit and cleared immediately when temn = 1. tsm can be set by a 16-bit memory manipulation instruction. the lower 8 bits of tsm can be set with a 1-bit or 8-bit memory manipulation instruction with tsml. reset signal generation clears this register to 0000h. figure 6-10. format of timer channel start register m (tsm) address: f01b2h, f01b3h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ts0 0 0 0 0 0 0 0 0 ts07 ts06 ts05 ts04 ts03 ts02 ts01 ts00 address: f01dah, f01dbh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ts1 0 0 0 0 0 0 0 0 0 0 0 0 ts13 ts12 ts11 ts10 tsmn operation enable (sta rt) trigger of channel n 0 no trigger operation 1 temn is set to 1 and the count operation becomes enabled. the tcrmn count operation start in the count ope ration enabled state varies depending on each operation mode (see table 6-4). caution be sure to clear bits 15 to 8 of ts0 and bits 15 to 4 of ts1 to ?0?. remarks 1. when the tsm register is read, 0 is always read. 2. mn: unit number + channel number m = 0, 1, mn = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 271 jun 20, 2011 table 6-4. operations from count oper ation enabled state to tcrmn count start timer operation mode operati on when tsmn = 1 is set ? interval timer mode no operation is carried out from start tr igger detection (tsmn=1) until count clock generation. the first count clock loads the value of tdrmn to tcrmn and the subsequent count clock performs count down operation (see 6.3 (6) (a) start timing in interval timer mode ). ? event counter mode writing 1 to tsmn bit loads the value of tdrmn to tcrmn. the subsequent count clock performs count down operation. the external trigger detection selected by stsmn2 to stsmn0 bits in the tmrmn register does not start count operation (see 6.3 (6) (b) start timing in event counter mode ). ? capture mode no operation is carried out from star t trigger detection until count clock generation. the first count clock loads 0000h to tcrmn and the subsequent count clock performs count up operation (see 6.3 (6) (c) start timing in capture mode ). ? one-count mode when temn = 0, writing 1 to tsmn bit sets the start trigger wait state. no operation is carried out from star t trigger detection until count clock generation. the first count clock loads the value of tdrmn to tcrmn and the subsequent count clock performs count down operation (see 6.3 (6) (d) start timing in one- count mode ). ? capture & one-count mode when temn = 0, writing 1 to tsmn bit sets the start trigger wait state. no operation is carried out from star t trigger detection until count clock generation. the first count clock loads 0000h to tcrmn and the subsequent count clock performs count up operation (see 6.3 (6) (e) start timing in capture & one- count mode ). cautions 1. channel 5 of timer array unit 0 and channe ls 0 to 3 of timer array unit 1 of the 78k0r/lf3 can be set only to the interval mode. 2. channel 6 of timer array unit 0 of the 78k0r /lf3 can be set only to the interval mode and one-count mode (when using as master). 3. channels 0 to 3 of timer array unit 1 of th e 78k0r/lg3 can be set only to the interval mode. (a) start timing in interval timer mode <1> writing 1 to tsmn sets temn = 1 <2> the write data to tsmn is held until count clock generation. <3> tcrmn holds the initial val ue until count clock generation. <4> on generation of count clock, the ?tdrmn value? is loaded to tcrmn and count starts. remark mn: unit number + channel number mn = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 272 jun 20, 2011 figure 6-11. start timing (in interval timer mode) tsmn (write) temn count clock f clk tcrmn inttmmn initial value tdrmn value when mdmn0 = 1 is set <1> <2> <3> <4> start trigger detection signal tsmn (write) hold signal caution in the first cycle operation of count clock a fter writing tsmn, an error at a maximum of one clock is generated since count start delays until count cl ock has been generated. when the information on count start timing is necessary, an interrupt can be generated at count start by setting mdmn0 = 1. remark mn: unit number + channel number mn = 00 to 07, 10 to 13 (b) start timing in event counter mode <1> while tepq is set to 0, tcrpq holds the initial value. <2> writing 1 to tspq sets 1 to tepq. <3> as soon as 1 has been written to tspq and 1 has been set to tepq, the "tdrpq value" is loaded to tcrpq to start counting. <4> after that, the tcrpq value is count ed down according to the count clock. figure 6-12. start timing (in event counter mode) tepq f clk tcrpq tdrpq value <1> <1> <2> <3> tdrpq value-1 initial value tspq (write) count clock start trigger detection signal tspq (write) hold signal remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 273 jun 20, 2011 (c) start timing in capture mode <1> writing 1 to tspq sets tepq = 1 <2> the write data to tspq is held until count clock generation. <3> tcrpq holds the initial val ue until count clock generation. <4> on generation of count clock, 0000h is loaded to tcrpq and count starts. figure 6-13. start timing (in capture mode) tepq f clk tcrpq inttmpq 0000h <1> <2> <3> <4> initial value when mdpq0 = 1 is set tspq (write) count clock start trigger detection signal tspq (write) hold signal caution in the first cycle operation of count clock afte r writing tspq, an error at a maximum of one clock is generated since count start delays until count cloc k has been generated. when the information on count start timing is necessary, an interrupt can be generated at count start by setting mdpq0 = 1. remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 274 jun 20, 2011 (d) start timing in one-count mode <1> writing 1 to tspq sets tepq = 1 <2> enters the start trigger input wait status, and tcrpq holds the initial value. <3> on start trigger detection , the ?tdrpq value? is loaded to tcrpq and count starts. figure 6-14. start timing (in one-count mode) tepq f clk tcrpq start trigger input wait status tdrpq value initial value <1> <2> <3> tspq (write) count clock note start trigger detection signal tspq (write) hold signal tin edge detection signal note when the one-count mode is set, the operation cloc k (mck) is selected as count clock (ccspq = 0). caution an input signal sampling error is generated since operation starts upon start trigger detection (the error is one count clock when tipq is used). remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07, 06 (only when used as the master) 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 275 jun 20, 2011 (e) start timing in capture & one-count mode <1> writing 1 to tspq sets tepq = 1 <2> enters the start trigger input wait status, and tcrpq holds the initial value. <3> on start trigger detection , 0000h is loaded to tcrpq and count starts. figure 6-15. start timing (in capture & one-count mode) tepq f clk tcrpq 0000h tspq (write) count clock note start trigger detection signal tspq (write) hold signal tin edge detection signal start trigger input wait status initial value <2> <3> <1> note when the capture & one-count mode is set, the operati on clock (mck) is selected as count clock (ccspq = 0). caution an input signal sampling error is generate d since operation starts upon start trigger detection (the error is one count clock when tipq is used). (7) timer channel stop register m (ttm) ttm is a trigger register that is used to clear a time r counter (tcrmn) and start t he counting operation of each channel. when a bit (ttmn) of this register is set to 1, the corresp onding bit (temn) of timer chan nel enable status register 0 (tem) is cleared to 0. ttmn is a trigger bit and cleared to 0 immediately when temn = 0. ttm can be set by a 16-bit memory manipulation instruction. the lower 8 bits of ttm can be set with a 1-bit or 8-bit memory manipulation instruction with ttml. reset signal generation clears this register to 0000h. remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07 78k0r/lg3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07 78k0r/lh3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 276 jun 20, 2011 figure 6-16. format of timer channel stop register m (ttm) address: f01b4h, f01b5h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tt0 0 0 0 0 0 0 0 0 tt07 tt06 tt05 tt04 tt03 tt02 tt01 tt00 address: f01dch, f01ddh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tt1 0 0 0 0 0 0 0 0 0 0 0 0 tt13 tt12 tt11 tt10 ttmn operation stop trigger of channel n 0 no trigger operation 1 operation is stopped (s top trigger is generated). caution be sure to clear bits 15 to 8 of tt0 and bits 15 to 4 of tt1 to ?0?. remarks 1. when the ttm register is read, 0 is always read. 2. mn: unit number + channel number m = 0, 1, mn = 00 to 07, 10 to 13 (8) timer input select registers 0, 1 (tis0, tis1) tis0 and tis1 use can be set to the input signal of a ti mer input pin (tipq), half t he frequency of the subsystem clock (f sub /2), one fourth the frequency of the subsystem clock (f sub /4), or an rtc interval interrupt (intrtci) as the timer input. the timer input can be selected for each channel. tis0 and tis1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13 figure 6-17. format of timer input select registers 0, 1 (tis0, tis1) (1/2) ? 78k0r/lf3 address: fff3eh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tis0 tis07 0 0 tis04 tis03 tis02 tis01 tis00 address: fff4eh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tis1 0 0 rtcis04 rtcis00 0 0 0 0
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 277 jun 20, 2011 figure 6-17. format of timer input select registers 0, 1 (tis0, tis1) (2/2) ? 78k0r/lg3 address: fff3eh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tis0 tis07 tis06 tis05 tis04 tis03 tis02 tis01 tis00 address: fff4eh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tis1 0 0 rtcis04 rtcis00 0 0 0 0 ? 78k0r/lh3 address: fff3eh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tis0 tis07 tis06 tis05 tis04 tis03 tis02 tis01 tis00 address: fff4eh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tis1 0 0 rtcis04 rtcis00 tis13 tis12 tis11 tis10 ? channels 1 to 3 and 5 to 7 of timer array unit 0 and channels 0 to 3 of timer array unit 1 tispq sdiv selection of timer input used with chann el (pq = 01, 02, 03, 05, 06, 07, 10, 11, 12, 13) 0 input signal of timer input pin (tipq) 0 f sub /2 1 1 f sub /4 ? channels 0 and 4 of timer array unit 0 tispq rtcispq sdiv selection of timer input used with channel (pq = 00, 04) 0 input signal of timer input pin (tipq) 0 f sub /2 0 1 f sub /4 0 rtc interval interrupt (intrtci) 1 1 1 setting prohibited caution when the lin-bus communication function is used, select the input signal of the rxd3 pin by setting isc1 to 1 and tis07 = 0. remarks 1. pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13 2. : don?t care 3. f sub : subsystem select clock 4. sdiv: bit 3 of the system clock control register (ckc)
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 278 jun 20, 2011 (9) timer output enable register p (toep) toep is used to enable or disable timer output of each channel. channel q for which timer output has been enabled becomes unable to rewrite the value of the topq bit of the timer output register (top) described later by software, and the va lue reflecting the setting of the timer output function through the count operation is output from the timer output pin (topq). toep can be set by a 16-bit memory manipulation instruction. the lower 8 bits of toep can be set with a 1-bit or 8-bit memory manipulation instruction with toepl. reset signal generation clears this register to 0000h. figure 6-18. format of timer output enable register p (toep) ? 78k0r/lf3 address: f01bah, f01bbh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 toe0 0 0 0 0 0 0 0 0 toe 07 0 0 toe 04 toe 03 toe 02 toe 01 toe 00 ? 78k0r/lg3 address: f01bah, f01bbh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 toe0 0 0 0 0 0 0 0 0 toe 07 toe 06 toe 05 toe 04 toe 03 toe 02 toe 01 toe 00 ? 78k0r/lh3 address: f01bah, f01bbh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 toe0 0 0 0 0 0 0 0 0 toe 07 toe 06 toe 05 toe 04 toe 03 toe 02 toe 01 toe 00 address: f01e2h, f01e3h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 toe1 0 0 0 0 0 0 0 0 0 0 0 0 toe 13 toe 12 toe 11 toe 10 toe pq timer output enable/disable of channel q 0 the topq operation stopped by count operation (timer channel output bit). writing to the topq bit is enabled. the topq pin functions as data output, and it outputs the level set to the topq bit. the output level of the topq pin can be manipulated by software. 1 the topq operation enabled by count oper ation (timer channel output bit). writing to the topq bit is di sabled (writing is ignored). the topq pin functions as timer output, and the toepq is set or reset depending on the timer operation. the topq pin outputs the square-wave or pwm depending on the timer operation. (caution and remark are given on the next page.)
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 279 jun 20, 2011 cautions 1. for 78k0r/lf3, be sure to clear bits 15 to 8, 6 and 5 of toe0 to ?0?. 2. for 78k0r/lg3, be sure to clear bits 15 to 8 of toe0 to ?0?. 3. for 78k0r/lh3, be sure to clear bit 15 to 8 of toe0, bits 15 to 4 of toe1 to ?0?. remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: p = 0, pq = 00 to 04, 07 78k0r/lg3: p = 0, pq = 00 to 07 78k0r/lh3: p = 0, 1, pq = 00 to 07, 10 to 13 (10) timer output register p (top) top is a buffer register of timer output of each channel. the value of each bit in this register is output from the timer output pin (topq) of each channel. this register can be rewritten by software only when ti mer output is disabled (toepq = 0). when timer output is enabled (toepq = 1), rewriting this register by softwar e is ignored, and the value is changed only by the timer operation. to use the p30/to00, p32/to01, p 12/to02, p31/to03, p13/to 04, p16/to05, p34/to06, p33/to07, p84/to10, p85/to11, p86/to12, or p87/to13 pi n as a port function pin, set the corresponding topq bit to ?0?. top can be set by a 16-bit memory manipulation instruction. the lower 8 bits of top can be set with an 8-bi t memory manipulation instruction with topl. reset signal generation clears this register to 0000h.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 280 jun 20, 2011 figure 6-19. format of timer output register p (top) ? 78k0r/lf3 address: f01b8h, f01b9h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 to0 0 0 0 0 0 0 0 0 to0 7 0 0 to0 4 to0 3 to0 2 to0 1 to0 0 ? 78k0r/lg3 address: f01b8h, f01b9h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 to0 0 0 0 0 0 0 0 0 to0 7 to0 6 to0 5 to0 4 to0 3 to0 2 to0 1 to0 0 ? 78k0r/lh3 address: f01b8h, f01b9h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 to0 0 0 0 0 0 0 0 0 to0 7 to0 6 to0 5 to0 4 to0 3 to0 2 to0 1 to0 0 address: f01e0h, f01e1h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 to1 0 0 0 0 0 0 0 0 0 0 0 0 to1 3 to1 2 to1 1 to1 0 to pq timer output of channel q 0 timer output value is ?0?. 1 timer output value is ?1?. cautions 1. for 78k0r/lf3, be sure to clear bits 15 to 8, 6 and 5 of to0 to ?0?. 2. for 78k0r/lg3, be sure to cl ear bits 15 to 8 of to0 to ?0?. 3. for 78k0r/lh3, be sure to clear bit 15 to 8 of to0, bits 15 to 4 of to1 to ?0?. remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: p = 0, pq = 00 to 04, 07 78k0r/lg3: p = 0, pq = 00 to 07 78k0r/lh3: p = 0, 1, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 281 jun 20, 2011 (11) timer output level register p (tolp) tolp is a register that controls t he timer output level of each channel. the setting of the inverted output of channel q by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (toepq = 1) in the combination operation mode (tompq = 1). in the toggle mode (tompq = 0), this register setting is invalid. tolp can be set by a 16-bit memory manipulation instruction. the lower 8 bits of tolp can be set with an 8-bi t memory manipulation instruction with tolpl. reset signal generation clears this register to 0000h. figure 6-20. format of timer output level register p (tolp) ? 78k0r/lf3 address: f01bch, f01bdh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tol0 0 0 0 0 0 0 0 0 tol 07 0 0 tol 04 tol 03 tol 02 tol 01 tol 00 ? 78k0r/lg3 address: f01bch, f01bdh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tol0 0 0 0 0 0 0 0 0 tol 07 tol 06 tol 05 tol 04 tol 03 tol 02 tol 01 tol 00 ? 78k0r/lh3 address: f01bch, f01bdh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tol0 0 0 0 0 0 0 0 0 tol 07 tol 06 tol 05 tol 04 tol 03 tol 02 tol 01 tol 00 address: f01e4h, f01e5h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tol1 0 0 0 0 0 0 0 0 0 0 0 0 tol 13 tol 12 tol 11 tol 10 tolpq control of timer output level of channel q 0 positive logic out put (active-high) 1 inverted output (active-low) cautions 1. for 78k0r/lf3, be sure to clear bits 15 to 8, 6 and 5 of tol0 to ?0?. 2. for 78k0r/lg3, be sure to clear bits 15 to 8 of tol0 to ?0?. 3. for 78k0r/lh3, be sure to clear bit 15 to 8 of tol0, bits 15 to 4 of tol1 to ?0?. remarks 1. if the value of this register is rewritten during timer operation, the timer output is inverted when the timer output signal changes next, instead of immedi ately after the register value is rewritten. 2. pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: p = 0, pq = 00 to 04, 07 78k0r/lg3: p = 0, pq = 00 to 07 78k0r/lh3: p = 0, 1, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 282 jun 20, 2011 (12) timer output mode register p (tomp) tomp is used to control the timer output mode of each channel. when a channel is used for the combination operation f unction (pwm output, one-shot pulse output, or multiple pwm output), set the corresponding bi t of the slave channel to 1. the setting of each channel q by this register is reflected at the timing when the timer output signal is set or reset while the timer output is enabled (toepq = 1). tomp can be set by a 16-bit memory manipulation instruction. the lower 8 bits of tomp can be set with an 8-bi t memory manipulation instruction with tompl. reset signal generation clears this register to 0000h. figure 6-21. format of timer output mode register p (tomp) ? 78k0r/lf3 address: f01beh, f01bfh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tom0 0 0 0 0 0 0 0 0 tom 07 0 0 tom 04 tom 03 tom 02 tom 01 tom 00 ? 78k0r/lg3 address: f01beh, f01bfh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tom0 0 0 0 0 0 0 0 0 tom 07 tom 06 tom 05 tom 04 tom 03 tom 02 tom 01 tom 00 ? 78k0r/lh3 address: f01beh, f01bfh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tom0 0 0 0 0 0 0 0 0 tom 07 tom 06 tom 05 tom 04 tom 03 tom 02 tom 01 tom 00 address: f01e6h, f01e7h after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tom1 0 0 0 0 0 0 0 0 0 0 0 0 tom 13 tom 12 tom 11 tom 10 tom pq control of timer output mode of channel q 0 toggle mode (to produce toggle output by timer interrupt request signal (inttmpq)) 1 combination operation mode (set by the timer interrupt request signal (inittmpq) of the master channel, and reset by the timer interrupt request signal (inittmpr) of the slave channel) cautions 1. for 78k0r/lf3, be sure to clear bits 15 to 8, 6 and 5 of tom0 to ?0?. 2. for 78k0r/lg3, be sure to clear bits 15 to 8 of tom0 to ?0?. 3. for 78k0r/lh3, be sure to clear bit 15 to 8 of tom0, bits 15 to 4 of tom1 to ?0?. (remark is listed on the next page.)
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 283 jun 20, 2011 remark pq: unit number + channel number (only for channels provided with timer i/o pins) <1> 78k0r/lf3: ? p = 0, q = 0 to 4, 7 (q = 0, 2, 4 for master channel) q < r 7 (where r is a consecutive integer greater than q) <2> 78k0r/lg3: ? p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel) q < r 7 (where r is a consecutive integer greater than q) <3> 78k0r/lh3: ? p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel) q < r 7 (where r is a consecutive integer greater than q) ? p = 1, q = 0 to 3 (q = 0, 2 for master channel) q < r 3 (where r is a consecutive integer greater than q) (13) input switch control register (isc) isc is used to implement lin-bus communication operation with channel 7 of timer array unit 0 in association with serial array unit 1. when bit 1 of this register is set to 1, the input signal of the serial data input pin (rxd3) is selected as a timer input signal. isc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 6-22. format of input switch control register (isc) address: fff3ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 isc4 isc3 isc2 isc1 isc0 isc1 switching channel 7 input of timer array unit 0 uses the input signal of the ti07 pin as a timer input (normal operation). 1 input signal of r x d3 pin is used as timer input (wakeup signal detection). caution be sure to clear bits 5 to 7 to ?0?. remarks 1. when the lin-bus communication function is used, se lect the input signal of the rxd3 pin by setting isc1 to 1. 2. bits 0 and 2 to 4 of isc are not used with tau0.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 284 jun 20, 2011 (14) noise filter enable regi sters 1, 2 (nfen1, nfen2) nfen1 and nfen2 are used to set whether the noise fi lter can be used for the timer input signal to each channel. enable the noise filter by setting the corresponding bi ts to 1 on the pins in need of noise removal. when the noise filter is on, match detection and syn chronization of the 2 clocks is performed with the cpu/peripheral hardware clock (f clk ). when the noise filter is off, onl y synchronization is performed with the cpu/peripheral hardware clock (f clk ). nfen1, nfen2 can be set by a 1-bit or 8- bit memory manipulation instruction. reset signal generation clears these registers to 00h.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 285 jun 20, 2011 figure 6-23. format of noise filter enable register 1 (nfen1) (1/2) ? 78k0r/lf3 address: f0061h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 nfen1 tnfen07 0 0 tnfen04 tnfen03 tnfen02 tnfen01 tnfen00 ? 78k0r/lg3, 78k0r/lh3 address: f0061h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 nfen1 tnfen07 tnfen06 tnfen05 tnfen04 tnfen03 tnfen02 tnfen01 tnfen00 tnfen07 enable/disable using noise filter of ti07/ to07/p33/intp3 pin or rxd3/p50/segz pin input signal note (78k0r/lf3: z = 30, 78k0r/lg3: z = 39, 78k0r/lh3: z = 53) 0 noise filter off 1 noise filter on tnfen06 enable/disable using noise filter of ti06/to06/p34/intp8 pin input signal 0 noise filter off 1 noise filter on tnfen05 enable/disable using noise filter of ti05/to05/p16/intp10 pin input signal 0 noise filter off 1 noise filter on tnfen04 enable/disable using noise filter of ti04/p53/segz pin input signal (78k0r/lf3: z = 27, 78k0r/lg3: z = 36, 78k0r/lh3: z = 50) 0 noise filter off 1 noise filter on tnfen03 enable/disable using noise filter of ti03/to03/p30/rtc1hz/intp1 pin input signal 0 noise filter off 1 noise filter on tnfen02 enable/disable using noise filter of ti02/p52/segz pin input signal (78k0r/lf3: z = 28, 78k0r/lg3: z = 37, 78k0r/lh3: z = 51) 0 noise filter off 1 noise filter on note the applicable pin can be switched by setting isc1 of the isc register. isc1 = 0: whether or not to use the noise filter of ti07 pin can be selected. isc1 = 1: whether or not to use the noi se filter of rxd3 pin can be selected.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 286 jun 20, 2011 figure 6-23. format of noise filter enable register 1 (nfen1) (2/2) tnfen01 enable/disable using noise filter of ti01/to01/p32/intp5/pclbuz0 pin input signal 0 noise filter off 1 noise filter on tnfen00 enable/disable using noise filter of ti00/ to03/p31/rtcdiv/rtccl/pclbuz1/intp2 pin input signal 0 noise filter off 1 noise filter on figure 6-24. format of noise filt er enable register 2 (nfen2) address: f0061h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 nfen1 0 0 0 0 tnfen13 tnfen12 tnfen11 tnfen10 tnfen13 enable/disable using noise filt er of ti13/to13/p87 pin input signal 0 noise filter off 1 noise filter on tnfen12 enable/disable using noise filt er of ti12/to12/p86 pin input signal 0 noise filter off 1 noise filter on tnfen11 enable/disable using noise filt er of ti11/to11/p85 pin input signal 0 noise filter off 1 noise filter on tnfen10 enable/disable using noise filt er of ti10/to10/p84 pin input signal 0 noise filter off 1 noise filter on
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 287 jun 20, 2011 (15) port mode registers 1, 3, 5, 8 (pm1, pm3, pm5, pm8) these registers set input/output of por ts 1, 3, 5, and 8 in 1-bit units. when using the p30/to00/ti03/rtc1hz/intp1, p 32/to01/ti01/intp5/pclbuz 0, p12/to02/so02/txd2, p31/to03/ti00/rtcdiv/rtccl/pc lbuz1/intp2, p13/to04/so10/ txd1, p16/to05/ti05/intp10, p34/to06/ti06/intp8, p33/to07/ti07/intp3, p 84/to10/ti10, p85/to11/ti 11, p86/to12/ti12, and p87/to13/ti13 pins for timer output, set pm30, pm32, pm12, pm31, pm13, pm16, pm34, pm33, and pm84 to pm87 and the output latches of p30, p32, p12, p 31, p13, p16, p34, p33, and p84 to p87 to 0. when using the p31/ti00/to03/rtcdiv/rtccl/pcl buz1/intp2, p32/ti01/to01/intp5/pclbuz0, p52/ti02/segz (78k0r/lf3: z = 28, 78k0r/lg3: z = 37, 78k0r/lh3: z = 51), p30/ti03/to00/rtc1hz/intp1, p53/ti04/segz (78k0r/lf3: z = 27, 78k0r/lg3: z = 36, 78k0r/lh3: z = 50), p16/ti05/to05/intp10, p34/ti06/to06/intp8, p33/ti07/to07/intp3, p 84/ti10/to10, p85/ti11/to 11, p86/ti12/to12, and p87/ti13/to13 pins for timer input, set pm31, pm32, pm52, pm30, pm53, pm16, pm34 pm33, and pm84 to pm87 to 1. at this time, the output latches of p31, p32, p52, p30, p53, p16, p34, p33, and p84 to p87 may be 0 or 1. pm1, pm3, pm5, and pm8 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation se ts these registers to ffh.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 288 jun 20, 2011 figure 6-25. format of port mode registers 1, 3, 5, 8 (pm1, pm3, pm5, pm8) ? 78k0r/lf3 address: fff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 1 1 pm15 pm14 pm13 pm12 pm11 pm10 address: fff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 1 pm33 pm32 pm31 pm30 address: fff25h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 ? 78k0r/lg3 address: fff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 1 pm16 pm15 pm14 pm13 pm12 pm11 pm10 address: fff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 pm34 pm33 pm32 pm31 pm30 address: fff25h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 ? 78k0r/lh3 address: fff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 address: fff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 pm34 pm33 pm32 pm31 pm30 address: fff25h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 address: fff28h after reset: feh r/w symbol 7 6 5 4 3 2 1 0 pm8 pm87 pm86 pm85 pm84 pm83 pm82 pm81 pm80 pmmn pmn pin i/o mode selection (m = 1, 3, 5, 8; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 289 jun 20, 2011 6.4 channel output (topq pin) control 6.4.1 topq pin output circuit configuration figure 6-26. output circuit configuration interrupt signal of the master channel (inttmpq) tolpq tompq toepq <1> <2> <3> <4> <5> topq write signal topq pin top register set reset/toggle internal bus interrupt signal of the slave channel (inttmpr) controller the following describes the topq pin output circuit. <1> when tompq = 0 (toggle mode), the set value of t he tolp register is ignored and only inttmpr (slave channel timer interrupt) is transmitted to the top register. <2> when tompq = 1 (combination operation mode) , both inttmpq (master channel timer interrupt) and inttmpr (slave channel timer interrupt) are transmitted to the top register. at this time, the tolp register becomes valid and the signals are controlled as follows: when tolpq = 0: forward operation (inttmpq set, inttmpr reset) when tolpq = 1: reverse operation (inttmpq reset, inttmpr set) when inttmpq and inttmpr are simultaneously generat ed, (0% output of pwm), inttmpr (reset signal) takes priority, and inttmpq (set signal) is masked. <3> when toepq = 1, inttmpq (master channel timer in terrupt) and inttmpr (slave channel timer interrupt) are transmitted to the topq register. writing to the top register (topq write signal) becomes invalid. when toepq = 1, the topq pin output never chang es with signals other than interrupt signals. to initialize the topq pin output level, it is nece ssary to set toepq = 0 and to write a value to topq. <4> when toepq = 0, writing to topq bit to the target channel (topq signal) becomes valid. when toepq = 0, neither inttmpq (master channel timer interrupt) nor in ttmpr (slave channel timer interrupt) is transmitted to topq register. <5> the top register can always be read, a nd the topq pin output level can be checked.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 290 jun 20, 2011 remark pq: unit number + channel number (only for channels provided with timer i/o pins) <1> 78k0r/lf3: ? p = 0, q = 0 to 4, 7 (q = 0, 2, 4 for master channel) q < r 7 (where r is a consecutive integer greater than q) <2> 78k0r/lg3: ? p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel) q < r 7 (where r is a consecutive integer greater than q) <3> 78k0r/lh3: ? p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel) q < r 7 (where r is a consecutive integer greater than q) ? p = 1, q = 0 to 3 (q = 0, 2 for master channel) q < r 3 (where r is a consecutive integer greater than q) 6.4.2 topq pin output setting the following figure shows the procedure and status transition of topq out put pin from initial setting to timer operation start. figure 6-27. status transition from ti mer output setting to operation start tcrpq timer alternate-function pin timer output signal toepq topq (counter) undefined value (ffffh after reset) write operation enabled period to topq <1> set the tompq set the tolpq <4> set the port to output mode <2> set the topq <3> set the toepq <5> timer operation start write operation disabled period to topq hi-z <1> the operation mode of timer output is set. ? tompq bit (0: toggle mode, 1: combination operation mode) ? tolpq bit (0: forward output, 1: reverse output) <2> the timer output signal is set to the initial status by setting topq. <3> the timer output operation is enabled by wr iting 1 to toepq (writing to topq is disabled). <4> the port i/o setting is set to output (see 6.3 (15) port mode registers 1, 3, 5, 8 ). <5> the timer operation is enabled (tspq = 1). remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 291 jun 20, 2011 6.4.3 cautions on channel output operation (1) changing values set in registers top, toep,tolp, and tomp during timer operation since the timer operations (operations of tcrpq and td rpq) are independent of the topq output circuit and changing the values set in top, toep, tolp, and tomp does not affect the timer oper ation, the values can be changed during timer operation. to output an expected wave form from the topq pin by timer operation, however, set top, toep, tolp, and tomp to the values stated in the register setting example of each operation. when the values set in toep, tolp, and tomp (except for top) are changed close to the timer interrupt (inttmpq), the waveform output to the topq pin may be different depending on whether the values are changed immediately before or immediately after the time r interrupt (inttmpq) signal generation timing. (2) default level of topq pin and ou tput level after timer operation start the following figure shows the topq pin output level transi tion when writing has been done in the state of toepq = 0 before port output is enabled and toepq = 1 is set after changing the default level. (a) when operation starts with tompq = 0 setting (toggle output) the setting of tolpq is invalid when tompq = 0. when t he timer operation starts after setting the default level, the toggle signal is generated and the ou tput level of topq pin is reversed. figure 6-28. topq pin output status at toggle output (tompq = 0) toepq topq = 0, tolpq = 0 topq = 1, tolpq = 0 topq = 0, tolpq = 1 (same output waveform as tolpq = 0) topq = 1, tolpq = 1 (same output waveform as tolpq = 0) default level, tolpq setting independent of tolpq setting port output is enabled topq pin transition toggle toggle toggle toggle toggle hi-z hi-z hi-z hi-z dependent on topq setting remarks 1. toggle: reverse topq pin output status 2. pq: unit number + channel number (onl y for channels provided with timer i/o pins) 78k0r/lf3: p = 0, pq = 00 to 04, 07 78k0r/lg3: p = 0, pq = 00 to 07 78k0r/lh3: p = 0, 1, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 292 jun 20, 2011 (b) when operation starts with tompq = 1 setti ng (combination operati on mode (pwm output)) when tompq = 1, the active level is determined by tolpq setting. figure 6-29. topq pin output status at pwm output (tompq = 1) toepq topq = 0, tolpq = 0 (active high) topq = 1, tolpq = 0 (active high) topq = 0, tolpq = 1 (active low) topq = 1, tolpq = 1 (active low) default level, tolpq setting dependent on tolpq setting dependent on topq setting no change set reset set reset set hi-z hi-z hi-z hi-z topq pin transition port output is enabled (3) operation of topq pin in combination operation mode (tompq = 1) (a) when tolpq setting has been changed during timer operation when the tolpq setting has been changed during timer oper ation, the setting becomes valid at the generation timing of topq change condition. rewriting tolpq does not change the output level of topq. the following figure shows the operation when the valu e of tolpq has been changed during timer operation (tompq = 1). figure 6-30. operation when tolpq h as been changed during timer operation internal set signal internal reset signal tolpq topq pin set/reset signals are inverted topq does not change remarks 1. set: the output signal of topq pin changes from inactive level to active level. reset: the output signal of topq pin changes from active level to inactive level. 2. pq: unit number + channel number (onl y for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 293 jun 20, 2011 (b) set/reset timing to realize 0%/100% output at pwm output, the topq pin/ topq set timing at master channel timer interrupt (inttmpq) generation is delayed by 1 count clock by the slave channel timer interrupt (inttmqr). if the set condition and reset condition are generated at the same time, a higher priority is given to the latter. figure 6-31 shows the set/reset operat ing statuses where the master/sla ve channels are set as follows. ? master channel: toepq = 1, tompq = 0, tolpq = 0 ? slave channel: toepr = 1, tompr = 1, tolpr = 0 figure 6-31. set/reset ti ming operat ing statuses to_reset (internal signal) to_reset (internal signal) (internal signal) inttmpq topq pin/ topq topr pin/ topr count clock f clk inttmpr to_set delays to_reset by 1 count clock with slave channel toggle set reset master channel slave channel remarks 1. to_reset: topq pin reset/toggle signal to_set: topq pin set signal 2. pq: unit number + channel number (onl y for channels provided with timer i/o pins) <1> 78k0r/lf3: ? p = 0, q = 0 to 4, 7 (q = 0, 2, 4 for master channel) q < r 7 (where r is a consecutive integer greater than q) <2> 78k0r/lg3: ? p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel) q < r 7 (where r is a consecutive integer greater than q) <3> 78k0r/lh3: ? p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel) q < r 7 (where r is a consecutive integer greater than q) ? p = 1, q = 0 to 3 (q = 0, 2 for master channel) q < r 3 (where r is a consecutive integer greater than q)
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 294 jun 20, 2011 6.4.4 collective manipulation of topq bits in the top register, the setting bits for all the channels are lo cated in one register in the same way as the tsp register (channel start trigger). therefor e, topq of all the channels can be manipulated collectively. only specific bits can also be manipulated by setting the corresponding toe pq = 0 to a target topq (channel output). figure 6-32. example of to0q bits collective manipulation before writing to0 0 0 0 0 0 0 0 0 to07 0 to06 0 to05 1 to04 0 to03 0 to02 0 to01 1 to00 0 toe0 0 0 0 0 0 0 0 0 toe07 0 toe06 0 toe05 1 toe04 0 toe03 1 toe02 1 toe01 1 toe00 1 data to be written 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 after writing to0 0 0 0 0 0 0 0 0 to07 1 to06 1 to05 1 to04 0 to03 0 to02 0 to01 1 to00 0 writing is done only to topq bits with toepq = 0, and writing to topq bits with toepq = 1 is ignored. topq (channel output) to which toepq = 1 is set is not affected by the write operat ion. even if the write operation is done to topq, it is ignored and the output change by timer operation is normally done. figure 6-33. topq pin statuses by co llective manipulation of topq bits to07 to06 to05 to04 to03 to02 to01 to00 two or more topq output can be changed simultaneously output does not change when value does not change before writing writing to top bit is ignored when toepq = 1 writing to top register (caution and remark are given on the next page.) o o o
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 295 jun 20, 2011 caution when toepq = 1, even if the output by ti mer interrupt of each timer (inttmpq) contends with writing to topq, output is normally done to topq pin. remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13 6.4.5 timer interrupt and topq pin output at operation start in the interval timer mode or capture mode, the mdmn0 bit in the tmrmn register sets whether or not to generate a timer interrupt at count start. when mdmn0 is set to 1, the count operation start timing ca n be known by the timer interrupt (inttmmn) generation. in the other modes, neither timer interrupt at c ount operation start nor to pq output is controlled. figures 6-34 and 6-35 show operation examples when the interval timer mode (toemn = 1, tommn = 0) is set. figure 6-34. when mdmn0 is set to 1 tcrmn temn topq inttmmn count operation start when mdmn0 is set to 1, a timer interrupt (inttmmn) is output at count operation st art, and topq performs a toggle operation. figure 6-35. when mdmn0 is set to 0 tcrmn temn topq inttmmn count operation start when mdmn0 is set to 0, a timer interrupt (inttmmn) is not output at count operatio n start, and topq does not change either. after counting one cycle, inttmmn is output and topq performs a toggle operation. remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07 78k0r/lg3: mn = 00 to 07, 10 to 13, pq = 00 to 07 78k0r/lh3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 296 jun 20, 2011 6.5 channel input control 6.5.1 edge detection circuit (1) edge detection basic operation timing edge detection circuit sampling is done in accordance with the operation clock (mck). figure 6-36. edge detect ion basic operation timing synchronized (noise filter) internal tipq signal f clk rising edge detection internal trigger falling edge detection internal trigger operation clock (mck) remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 297 jun 20, 2011 6.6 basic function of timer array unit 6.6.1 overview of single-operation f unction and combination operation function the timer array unit consists of several channels and has a single-operation function t hat allows each channel to operate independently, and a combination operation function that uses two or more channels in combination. the single-operation function can be used for any channel, regardless of the operation mode of the other channels. the combination operation function is realized by combin ing a master channel (referenc e timer that mainly counts periods) and a slave channel (timer that operates in acco rdance with the master channel), and several rules must be observed when using this function. 6.6.2 basic rules of comb ination operation function the basic rules of using the combinat ion operation function are as follows. (1) only an even channel (channel 0, 2, 4, etc.) can be set as a master channel. (2) any channel, except channel 0, can be set as a slave channel. (3) the slave channel must be lower than the master channel. example: if channel 2 of tau0 is set as a master channel, channel 3 or those that follo w (channels 3, 4, etc. 5) can be set as a slave channel. if channel 2 of tau1 is set as a master channel , channel 3 (because tau1 is provided only with channels up to channel 3) can be set as a slave channel. (4) two or more slave channels can be set for one master channel. (5) when two or more master channels are to be used, sl ave channels with a master c hannel between them may not be set. example: if channels 0 and 4 of tau0 are set as master channels, channels 1 to 3 can be set as the slave channels of master channel 0. channels 5 to 7 cann ot be set as the slave channels of master channel 0. (6) the operating clock for a slave channel in combinatio n with a master channel must be the same as that of the master channel. the cks bit (bit 15 of the tmrmn register) of the slave channel that operates in combination with the master channel must be the same va lue as that of t he master channel. (7) a master channel can transmit inttmmn (interrupt), st art software trigger, and count clock to the lower channels. (8) a slave channel can use the inttmmn (interrupt), start software trigger, and count clock of the master channel, but it cannot transmit its own inttmmn (interrupt), start so ftware trigger, and count clock to the lower channel. (9) a master channel cannot use the inttmmn (interrupt), start software tri gger, and count clock from the higher master channel. (10) to simultaneously start channels that operate in combi nation, the tsmn bit of the ch annels in combination must be set at the same time. (11) during a counting operation, the ts mn bit of all channels that operate in combination or only the master channel can be set. tsmn of only a slave channel cannot be set. (12) to stop the channels in combination simultaneously, the ttmn bit of the channels in combination must be set at the same time. remark mn: unit number + channel number mn = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 298 jun 20, 2011 channel 1: slave channel 0: master channel group 1 (combination operation function) * the operating clock of channel group 1 may be different from that of channel group 2. channel 2: slave channel 3: single-operation function channel 4: master channel 5: slave channel 6: single-operation function channel 7: single-operation function ck00 ck01 tau0 * a channel that singly operates may be between channel group 1 and channel group 2. channel group 2 (combination operation function) 6.6.3 applicable range of basic ru les of combination operation function the rules of the combination operation function are applied in a channel group (a master channel and slave channels forming one combination operation function). if two or more channel groups that do not operate in combi nation are specified, the basic rules of the combination operation function in 6.6.2 basic rules of comb ination operation function do not apply to the channel groups. example
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 299 jun 20, 2011 6.7 operation of timer array unit as independent channel 6.7.1 operation as interval timer/square wave output (1) interval timer the timer array unit can be used as a reference timer that generates inttmmn (timer interrupt) at fixed intervals. the interrupt generation period can be calculated by the following expression. generation period of inttmmn (timer interrupt) = period of count clock (set value of tdrmn + 1) (2) operation as square wave output topq performs a toggle operation as soon as inttmpq has been generated, and outp uts a square wave with a duty factor of 50%. the period and frequency for outputting a square wave from topq can be calculated by the following expressions. ? period of square wave output from topq = period of count clock (set value of tdrpq + 1) 2 ? frequency of square wave output from topq = fr equency of count clock/{(set value of tdrpq + 1) 2} the valid edge of tipq pin input signal, the valid edge of f sub /2, the valid edge of f sub/ 4, or the valid edge of intrtc1 can be selected as the count clock, in addition to ckm0 and ckm1. consequently, the interval timer can be operated, regardless of the f clk frequency (main system clock, subsystem clock). when changing the clock selected as f clk (changing the value of the system cl ock control register (ckc)), stop the timer array units 0 and 1 (taus0, taus1) (tt0 = 00ffh, tt1 = 000fh) first. only in the case of sdiv=0, ccsmn=1 and tismn=1, contin uously use of taum is allowed, even when changing cpu clock. however, the following limitation is existing. ? when changing cpu clock, source clock decrease/increase occurs as follows. main clock subsystem clock (css = 0 1): ? 1 clock subsystem clock main clock (css = 1 0): +1 clock tcrmn operates as a down counter in the interval timer mode. tcrmn loads the value of tdrmn at the fi rst count clock after the channel start trigger bit (tsmn) is set to 1. if mdmn0 of tmrmn = 0 at this time, inttmmn is not output and topq is not toggled. if mdmn0 of tmrmn = 1, inttmmn is output and topq is toggled. after that, tcrmn count down in syn chronization with the count clock. when tcrmn = 0000h, inttmmn is output and topq is toggled at the next count clock. at the same time, tcrmn loads the value of tdrmn again. a fter that, the same operation is repeated. tdrmn can be rewritten at any time. the new valu e of tdrmn becomes valid from the next period.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 300 jun 20, 2011 figure 6-37. block diagram of operation as interval timer/square wave output timer counter (tcrmn) topq pin interrupt signal (inttmmn) data register (tdrmn) interrupt controller output controller clock selection trigger selection operation clock ckm0 ckm1 tsmn clock selection edge selection timer input selection tipq pin input f sub /2 f sub /4 intrtci note note channels 0 and 4 of timer array unit 0 only remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07 78k0r/lg3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07 78k0r/lh3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13 figure 6-38. example of basic timing of operati on as interval timer/square wave output (mdmn0 = 1) tsmn temn tdrmn tcrmn topq inttmmn a a+1 b 0000h a+1 a+1 b+1 b+1 b+1 remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07 78k0r/lg3: mn = 00 to 07, 10 to 13, pq = 00 to 07 78k0r/lh3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 301 jun 20, 2011 figure 6-39. example of set contents of registers during operation as interval time r/square wave output (1/3) (1) when ckm0 or ckm1 is selected as count clock (a) timer mode register mn (tmrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrmn cksmn 1/0 0 0 ccsmn 0 mas termn 0 stsmn2 0 stsmn1 0 stsmn0 0 cismn1 0 cismn0 0 0 0 mdmn3 0 mdmn2 0 mdmn1 0 mdmn0 1/0 operation mode of channel n 000b: interval timer setting of operation when counting is started 0: neither generates inttmmn nor inverts timer output when counting is started. 1: generates inttmmn and inverts timer output when counting is started. selection of edge of timer input 00b: sets 00b because these are not used. start trigger selection 000b: selects only software start. slave/master selection 0: cleared to 0 when independent function is selected. count clock selection 0: selects operation clock. operation clock selection 0: selects ckm0 as operation clock of channel n. 1: selects ckm1 as operation clock of channel n. (b) timer output register p (top) bit q top topq 1/0 0: outputs 0 from topq. 1: outputs 1 from topq. (c) timer output enable register p (toep) bit q toep toepq 1/0 0: stops the topq output operation by counting operation. 1: enables the topq output operation by counting operation. (d) timer output level register p (tolp) bit q tolp tolpq 0 0: cleared to 0 when tompq = 0 (toggle mode) (e) timer output mode register p (tomp) bit q tomp tompq 0 0: sets toggle mode. remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07 78k0r/lg3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07 78k0r/lh3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 302 jun 20, 2011 figure 6-39. example of set contents of registers during operation as interval time r/square wave output (2/3) (2) when the timer input (tipq pin input, f sub /4, f sub /2 or intrtci) is selected as count clock note (1/2) note the timer input is selected by using tispq bit, sdiv bit, and rtcispq bit. for details, refer to figure 6-17 format of timer input select re gisters 0, 1 (tis0, tis1). (a) timer mode register mn (tmrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrmn cksmn 1/0 0 0 ccsmn 1 mas termn 0 stsmn2 0 stsmn1 0 stsmn0 0 cismn1 1/0 cismn0 1/0 0 0 mdmn3 0 mdmn2 0 mdmn1 0 mdmn0 1/0 operation mode of channel n 000b: interval timer setting of operation when counting is started 0: neither generates inttmmn nor inverts timer output when counting is started. 1: generates inttmmn and inverts timer output when counting is started. selection of edge of timer input 00b: detects falling edge. 01b: detects rising edge. 10b: detects both edges. 11b: setting prohibited start trigger selection 000b: selects only software start. slave/master selection 0: cleared to 0 when independent function is selected. count clock selection 1: selects timer input valid edge. operation clock selection 0: selects ckm0 as operation clock of channel n. 1: selects ckm1 as operation clock of channel n. f clk (no division) is selected as select ed operation clock by tpsm register. (b) timer clock select register m (tpsm) bits 7 to 4, 3 to 0 tpsm prsmk3 to prsmk0 0000 0000b: selects f clk (no division) as operation clock se lected by cksmn of tmrmn register. k = 0 (bits 0 to 3) when ckm0 is selected and k = 1 (bits 4 to 7) when ckm1 is selected (c) timer output register p (top) bit q top topq 1/0 0: outputs 0 from topq. 1: outputs 1 from topq. remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07 78k0r/lg3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07 78k0r/lh3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 303 jun 20, 2011 figure 6-39. example of set contents of registers during operation as interval time r/square wave output (3/3) (2) when the timer input (tipq pin input, f sub /4, f sub /2 or intrtci) is selec ted as count clock (2/2) (e) timer output enable register p (toep) bit q toep toepq 1/0 0: stops the topq output operation by counting operation. 1: enables the topq output operation by counting operation. (f) timer output level register p (tolp) bit q tolp tolpq 0 0: cleared to 0 when tompq = 0 (toggle mode) (g) timer output mode register p (tomp) bit q tomp tompq 0 0: sets toggle mode. remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07 78k0r/lg3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07 78k0r/lh3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 304 jun 20, 2011 figure 6-40. operation procedure of interv al timer/square wave output function (1/2) software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en or tau1en bits of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tpsm register. determines clock frequencies of ckm0 and ckm1. sets the tmrmn register (determines operation mode of channel). if timer input is selected for the count clock, set the timer input (tipq pin input, f sub /4, f sub /2, or intrtci) by using the tispq, sdiv, and rtcispq bits. sets interval (period) value to the tdrmn register. channel stops operating. (clock is supplied and some power is consumed.) channel default setting to use the topq output clears the tompq bit of the tomm register to 0 (toggle mode). clears the tolpq bit to 0. sets the topq bit and determines default level of the topq output. sets toepq to 1 and enables operation of topq. clears the port register and port mode register to 0. the tomn pin goes into hi-z output state. the topq default setting level is output when the port mode register is in the output mode and the port register is 0. topq does not change because channel stops operating. the topq pin outputs the topq set level. operation start sets toepq to 1 (only when operation is resumed). sets the tsmn bit to 1. the tsmn bit automatically returns to 0 because it is a trigger bit. temn = 1, and count operation starts. value of tdrmn is loaded to tcrmn at the count clock input. inttmmn is generated and topq performs toggle operation if the mdmn0 bit of the tmrmn register is 1. during operation set values of tmrmn, tomp, and tolp registers cannot be changed. set value of the tdrmn register can be changed. the tcrmn register can always be read. the tsrmn register is not used. set values of the top and toep registers can be changed. counter (tcrmn) counts down. when count value reaches 0000h, the value of tdrmn is loaded to tcrmn again and the count operation is continued. by detecting tcrmn = 0000h, inttmmn is generated and tomn performs toggle operation. after that, the above operation is repeated. the ttmn bit is set to 1. the ttmn bit automatically returns to 0 because it is a trigger bit. temn = 0, and count operation stops. tcrmn holds count value and stops. the topq output is not initialized but holds current status. operation stop toepq is cleared to 0 and value is set to top register. the topq pin outputs the topq set level. remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07 78k0r/lg3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07 78k0r/lh3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13 operation is resumed.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 305 jun 20, 2011 figure 6-40. operation procedure of interv al timer/square wave output function (2/2) software operation hardware status tau stop to hold the topq pin output level clears topq bit to 0 after the value to be held is set to the port register. when holding the topq pin output level is not necessary switches the port mode register to input mode. the topq pin output level is held by port function. the topq pin output level goes into hi-z output state. the tau0en or tau1en bits of the per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the topq bit is cleared to 0 and the topq pin is set to port mode.) remark mn: unit number + channel number, pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07 78k0r/lg3: mn = 00 to 07, 10 to 13, pq = 00 to 07 78k0r/lh3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 306 jun 20, 2011 6.7.2 operation as external event counter the timer array unit can be used as an external event count er that counts the number of times the valid input edge (external event) is detected in the tipq pin. when a specified count value is r eached, the event counter generates an interrupt. the specified number of counts ca n be calculated by the following expression. specified number of counts = set value of tdrpq + 1 tcrpq operates as a down counter in the event counter mode. when the channel start trigger bit (tspq) is set to 1, tcrpq loads the value of tdrpq. tcrpq counts down each time the valid input edge of the tipq pin has been detected. when tcrpq = 0000h, tcrpq loads the value of tdrpq again, and outputs inttmpq. after that, the above operation is repeated. topq must not be used because its waveform depends on the external event and irregular. tdrpq can be rewritten at any time. the new value of tdrpq becomes valid during the next count period. figure 6-41. block diagram of oper ation as external event counter timer counter (tcrpq) edge detection interrupt signal (inttmpq) tipq pin data register (tdrpq) interrupt controller clock selection trigger selection tspq remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 307 jun 20, 2011 figure 6-42. example of basic timing of operation as external event counter tspq tepq tipq tdrpq tcrpq 0003h 0002h 0 0000h 1 3 0 1 2 0 1 2 1 2 3 2 inttmpq 4 events 4 events 3 events remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 308 jun 20, 2011 figure 6-43. example of set contents of registers in external event counter mode (a) timer mode register pq (tmrpq) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrpq ckspq 1/0 0 0 ccspq 1 mas terpq 0 stspq2 0 stspq1 0 stspq0 0 cispq1 1/0 cispq0 1/0 0 0 mdpq3 0 mdpq2 1 mdpq1 1 mdpq0 0 operation mode of channel q 011b: event count mode setting of operation when counting is started 0: neither generates inttmpq nor inverts timer output when counting is started. selection of tipq pin input edge 00b: detects falling edge. 01b: detects rising edge. 10b: detects both edges. 11b: setting prohibited start trigger selection 000b: selects only software start. slave/master selection 0: cleared to 0 when independent function is selected. count clock selection 1: selects the tipq pin input valid edge. operation clock selection 0: selects ckp0 as operation clock of channel q. 1: selects ckp1 as operation clock of channel q. (b) timer output register p (top) bit q top topq 0 0: outputs 0 from topq. (c) timer output enable register p (toep) bit q toep toepq 0 0: stops the topq output operation by counting operation. (d) timer output level register p (tolp) bit q tolp tolpq 0 0: cleared to 0 when tompq = 0 (toggle mode). (e) timer output mode register p (tomp) bit q tomp tompq 0 0: sets toggle mode. remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: p = 0, pq = 00 to 04, 07 78k0r/lg3: p = 0, pq = 00 to 07 78k0r/lh3: p = 0, 1, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 309 jun 20, 2011 figure 6-44. operation procedure when ex ternal event counter function is used software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en or tau1en bits of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tpsp register. determines clock frequencies of ckp0 and ckp1. channel default setting sets the tmrpq register (determines operation mode of channel). sets number of counts to the tdrpq register. clears the toepq bit of the toep register to 0. channel stops operating. (clock is supplied and some power is consumed.) operation start sets the tspq bit to 1. the tspq bit automatically returns to 0 because it is a trigger bit. tepq = 1, and count operation starts. value of tdrpq is loaded to tcrpq and detection of the tipq pin input edge is awaited. during operation set value of the tdrpq register can be changed. the tcrpq register can always be read. the tsrpq register is not used. set values of tmrpq, tomp, tolp, top, and toep registers cannot be changed. counter (tcrpq) counts down each time input edge of the tipq pin has been detected. when count value reaches 0000h, the value of tdrpq is loaded to tcrpq again, and the count operation is continued. by detecting tcrpq = 0000h, the inttmpq output is generated. after that, the above operation is repeated. operation stop the ttpq bit is set to 1. the ttpq bit automatically returns to 0 because it is a trigger bit. tepq = 0, and count operation stops. tcrpq holds count value and stops. tau stop the tau0en or tau1en bits of the per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: p = 0, pq = 00 to 04, 07 78k0r/lg3: p = 0, pq = 00 to 07 78k0r/lh3: p = 0, 1, pq = 00 to 07, 10 to 13 operation is resumed.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 310 jun 20, 2011 6.7.3 operation as frequency divider the timer array unit can be used as a frequency divider that di vides a clock input to the tipq pin and outputs the result from topq. the divided clock frequency output from topq c an be calculated by the following expression. ? when rising edge/falling edge is selected: divided clock frequency = input clock frequency/{(set value of tdrpq + 1) 2} ? when both edges are selected: divided clock frequency ? input clock frequency/(set value of tdrpq + 1) tcrpq operates as a down counter in the interval timer mode. after the channel start trigger bit (tspq) is set to 1, tc rpq loads the value of tdrpq when the tipq valid edge is detected. if mdpq0 of tmrpq = 0 at this time, inttmpq is not output and topq is not toggled. if mdpq0 of tmrpq = 1, inttmpq is output and topq is toggled. after that, tcrpq counts down at the valid edge of tipq. when tcrpq = 0000h, it toggles topq. at the same time, tcrpq loads the value of tdrpq again, and continues counting. if detection of both the edges of tipq is selected, the duty fact or error of the input clock affects the divided clock period of the topq output. the period of the topq output clock includes a samp ling error of one period of the operation clock. clock period of topq output = ideal topq output clock period operation clock period (error) tdrpq can be rewritten at any time. the new value of tdrpq becomes valid during the next count period. figure 6-45. block diagram of operation as frequency divider timer counter (tcrpq) edge detection tipq pin data register (tdrpq) clock selection trigger selection tspq topq pin output controller remark pq: unit number + channel number (only for channels provided with timer i/o pins) pq = 00, 02 to 04
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 311 jun 20, 2011 figure 6-46. example of basic timing of operation as frequency divider (mdpq0 = 1) tspq tepq tipq tdrpq tcrpq topq inttmpq 0002h divided by 6 0001h 0 0000h 1 2 0 1 2 0 1 0 1 0 1 0 1 0 1 2 divided by 4 remark pq: unit number + channel number (only for channels provided with timer i/o pins) pq = 00, 02 to 04
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 312 jun 20, 2011 figure 6-47. example of set contents of registers when frequency divider is used (a) timer mode register pq (tmrpq) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrpq ckspq 1/0 0 0 ccspq 1 mas terpq 0 stspq2 0 stspq1 0 stspq0 0 cispq1 1/0 cispq0 1/0 0 0 mdpq3 0 mdpq2 0 mdpq1 0 mdpq0 1/0 operation mode of channel q 000b: interval timer setting of operation when counting is started 0: neither generates inttmpq nor inverts timer output when counting is started. 1: generates inttmpq and inverts timer output when counting is started. selection of tipq pin input edge 00b: detects falling edge. 01b: detects rising edge. 10b: detects both edges. 11b: setting prohibited start trigger selection 000b: selects only software start. slave/master selection 0: cleared to 0 when independent function is selected. count clock selection 1: selects the tipq pin input valid edge. operation clock selection 0: selects ckp0 as operation clock of channel q. 1: selects ckp1 as operation clock of channel q. (b) timer output register p (top) bit q top topq 1/0 0: outputs 0 from topq. 1: outputs 1 from topq. (c) timer output enable register p (toep) bit q toep toepq 1/0 0: stops the topq output operation by counting operation. 1: enables the topq output operation by counting operation. (d) timer output level register p (tolp) bit q tolp tolpq 0 0: cleared to 0 when tompq = 0 (toggle mode) (e) timer output mode register p (tomp) bit q tomp tompq 0 0: sets toggle mode. remark pq: unit number + channel number (only for channels provided with timer i/o pins) pq = 00, 02 to 04
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 313 jun 20, 2011 figure 6-48. operation procedure when fr equency divider function is used (1/2) software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en or tau1en bits of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tpsp register. determines clock frequencies of ckp0 and ckp1. sets the tmrpq register (determines operation mode of channel). sets interval (period) value to the tdrpq register. channel stops operating. (clock is supplied and some power is consumed.) channel default setting clears the tompq bit of the tomp register to 0 (toggle mode). clears the tolpq bit to 0. sets the topq bit and determines default level of the topq output. sets toepq to 1 and enables operation of topq. clears the port register and port mode register to 0. the topq pin goes into hi-z output state. the topq default setting level is output when the port mode register is in output mode and the port register is 0. topq does not change because channel stops operating. the topq pin outputs the topq set level. operation start sets the toepq to 1 (only when operation is resumed). sets the tspq bit to 1. the tspq bit automatically returns to 0 because it is a trigger bit. tepq = 1, and count operation starts. value of tdrpq is loaded to tcrpq at the count clock input. inttmpq is generated and topq performs toggle operation if the mdpq0 bit of the tmrpq register is 1. during operation set value of the tdrpq register can be changed. the tcrpq register can always be read. the tsrpq register is not used. set values of top and toep registers can be changed. set values of tmrpq, tomp, and tolp registers cannot be changed. counter (tcrpq) counts down. when count value reaches 0000h, the value of tdrpq is loaded to tcrpq again, and the count operation is continued. by detecting tcrpq = 0000h, inttmpq is generated and topq performs toggle operation. after that, the above operation is repeated. the ttpq bit is set to 1. the ttpq bit automatically returns to 0 because it is a trigger bit. tepq = 0, and count operation stops. tcrpq holds count value and stops. the topq output is not initialized but holds current status. operation stop toepq is cleared to 0 and value is set to the top register. the topq pin outputs the topq set level. remark pq: unit number + channel number (only for channels provided with timer i/o pins) pq = 00, 02 to 04 operation is resumed.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 314 jun 20, 2011 figure 6-48. operation procedure when fr equency divider function is used (2/2) software operation hardware status to hold the topq pin output level clears topq bit to 0 after the value to be held is set to the port register. when holding the topq pin output level is not necessary switches the port mode register to input mode. the topq pin output level is held by port function. the topq pin output level goes into hi-z output state. tau stop the tau0en or tau1en bits of the per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the topq bit is cleared to 0 and the topq pin is set to port mode). remark pq: unit number + channel number (only for channels provided with timer i/o pins) pq = 00, 02 to 04
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 315 jun 20, 2011 6.7.4 operation as input pu lse interval measurement the count value can be captured at the ti pq valid edge and the interval of t he pulse input to tipq can be measured. the pulse interval can be calculated by the following expression. tipq input pulse interval = period of count clock ((10000h tsrpq: ovf) + (capture value of tdrpq + 1)) caution the tipq pin input is sampled using th e operating clock selected with the ckspq bit of the tmrpq register, so an erro r equal to the number of operating clocks occurs. tcrpq operates as an up counter in the capture mode. when the channel start trigger (tspq) is set to 1, tcrpq co unts up from 0000h in synchronization with the count clock. when the tipq pin input valid edge is detec ted, the count value is transferred (c aptured) to tdrpq and, at the same time, the counter (tcrpq) is cleared to 0000h, and the inttm pq is output. if the counter overflows at this time, the ovfpq bit of the tsrpq register is set to 1. if the counter does not overflow, t he ovfpq bit is cleared. after that, the above operation is repeated. as soon as the count value has been captured to the tdrpq register, the ovfpq bit of the tsrpq register is updated depending on whether the counter overflow s during the measurement period. ther efore, the overflow status of the captured value can be checked. if the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the ovfpq bit of the tsrpq register is set to 1. howe ver, the ovfpq bit is configured as a cumulative flag, the correct interval value cannot be measured if an overflow occurs more than once. set stspq2 to stspq0 of the tmrpq register to 001b to us e the valid edges of tipq as a start trigger and a capture trigger. when tepq = 1, instead of the tipq pin input, a software operation (tspq = 1) can be used as a capture trigger. figure 6-49. block diagram of operatio n as input pulse interval measurement timer counter (tcrpq) interrupt signal (inttmpq) data register (tdrpq) interrupt controller clock selection trigger selection operation clock ckp0 ckp1 edge detection tipq pin tspq remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: p = 0, pq = 00 to 04, 07 78k0r/lg3: p = 0, pq = 00 to 07 78k0r/lh3: p = 0, 1, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 316 jun 20, 2011 figure 6-50. example of basic timing of operati on as input pulse interval measurement (mdpq0 = 0) tspq tepq tipq tdrpq tcrpq 0000h c b 0000h a c d inttmpq ffffh b a d ovfpq remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 317 jun 20, 2011 figure 6-51. example of set contents of registers to measure input pulse interval (a) timer mode register pq (tmrpq) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrpq ckspq 1/0 0 0 ccspq 0 mas terpq 0 stspq2 0 stspq1 0 stspq0 1 cispq1 1/0 cispq0 1/0 0 0 mdpq3 0 mdpq2 1 mdpq1 0 mdpq0 1/0 operation mode of channel q 010b: ca p ture mode setting of operation when counting is started 0: does not generate inttmpq when counting is started. 1: generates inttmpq when counting is started. selection of tipq pin input edge 00b: detects falling edge. 01b: detects rising edge. 10b: detects both edges. 11b: setting prohibited capture trigger selection 001b: selects the tipq pin input valid edge. slave/master selection 0: cleared to 0 when independent function is selected. count clock selection 0: selects operation clock. operation clock selection 0: selects ckp0 as operation clock of channel q. 1: selects ckp1 as operation clock of channel q. (b) timer output register p (top) bit q top topq 0 0: outputs 0 from topq. (c) timer output enable register p (toep) bit q toep toepq 0 0: stops topq output operation by counting operation. (d) timer output level register p (tolp) bit q tolp tolpq 0 0: cleared to 0 when tompq = 0 (toggle mode). (e) timer output mode register p (tomp) bit q tomp tompq 0 0: sets toggle mode. remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: p = 0, pq = 00 to 04, 07 78k0r/lg3: p = 0, pq = 00 to 07 78k0r/lh3: p = 0, 1, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 318 jun 20, 2011 figure 6-52. operation procedure when input pulse interval measurement function is used software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en or tau1en bits of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tpsp register. determines clock frequencies of ckp0 and ckp1. channel default setting sets the tmrpq register (determines operation mode of channel). channel stops operating. (clock is supplied and some power is consumed.) operation start sets tspq bit to 1. the tspq bit automatically returns to 0 because it is a trigger bit. tepq = 1, and count operation starts. tcrpq is cleared to 0000h at the count clock input. when the mdpq0 bit of the tmrpq register is 1, inttmpq is generated. during operation set values of only the cispq1 and cispq0 bits of the tmrpq register can be changed. the tdrpq register can always be read. the tcrpq register can always be read. the tsrpq register can always be read. set values of tomp, tolp, top, and toep registers cannot be changed. counter (tcrpq) counts up from 0000h. when the tipq pin input valid edge is detected, the count value is transferred (captured) to tdrpq. at the same time, tcrpq is cleared to 0000h, and the inttmpq signal is generated. if an overflow occurs at this time, the ovfpq bit of the tsrpq register is set; if an overflow does not occur, the ovfpq bit is cleared. after that, the above operation is repeated. operation stop the ttpq bit is set to 1. the ttpq bit automatically returns to 0 because it is a trigger bit. tepq = 0, and count operation stops. tcrpq holds count value and stops. the ovfpq bit of the tsrpq register is also held. tau stop the tau0en or tau1en bits of the per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: p = 0, pq = 00 to 04, 07 78k0r/lg3: p = 0, pq = 00 to 07 78k0r/lh3: p = 0, 1, pq = 00 to 07, 10 to 13 operation is resumed.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 319 jun 20, 2011 6.7.5 operation as input signal hi gh-/low-level width measurement by starting counting at one edge of ti pq and capturing the number of counts at another edge, the signal width (high- level width/low-level width) of tipq can be measured. t he signal width of tipq can be calculated by the following expression. signal width of tipq input = period of count clock ((10000h tsrpq: ovf) + (capture value of tdrpq + 1)) caution the tipq pin input is sampled using th e operating clock selected with the ckspq bit of the tmrpq register, so an erro r equal to the number of operating clocks occurs. tcrpq operates as an up counter in the capture & one-count mode. when the channel start trigger (tspq) is set to 1, tepq is set to 1 and the tipq pin start edge detection wait status is set. when the tipq start valid edge (rising ed ge of tipq when the high-level width is to be measured) is detected, the counter counts up in synchronization wit h the count clock. when the valid capt ure edge (falling edge of tipq when the high-level width is to be measured) is detected later, the c ount value is transferred to tdrpq and, at the same time, inttmpq is output. if the counter overflows at this time, the ov fpq bit of the tsrpq register is set to 1. if the counter does not overflow, the ovfpq bit is cleared. tcrpq stops at the value ?value transferred to tdrpq + 1?, and the tipq pin start edge detection wait status is set. after that, the above operation is repeated. as soon as the count value has been captured to the tdrpq register, the ovfpq bit of the tsrpq register is updated depending on whether the counter overflow s during the measurement period. ther efore, the overflow status of the captured value can be checked. if the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the ovfpq bit of the tsrpq register is set to 1. howe ver, the ovfpq bit is configured as an int egral flag, and the correct interval value cannot be measured if an overflow occurs more than once. whether the high-level width or low-level width of the tipq pin is to be measured can be selected by using the cispq1 and cispq0 bits of the tmrpq register. because this function is used to meas ure the signal width of the tipq pin input, tspq cannot be set to 1 while tepq is 1. cispq1, cispq0 of tmrpq = 10b: low-level width is measured. cispq1, cispq0 of tmrpq = 11b: high-level width is measured. remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 320 jun 20, 2011 figure 6-53. block diagram of operation as in put signal high-/low-le vel width measurement timer counter (tcrpq) interrupt signal (inttmpq) data register (tdrpq) interrupt controller clock selection trigger selection operation clock ckp0 ckp1 edge detection tipq pin remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: p = 0, pq = 00 to 04, 07 78k0r/lg3: p = 0, pq = 00 to 07 78k0r/lh3: p = 0, 1, pq = 00 to 07, 10 to 13 figure 6-54. example of basic timing of operati on as input signal high-/low-level width measurement tspq tepq tipq tdrpq tcrpq b 0000h a c inttmpq ffffh b a c ovfpq 0000h remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: pq = 00 to 04, 07 78k0r/lg3: pq = 00 to 07 78k0r/lh3: pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 321 jun 20, 2011 figure 6-55. example of set contents of regist ers to measure input signa l high-/low-level width (a) timer mode register pq (tmrpq) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrpq ckspq 1/0 0 0 ccspq 0 mas terpq 0 stspq2 0 stspq1 1 stspq0 0 cispq1 1 cispq0 1/0 0 0 mdpq3 1 mdpq2 1 mdpq1 0 mdpq0 0 operation mode of channel q 110b: capture & one-count setting of operation when counting is started 0: does not generate inttmpq when counting is started. selection of tipq pin input edge 10b: both edges (to measure low-level width) 11b: both edges (to measure high-level width) start trigger selection 010b: selects the tipq pin input valid edge. slave/master selection 0: cleared to 0 when independent function is selected. count clock selection 0: selects operation clock. operation clock selection 0: selects ckp0 as operation clock of channel q. 1: selects ckp1 as operation clock of channel q. (b) timer output register p (top) bit q top topq 0 0: outputs 0 from topq. (c) timer output enable register p (toep) bit q toep toepq 0 0: stops the topq output operation by counting operation. (d) timer output level register p (tolp) bit q tolp tolpq 0 0: cleared to 0 when tompq = 0 (toggle mode). (e) timer output mode register p (tomp) bit q tomp tompq 0 0: sets toggle mode. remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: p = 0, pq = 00 to 04, 07 78k0r/lg3: p = 0, pq = 00 to 07 78k0r/lh3: p = 0, 1, pq = 00 to 07, 10 to 13
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 322 jun 20, 2011 figure 6-56. operation procedure when input signal high-/low-level width measu rement function is used software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en or tau1en bits of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tpsp register. determines clock frequencies of ckp0 and ckp1. channel default setting sets the tmrpq register (determines operation mode of channel). clears toepq to 0 and stops operation of topq. channel stops operating. (clock is supplied and some power is consumed.) sets the tspq bit to 1. the tspq bit automatically returns to 0 because it is a trigger bit. tepq = 1, and the tipq pin start edge detection wait status is set. operation start detects tipq pin input count start valid edge. clears tcrpq to 0000h and starts counting up. during operation set value of the tdrpq register can be changed. the tcrpq register can always be read. the tsrpq register is not used. set values of tmrpq, tomp, tolp, top, and toep registers cannot be changed. when the tipq pin start edge is detected, the counter (tcrpq) counts up from 0000h. if a capture edge of the tipq pin is detected, the count value is transferred to tdrpq and inttmpq is generated. if an overflow occurs at this time, the ovfpq bit of the tsrpq register is set; if an overflow does not occur, the ovfpq bit is cleared. tcrpq stops the count operation until the next tipq pin start edge is detected. operation stop the ttpq bit is set to 1. ttpq bit automatically returns to 0 because it is a trigger bit. tepq = 0, and count operation stops. tcrpq holds count value and stops. the ovfpq bit of the tsrpq register is also held. tau stop the tau0en or tau1en bits of per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. remark pq: unit number + channel number (only for channels provided with timer i/o pins) 78k0r/lf3: p = 0, pq = 00 to 04, 07 78k0r/lg3: p = 0, pq = 00 to 07 78k0r/lh3: p = 0, 1, pq = 00 to 07, 10 to 13 ope r ation is resumed.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 323 jun 20, 2011 6.8 operation of plural channels of timer array unit 6.8.1 operation as pwm function two channels can be used as a set to generate a pulse of any period and duty factor. the period and duty factor of the output pulse can be calculated by the following expressions. pulse period = {set value of tdrmn (master) + 1} count clock period duty factor [%] = {set value of tdrmp (s lave)}/{set value of tdrmn (master) + 1} 100 0% output: set value of tdrmp (slave) = 0000h 100% output: set value of tdrmp (slave) {set value of tdrmn (master) + 1} remark the duty factor exceeds 100% if the set value of t drmp (slave) > (set value of tdrmn (master) + 1), it summarizes to 100% output. the master channel operates in the interval timer mode and counts the peri ods. when the channel start trigger (tsmn) is set to 1, inttmmn is output. tcrmn counts down starting fr om the loaded value of tdrmn, in synchronization with the count clock. when tcrmn = 0000h, inttmmn is output. tcrm n loads the value of tdrmn again. after that, it continues the similar operation. tcrmp of a slave channel operates in one-count mode, counts t he duty factor, and outputs a pwm waveform from the tomp pin. tcrmp of the slave channel loads the value of tdrmp, using intt mmn of the master channel as a start trigger, and stops counting until t he next start trigger (inttmmn of the master channel) is input. the output level of tomp becomes acti ve one count clock after generation of inttmmn from the master channel, and inactive when tcrmp = 0000h. caution to rewrite both tdrmn of the master channe l and tdrmp of the slave channel, a write access is necessary two times. the timing at which the values of tdrmn and tdrmp are loaded to tcrmn and tcrmp is upon occurrence of inttmmn of the master channel. thus, when rewriting is performed split before and after occurrence of inttmmn of th e master channel, the tomp pin cannot output the expected waveform. to rewrite both tdrmn of the m aster and tdrmp of the slave, therefore, be sure to rewrite both the registers immediately after inttmmn is generated fr om the master channel. remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, 6, p = n+1, to00 to to04, and to07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins ? m = 1, n = 0, 2, p = n+1, to10 to to13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 324 jun 20, 2011 figure 6-57. block diagram of operation as pwm function timer counter (tcrmn) interrupt signal (inttmmn) data register (tdrmn) interrupt controller clock selection trigger selection operation clock ckm0 ckm1 tsmn timer counter (tcrmp) interrupt signal (inttmmp) data register (tdrmp) interrupt controller clock selection trigger selection operation clock ckm0 ckm1 tomp pin output controller master channel (interval timer mode) slave channel (one-count mode) remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, 6, p = n+1, to00 to to04, and to07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins ? m = 1, n = 0, 2, p = n+1, to10 to to13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 325 jun 20, 2011 figure 6-58. example of basic ti ming of operation as pwm function tsmn temn tdrmn tcrmn tomn inttmmn a b 0000h tsmp temp tdrmp tcrmp tomp inttmmp c c d 0000h c d master channel slave channel a+1 a+1 b+1 ffffh ffffh remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, 6, p = n+1, to00 to to04, and to07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins ? m = 1, n = 0, 2, p = n+1, to10 to to13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 326 jun 20, 2011 figure 6-59. example of set contents of register s when pwm function (master channel) is used (a) timer mode register mn (tmrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrmn cksmn 1/0 0 0 ccsmn 0 mas termn 1 stsmn2 0 stsmn1 0 stsmn0 0 cismn1 0 cismn0 0 0 0 mdmn3 0 mdmn2 0 mdmn1 0 mdmn0 1 operation mode of channel n 000b: interval timer setting of operation when counting is started 1: generates inttmmn when counting is started. selection of timn pin input edge 00b: sets 00b because these are not used. start trigger selection 000b: selects only software start. slave/master selection 1: channel 1 is set as master channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ckm0 as operation clock of channel n. 1: selects ckm1 as operation clock of channel n. (b) timer output register m (tom) bit n tom tomn 0 0: outputs 0 from tomn. (c) timer output enable register m (toem) bit n toem toemn 0 0: stops the tomn output operation by counting operation. (d) timer output level register m (tolm) bit n tolm tolmn 0 0: cleared to 0 when tommn = 0 (toggle mode). (e) timer output mode register m (tomm) bit n tomm tommn 0 0: sets toggle mode. remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, 6, p = n+1, to00 to to04, to07, ti00 to ti04, and ti07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, 6, p = n+ 1, to00 to to07, ti00 to ti07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, 6, p = n+ 1, to00 to to07, ti00 to ti07 pins ? m = 1, n = 0, 2, p = n+1, to10 to to13, ti10 to ti13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 327 jun 20, 2011 figure 6-60. example of set contents of regist ers when pwm function (slave channel) is used (a) timer mode register mp (tmrmp) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrmp cksmp 1/0 0 0 ccsmp 0 mas termp 0 stsmp2 1 stsmp1 0 stsmp0 0 cismp1 0 cismp0 0 0 0 mdmp3 1 mdmp2 0 mdmp1 0 mdmp0 1 operation mode of channel p 100b: one-count mode start trigger during operation 1: trigger input is valid. selection of timp pin input edge 00b: sets 00b because these are not used. start trigger selection 100b: selects inttmmn of master channel. slave/master selection 0: channel 0 is set as slave channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ckm0 as operation clock of channel p. 1: selects ckm1 as operation clock of channel p. * make the same setting as master channel. (b) timer output register m (tom) bit p tom tomp 1/0 0: outputs 0 from tomp. 1: outputs 1 from tomp. (c) timer output enable register m (toem) bit p toem toemp 1/0 0: stops the tomp output operation by counting operation. 1: enables the tomp output operation by counting operation. (d) timer output level register m (tolm) bit p tolm tolmp 1/0 0: positive logic output (active-high) 1: inverted output (active-low) (e) timer output mode register m (tomm) bit p tomm tommp 1 1: sets the combination operation mode. remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, 6, p = n+1, to00 to to04, to07, ti00 to ti04, and ti07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, 6, p = n+ 1, to00 to to07, ti00 to ti07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, 6, p = n+ 1, to00 to to07, ti00 to ti07 pins ? m = 1, n = 0, 2, p = n+1, to10 to to13, ti10 to ti13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 328 jun 20, 2011 figure 6-61. operation procedure wh en pwm function is used (1/2) software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en or tau1en bits of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tpsm register. determines clock frequencies of ckm0 and ckm1. sets the tmrmn and tmrmp registers of two channels to be used (determines oper ation mode of channels). an interval (period) value is set to the tdrmn register of the master channel, and a duty factor is set to the tdrmp register of the slave channel. channel stops operating. (clock is supplied and some power is consumed.) channel default setting sets slave channel. the tommp bit of the tomn register is set to 1 (combination operation mode). sets the tolmp bit. sets the tomp bit and determines default level of the tomp output. sets toemp to 1 and enables operation of tomp. clears the port register and port mode register to 0. the tomn pin goes into hi-z output state. the tomn default setting level is output when the port mode register is in output mode and the port register is 0. tomp does not change because channel stops operating. the tomp pin outputs the tomp set level. remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, 6, p = n+1, to00 to to04, and to07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins ? m = 1, n = 0, 2, p = n+1, to10 to to13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 329 jun 20, 2011 figure 6-61. operation procedure wh en pwm function is used (2/2) software operation hardware status operation start sets toemp (slave) to 1 (only when operation is resumed). the tsmn (master) and tsmp (slave) bits of the tsm register are set to 1 at the same time. the tsmn and tsmp bits automatically return to 0 because they are trigger bits. temn = 1, temp = 1 when the master channel starts counting, inttmmn is generated. triggered by this interrupt, the slave channel also starts counting. during operation set values of the tmrmn and tmrmp registers and tommn, tommp, tolmn, and tolmp bits cannot be changed. set values of the tdrmn and tdrmp registers can be changed after inttmmn of the master channel is generated. the tcrmn and tcrmp registers can always be read. the tsrmn and tsrmp registers are not used. set values of the tom and toem registers cannot be changed. the counter of the master channel loads the tdrmn value to tcrmn, and counts down. when the count value reaches tcrmn = 0000h, inttmmn output is generated. at the same time, the value of the tdrmn register is loaded to tcrmn, and the counter starts counting down again. at the slave channel, the va lue of tdrmp is loaded to tcrmp, triggered by inttmmn of the master channel, and the counter starts counting down. the output level of tomp becomes active one c ount clock after generation of the inttmmn output from the master channel. it becomes inactive when tcrmp = 0000h, and the counting operation is stopped. after that, the above operation is repeated. the ttmn (master) and ttmp (slave) bits are set to 1 at the same time. the ttmn and ttmp bits automatically return to 0 because they are trigger bits. temn, temp = 0, and count operation stops. tcrmn and tcrmp hold count value and stops. the tomp output is not initialized but holds current status. operation stop toemp of slave channel is cleared to 0 and value is set to the tomp register. the tomp pin outputs the tomp set level. to hold the tomp pin output levels clears tomp bit to 0 after the value to be held is set to the port register. when holding the tomp pin output levels is not necessary switches the port mode register to input mode. the tomp pin output levels is held by port function. the tomp pin output levels go are into hi-z output state. tau stop the tau0en or tau1en bits of the per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the tomp bit is cleared to 0 and the tomp pin is set to port mode.) remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, 6, p = n+1, to00 to to04, and to07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins ? m = 1, n = 0, 2, p = n+1, to10 to to13 pins operation is resumed.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 330 jun 20, 2011 6.8.2 operation as one-shot pulse output function a one-shot pulse with any delay pulse width can be generat ed by using two channels in combination and timn pin input or software manipulation (tsmn = 1). the delay time and pulse width can be ca lculated by the following expressions. delay time = {set value of tdrmn (master) + 2} count clock period pulse width = {set value of tdrmp (slave)} count clock period the master channel operates in the one- count mode and counts the delays. t crmn of the master channel starts operating upon start trigger detection and tcrmn loads the value of tdrmn. tcrmn counts down from the value of tdrmn it has loaded, in synchronizati on with the count clock. when tcrm n = 0000h, it outputs inttmmn and stops counting until the next start trigger is detected. the slave channel operates in the on e-count mode and counts the pulse width. tcrmp of the slave channel starts operation using inttmmn of the master channel as a start trigger, and loads t he tdrmp value. tcrmp counts down from the value of tdrmp it has load ed, in synchronization with the count va lue. when tcrmp = 0000h, it outputs inttmmp and stops counting until the next star t trigger (inttmmn of the master channe l) is detected. the output level of tomp becomes active one count clock after generation of inttmmn from the master channel, and inactive when tcrmp = 0000h. instead of using the timn pin input, a one-shot pulse can al so be output using the software operation (tsmn = 1) as a start trigger. caution the timing of loading of tdrmn of the master channel is different from that of tdrmp of the slave channel. if tdrmn and tdrmp are re written during operation, therefore, an illegal waveform is output. be sure to rewrite tdrmn and t drmp after inttmmn of the channel to be rewritten is generated. remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, 6, p = n+1, to00 to to04, to07, ti00 to ti04, and ti07 pins ? channel 6 of timer array unit 0 can output a one-shot pulse only when software trigger start is selected and it is used as the master channel (because the ti06 pin is not provided). 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, 6, p = n+ 1, to00 to to07, ti00 to ti07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, 6, p = n+ 1, to00 to to07, ti00 to ti07 pins ? m = 1, n = 0, 2, p = n+1, to10 to to13, ti10 to ti13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 331 jun 20, 2011 figure 6-62. block diagram of operat ion as one-shot pulse output function timer counter (tcrmn) interrupt signal (inttmmn) data register (tdrmn) interrupt controller clock selection trigger selection operation clock ckm0 ckm1 tsmn timer counter (tcrmp) interrupt signal (inttmmp) data register (tdrmp) interrupt controller clock selection trigger selection operation clock ckm0 ckm1 tomp pin output controller master channel (one-count mode) slave channel (one-count mode) edge detection timn pin remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, 6, p = n+1, to00 to to04, to07, ti00 to ti04, and ti07 pins ? channel 6 of timer array unit 0 can output a one-shot pulse only when software trigger start is selected and it is used as the master channel (because the ti06 pin is not provided). 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, 6, p = n+ 1, to00 to to07, ti00 to ti07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, 6, p = n+ 1, to00 to to07, ti00 to ti07 pins ? m = 1, n = 0, 2, p = n+1, to10 to to13, ti10 to ti13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 332 jun 20, 2011 figure 6-63. example of basic timing of operation as one-shot pulse output function (start trigger tlmn input valid edge) temn tdrmn tcrmn tomn inttmmn a b 0000h tsmp temp tdrmp tcrmp tomp inttmmp 0000h b master channel slave channel a+2 b a+2 ffffh ffffh timn tsmn remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, 6, p = n+1, to00 to to04, and to07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins ? m = 1, n = 0, 2, p = n+1, to10 to to13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 333 jun 20, 2011 figure 6-64. example of set c ontents of registers when on e-shot pulse output function is used (master channel) (a) timer mode register mn (tmrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrmn cksmn 1/0 0 0 ccsmn 0 mas termn 1 stsmn2 0 stsmn1 0 stsmn0 1 cismn1 1/0 cismn0 1/0 0 0 mdmn3 1 mdmn2 0 mdmn1 0 mdmn0 0 operation mode of channel n 100b: one-count mode start trigger during operation 0: trigger input is invalid. selection of timn pin input edge 00b: detects falling edge. 01b: detects rising edge. 10b: detects both edges. 11b: setting prohibited start trigger selection 000b: selects the software trigger start. 001b: selects the timn pin input valid edge. slave/master selection 1: channel 1 is set as master channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ckm0 as operation clock of channels n. 1: selects ckm1 as operation clock of channels n. (b) timer output register m (tom) bit n tom tomn 0 0: outputs 0 from tomn. (c) timer output enable register m (toem) bit n toem toemn 0 0: stops the tomn output operation by counting operation. (d) timer output level register m (tolm) bit n tolm tolmn 0 0: cleared to 0 when tommn = 0 (toggle mode). (e) timer output mode register m (tomm) bit n tomm tommn 0 0: sets toggle mode. remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, 6, p = n+1, to00 to to04, to07, ti00 to ti04, and ti07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, 6, p = n+ 1, to00 to to07, ti00 to ti07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, 6, p = n+ 1, to00 to to07, ti00 to ti07 pins ? m = 1, n = 0, 2, p = n+1, to10 to to13, ti10 to ti13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 334 jun 20, 2011 figure 6-65. example of set contents of registers when one-shot pulse ou tput function is used (slave channel) (a) timer mode register mp (tmrmp) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrmp cksmp 1/0 0 0 ccsmp 0 mas termp 0 stsmp2 1 stsmp1 0 stsmp0 0 cismp1 0 cismp0 0 0 0 mdmp3 1 mdmp2 0 mdmp1 0 mdmp0 0 operation mode of channel p 100b: one-count mode start trigger during operation 0: trigger input is invalid. selection of timp pin input edge 00b: sets 00b because these are not used. start trigger selection 100b: selects inttmmn of master channel. slave/master selection 0: channel 0 is set as slave channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ckm0 as operation clock of channel p. 1: selects ckm1 as operation clock of channel p. * make the same setting as master channel. (b) timer output register m (tom) bit p tom tomp 1/0 0: outputs 0 from tomp. 1: outputs 1 from tomp. (c) timer output enable register m (toem) bit p toem toemp 1/0 0: stops the tomp output operation by counting operation. 1: enables the tomp output operation by counting operation. (d) timer output level register m (tolm) bit p tolm tolmp 1/0 0: positive logic output (active-high) 1: inverted output (active-low) (e) timer output mode register m (tomm) bit p tomm tommp 1 1: sets the combination operation mode. remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, 6, p = n+1, to00 to to04, to07, ti00 to ti04, and ti07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, 6, p = n+ 1, to00 to to07, ti00 to ti07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, 6, p = n+ 1, to00 to to07, ti00 to ti07 pins ? m = 1, n = 0, 2, p = n+1, to10 to to13, ti10 to ti13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 335 jun 20, 2011 figure 6-66. operation procedure of one-shot pulse output function (1/2) software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en or tau1en bits of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tpsm register. determines clock frequencies of ckm0 and ckm1. sets the tmrmn and tmrmp registers of two channels to be used (determines oper ation mode of channels). an output delay is set to the tdrmn register of the master channel, and a pulse width is set to the tdrmp register of the slave channel. channel stops operating. (clock is supplied and some power is consumed.) channel default setting sets slave channel. the tommp bit of the tomm register is set to 1 (combination operation mode). sets the tolmp bit. sets the tomp bit and determines default level of the tomp output. sets toemp to 1 and enables operation of tomp. clears the port register and port mode register to 0. the tomn pin goes into hi-z output state. the tomn default setting level is output when the port mode register is in output mode and the port register is 0. tomp does not change because channel stops operating. the tomp pin outputs the tomp set level. remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, 6, p = n+1, to00 to to04, and to07 pins ? channel 6 of timer array unit 0 can output a one-shot pulse only when software trigger start is selected and it is used as the master channel (because the ti06 pin is not provided). 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins ? m = 1, n = 0, 2, p = n+1, to10 to to13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 336 jun 20, 2011 figure 6-66. operation procedure of one-shot pulse output function (2/2) software operation hardware status sets toemp (slave) to 1 (only when operation is resumed). the tsmn (master) and tsmp (slave) bits of the tsm register are set to 1 at the same time. the tsmn and tsmp bits automatically return to 0 because they are trigger bits. temn and temp are set to 1 and the master channel enters the timn input edge detection wait status. counter stops operating. operation start detects the start trigger of master channel. (the valid edge of the timn pin input is detected or the tsmn bit is set to 1.) master channel starts counting. during operation set values of only the cismn1 and cismn0 bits of the tmrmn register can be changed. set values of the tmrmp, tdrmn, and tdrmp registers and tommn, tommp, tolmn, and tolmp bits cannot be changed. the tcrmn and tcrmp registers can always be read. the tsrmn and tsrmp registers are not used. set values of the tom and toem registers can be changed. master channel loads the value of tdrmn to tcrmn when the start trigger is detected, and the counter starts counting down. when the count value reaches tcrmn = 0000h, the inttmmn output is generated, and the counter stops until the next valid edge is input to the timn pin. the slave channel, triggered by inttmmn of the master channel, loads the value of tdrmp to tcrmp, and the counter starts counting down. the output level of tomp becomes active one count clock after generation of inttmmn from the master channel. it becomes inactive when tcrmp = 0000h, and the counting operation is stopped. after that, the above operation is repeated. the ttmn (master) and ttmp (slave) bits are set to 1 at the same time. the ttmn and ttmp bits automatically return to 0 because they are trigger bits. temn, temp = 0, and count operation stops. tcrmn and tcrmp hold count value and stops. the tomp output is not initialized but holds current status. operation stop toemp of slave channel is cleared to 0 and value is set to the tom register. the tomp pin outputs the tomn set level. to hold the tomp pin output levels clears tomp bit to 0 after the value to be held is set to the port register. when holding the tomp pin output levels is not necessary switches the port mode register to input mode. the tomp pin output levels is held by port function. the tomp pin output levels go are into hi-z output state. tau stop the tau0en or tau1en bits of the per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the tomp bit is cleared to 0 and the tomp pin is set to port mode.) remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, 6, p = n+1, to00 to to04, and to07 pins ? channel 6 of timer array unit 0 can output a one-shot pulse only when software trigger start is selected and it is used as the master channel (because the ti06 pin is not provided). 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, 6, p = n+1, to00 to to07 pins ? m = 1, n = 0, 2, p = n+1, to10 to to13 pins operation is resumed.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 337 jun 20, 2011 6.8.3 operation as multiple pwm output function by extending the pwm function and using two or more sl ave channels, many pwm output signals can be produced. for example, when using two slave channels, the period and du ty factor of an output pul se can be calculated by the following expressions. pulse period = {set value of tdrmn (master) + 1} count clock period duty factor 1 [%] = {set value of tdrmp (s lave 1)}/{set value of tdrmn (master) + 1} 100 duty factor 2 [%] = {set value of tdrmp (s lave 2)}/{set value of tdrmn (master) + 1} 100 remark although the duty factor exceeds 100% if the set value of tdrmp (slave 1) > {set value of tdrmn (master) + 1} or if the {set value of tdrmq (slave 2)} > {set value of tdrmn (master) + 1}, it is summarized into 100% output. tcrmn of the master channel operates in the interval timer mode and counts the periods. tcrmp of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a pwm waveform from the tomp pin. tcrmp loads the value of tdrmp to tcrmp, using inttmmn of the master channel as a start trigger, and start counting down. when tcrmp = 0000h, tcrmp outputs inttmmp and stops counting until the next start trigger (inttmmn of the master channel) has been input. the out put level of tomp becomes active one count clock after generation of inttmmn from the master channel, and inactive when tcrmp = 0000h. in the same way as tcrmp of the slav e channel 1, tcrmq of the slave channel 2 operates in one-count mode, counts the duty factor, and outputs a pwm waveform from the tomq pi n. tcrmq loads the value of tdrmq to tcrmq, using inttmmn of the master channel as a start trigger, and starts counting down. when tcrmq = 0000h, tcrmq outputs inttmmq and stops counting until the next start trigger (intt mmn of the master channel) has been input. the output level of tomq becomes active one count clock after generati on of inttmmn from the master channel, and inactive when tcrmq = 0000h. when channel 0 is used as the master channel as described above, up to seven types of pwm signals can be output at the same time with timer array unit 0 and up to three types with timer array unit 1. caution to rewrite both tdrmn of the master channe l and tdrmp of the slave channel 1, write access is necessary at least twice. since the values of tdrmn and tdrmp are loaded to tcrmn and tcrmp after inttmmn is generated from the master channel, if rewriti ng is performed sepa rately before and after generation of inttmmn from the master chan nel, the tomp pin cannot output the expected waveform. to rewrite both tdrmn of the master and tdrmp of the slave, be sure to rewrite both the registers immediately after inttmmn is generated from the master channel (this applies also to tdrmq of the slave channel 2) . remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, p = n+1, q = n+2, to00 to to04, and to07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, p = n+1, q = n+2, to00 to to07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, p = n+1, q = n+2, to00 to to07 pins ? m = 1, n = 0, p = 1, q = 2, to10 to to13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 338 jun 20, 2011 figure 6-67. block diagram of operation as multiple pwm output function (output two types of pwms) timer counter (tcrmn) interrupt signal (inttmmn) data register (tdrmn) interrupt controller clock selection trigger selection operation clock ckm0 ckm1 tsmn timer counter (tcrmp) interrupt signal (inttmmp) data register (tdrmp) interrupt controller clock selection trigger selection operation clock ckm0 ckm1 tomp pin output controller master channel (interval timer mode) slave channel 1 (one-count mode) timer counter (tcrmq) interrupt signal (inttmmq) data register (tdrmq) interrupt controller clock selection trigger selection operation clock ckm0 ckm1 tomq pin output controller slave channel 2 (one-count mode) remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, p = n+1, q = n+2, to00 to to04, and to07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, p = n+1, q = n+2, to00 to to07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, p = n+1, q = n+2, to00 to to07 pins ? m = 1, n = 0, p = 1, q = 2, to10 to to13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 339 jun 20, 2011 figure 6-68. example of basic timing of operation as multiple pwm output function (output two types of pwms) tsmn temn tdrmn tcrmn tomn inttmmn a b 0000h tsmp temp tdrmp tcrmp tomp inttmmp c c d 0000h c d master channel slave channel 1 a+1 a+1 b+1 ffffh ffffh tsmq temq tdrmq tcrmq tomq inttmmq e f 0000h e f slave channel 2 a+1 a+1 b+1 ffffh e f d remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, p = n+1, q = n+2, to00 to to04, and to07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, p = n+1, q = n+2, to00 to to07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, p = n+1, q = n+2, to00 to to07 pins ? m = 1, n = 0, p = 1, q = 2, to10 to to13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 340 jun 20, 2011 figure 6-69. example of set contents of registers when multiple pwm output function (master channel) is used (a) timer mode register mn (tmrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrmn cksmn 1/0 0 0 ccsmn 0 mas termn 1 stsmn2 0 stsmn1 0 stsmn0 0 cismn1 0 cismn0 0 0 0 mdmn3 0 mdmn2 0 mdmn1 0 mdmn0 1 operation mode of channel n 000b: interval timer setting of operation when counting is started 1: generates inttmmn when counting is started. selection of timn pin input edge 00b: sets 00b because these are not used. start trigger selection 000b: selects only software start. slave/master selection 1: channel 1 is set as master channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ckm0 as operation clock of channel n. 1: selects ckm1 as operation clock of channel n. (b) timer output register m (tom) bit n tom tomn 0 0: outputs 0 from tomn. (c) timer output enable register m (toem) bit n toem toemn 0 0: stops the tomn output operation by counting operation. (d) timer output level register m (tolm) bit n tolm tolmn 0 0: cleared to 0 when tommn = 0 (toggle mode). (e) timer output mode register m (tomm) bit n tomm tommn 0 0: sets toggle mode. remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, to00 to to04, to07, ti00 to ti04, and ti07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, to00 to to07, and ti00 to ti07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, to00 to to07, and ti00 to ti07 pins ? m = 1, n = 0, to10 to to13 , and ti10 to ti13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 341 jun 20, 2011 figure 6-70. example of set contents of registers when multiple pwm output function (slave channel) is used (output two types of pwms) (a) timer mode register mp, mq (tmrmp, tmrmq) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrmp cksmp 1/0 0 0 ccsmp 0 mas termp 0 stsmp2 1 stsmp1 0 stsmp0 0 cismp1 0 cismp0 0 0 0 mdmp3 1 mdmp2 0 mdmp1 0 mdmp0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmrmq cksmq 1/0 0 0 ccsmq 0 mas termq 0 stsmq2 1 stsmq1 0 stsmq0 0 cismq1 0 cismq0 0 0 0 mdmq3 1 mdmq2 0 mdmq1 0 mdmq0 1 operation mode of channel p, q 100b: one-count mode start trigger during operation 1: trigger input is valid. selection of timp and timq pin input edge 00b: sets 00b because these are not used. start trigger selection 100b: selects inttmmn of master channel. slave/master selection 0: channel 0 is set as slave channel. count clock selection 0: selects operation clock. operation clock selection 0: selects ckm0 as operation clock of channel p, q. 1: selects ckm1 as operation clock of channel p, q. * make the same setting as master channel. (b) timer output register m (tom) bit q bit p tom tomq 1/0 tomp 1/0 0: outputs 0 from tomp or tomq. 1: outputs 1 from tomp or tomq. (c) timer output enable register m (toem) bit q bit p toem toemq 1/0 toemp 1/0 0: stops the tomp or tomq output operation by counting operation. 1: enables the tomp or tomq output operation by counting operation. (d) timer output level register m (tolm) bit q bit p tolm tolmq 1/0 tolmp 1/0 0: positive logic output (active-high) 1: inverted output (active-low) (e) timer output mode register m (tomm) bit q bit p tomm tommq 1 tommp 1 1: sets the combination operation mode.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 342 jun 20, 2011 remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, p = n+1, q = n+2, to00 to to04, and to07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, p = n+1, q = n+2, to00 to to07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, p = n+1, q = n+2, to00 to to07 pins ? m = 1, n = 0, p = 1, q = 2, to10 to to13 pins figure 6-71. operation procedure when mult iple pwm output function is used (1/2) software operation hardware status power-off status (clock supply is stopped and writing to each register is disabled.) sets the tau0en or tau1en bits of the per0 register to 1. power-on status. each channel stops operating. (clock supply is started and writing to each register is enabled.) tau default setting sets the tpsm register. determines clock frequencies of ckm0 and ckm1. sets the tmrmn, tmrmp, and tmrmq registers of each channel to be used (determines operation mode of channels). an interval (period) value is set to the tdrmn register of the master channel, and a duty factor is set to the tdrmp and tdrmq register of the slave channel. channel stops operating. (clock is supplied and some power is consumed.) channel default setting sets slave channel. the tommp and tommq bits of the tomm register are set to 1 (combination operation mode). clears the tolmp and tolmq bits to 0. sets the tomp and tomq bits and determines default level of the tomp and tomq outputs. sets toemp or toemq to 1 and enables operation of tomp and tomq. clears the port register and port mode register to 0. the tomn pin goes into hi-z output state. the tomp and tomq default setting levels are output when the port mode register is in output mode and the port register is 0. tomp or tomq does not change because channel stops operating. the tomp and tomq pins output the tomp and tomq set levels. remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, p = n+1, q = n+2, to00 to to04, and to07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, p = n+1, q = n+2, to00 to to07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, p = n+1, q = n+2, to00 to to07 pins ? m = 1, n = 0, p = 1, q = 2, to10 to to13 pins
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 343 jun 20, 2011 figure 6-71. operation procedure when mult iple pwm output function is used (2/2) software operation hardware status operation start sets toemp and toemq (slave) to 1 (only when operation is resumed). the tsmn bit (master), and tsmp and tsmq (slave) bits of the tsm register are set to 1 at the same time. the tsmn, tsmp, and tsmq bits automatically return to 0 because they are trigger bits. temn = 1, temp, temq = 1 when the master channel starts counting, inttmmn is generated. triggered by this interrupt, the slave channel also starts counting. during operation set values of the tmrmn, tmrmp, and tmrmq registers and tommn, tommp, tommq, tolmn, tolmp, and tolmq bits cannot be changed. set values of the tdrmn, tdrmp, and tdrmq registers can be changed after inttmmn of the master channel is generated. the tcrmn, tcrmp, and tcrmq registers can always be read. the tsrmn, tsrmp, and tsrmq registers are not used. set values of the tom and toem registers can be changed. the counter of the master channel loads the tdrmn value to tcrmn and counts down. when the count value reaches tcrmn = 0000h, inttmmn output is generated. at the same time, the value of the tdrmn register is loaded to tcrmn, and the counter starts counting down again. at the slave channel 1, the values of tdrmp are transferred to tcrmp, triggered by inttmmn of the master channel, and the counter starts counting down. the output levels of tomp become active one count clock after generation of the inttmmn output from the master channel. it becomes inactive when tcrmp = 0000h, and the counting operation is stopped. at the slave channel 2, the values of tdrmq are transferred to tdrmq, triggered by inttmmn of the master channel, and the counter starts counting down. the output levels of tomq become active one count clock after generation of the inttmmn output from the master channel. it becomes inactive when tcrmq = 0000h, and the counting operation is stopped. after that, the above operation is repeated. the ttmn bit (master), ttmp, and ttmq (slave) bits are set to 1 at the same time. the ttmn, ttmp, and ttmq bits automatically return to 0 because they are trigger bits. temn, temp, and temq = 0, and count operation stops. tcrmn, tcrmp and tcrmq hold count value and stops. the tomp and tomq outputs are not initialized but holds current status. operation stop toemp or toemq of slave channel is cleared to 0 and value is set to the tomp and tomq registers. the tomp and tomq pins output the tomp and tomq set levels. to hold the tomp and tomq pins output levels clears tomp and tomq bits to 0 after the value to be held is set to the port register. when holding the tomp and tomq pins output levels is not necessary switches the port mode register to input mode. the tomp and tomq pins output levels are held by port function. the tomp and tomq pins output levels go into hi-z output state. tau stop the tau0en or tau1en bits of the per0 register is cleared to 0. power-off status all circuits are initialized and sfr of each channel is also initialized. (the tomp and tomq bits are cleared to 0 and the tomp and tomq pins are set to port mode.) operation is resumed.
78k0r/lx3 chapter 6 timer array unit r01uh0004ej0501 rev.5.01 344 jun 20, 2011 remarks 1. 78k0r/lf3: ? m = 0, n = 0, 2, p = n+1, q = n+2, to00 to to04, and to07 pins 2 . 78k0r/lg3: ? m = 0, n = 0, 2, 4, p = n+1, q = n+2, to00 to to07 pins 3. 78k0r/lh3: ? m = 0, n = 0, 2, 4, p = n+1, q = n+2, to00 to to07 pins ? m = 1, n = 0, p = 1, q = 2, to10 to to13 pins
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 345 jun 20, 2011 chapter 7 real-time counter 7.1 functions of real-time counter the real-time counter is mounted onto all 78k0r/lx 3 microcontroller products. the real-time counter ha s the following features. ? having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years. ? constant-period interrupt function (period: 1 month to 0.5 seconds) ? alarm interrupt function (alarm: week, hour, minute) ? interval interrupt function ? pin output function of 1 hz ? pin output function of 512 hz or 16.384 khz or 32.768 khz 7.2 configuration of real-time counter the real-time counter includes the following hardware. table 7-1. configuration of real-time counter item configuration peripheral enable register 0 (per0) real-time counter control register 0 (rtcc0) real-time counter control register 1 (rtcc1) real-time counter control register 2 (rtcc2) sub-count register (rsubc) second count register (sec) minute count register (min) hour count register (hour) day count register (day) week count register (week) month count register (month) year count register (year) watch error correction register (subcud) alarm minute register (alarmwm) alarm hour register (alarmwh) alarm week register (alarmww) port mode register 3 control registers port register 3
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 346 jun 20, 2011 figure 7-1. block diagra m of real-time counter intrtc f sub rtce rcloe1 rcloe0 ampm ct2 ct1 ct0 rinte rcloe2 ict2 ict1 ict0 rtce ampm ct0 to ct2 rckdiv f sub rckdiv rinte intrtci rcloe2 f sub rwait wale walie wafg rwait rwst rifg rwst rifg 12-bit counter real-time counter control register 1 (rtcc1) real-time counter control register 0 (rtcc0) alarm week register (alarmww) (7-bit) alarm hour register (alarmwh) (6-bit) alarm minute register (alarmwm) (7-bit) year count register (year) (8-bit) month count register (month) (5-bit) week count register (week) (3-bit) day count register (day) (6-bit) hour count register (hour) (6-bit) minute count register (min) (7-bit) second count register (sec) (7-bit) wait control 0.5 seconds sub-count register (rsubc) (16-bit) count clock = 32.768 khz selector buffer buffer buffer buffer buffer buffer buffer count enable/ disable circuit watch error correction register (subcud) (8-bit) selector selector internal bus real-time counter control register 2 (rtcc2) 1 month 1 day 1 hour 1 minute rtcdiv/ rtccl/ti00/ to03/intp2/ p31 to lcd driver/controller rtc1hz/ ti03/to00/ p30/intp1 pm30 output latch ( p30) pm31 output latch ( p31) to cannels 0 or 4 of the tau0
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 347 jun 20, 2011 7.3 registers controlling real-time counter timer real-time counter is controlle d by the following 18 registers. ? peripheral enable register 0 (per0) ? real-time counter control register 0 (rtcc0) ? real-time counter control register 1 (rtcc1) ? real-time counter control register 2 (rtcc2) ? sub-count register (rsubc) ? second count register (sec) ? minute count register (min) ? hour count register (hour) ? day count register (day) ? week count register (week) ? month count register (month) ? year count register (year) ? watch error correction register (subcud) ? alarm minute register (alarmwm) ? alarm hour register (alarmwh) ? alarm week register (alarmww) ? port mode register 3 (pm3) ? port register 3 (p3)
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 348 jun 20, 2011 (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to r educe the power consumption and noise. when the real-time counter is used, be sure to set bit 7 (rtcen) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-2. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> per0 rtcen dacen adcen iicaen note1 sau1en sau0en tau1en tau0en rtcen control of real-time counter (rtc) input clock note2 0 stops supply of input clock. ? sfr used by the real-time counter (rtc) cannot be written. ? the real-time counter (rtc) is in the reset status. 1 supplies input clock. ? sfr used by the real-time counter (rtc) can be read/written. notes 1. 78k0r/lg3, 78k0r/lh3 only 2. by using rtcen, can supply and stop the clock that is used when accessing the real-time counter (rtc) from the cpu. rtcen cannot control supply of the operating clock (f sub ) to rtc. cautions 1. when using the real-time counter, first set rtcen to 1, while oscillation of the subsystem clock (f sub ) is stable. if rtcen = 0, writing to a control register of the real-time counter is ignored, and, even if the register is read, only the default value is read. 2. clock supply to peripheral functions excep t the real-time counter can be stopped in the halt mode when operating on the sub system clock by setti ng rtclpc of the operation speed mode control register (osmc) to 1. in this case, set rtcen to 1 and bits 0 to 6 of per0 to 0. (2) real-time counter cont rol register 0 (rtcc0) the rtcc0 register is an 8-bit register that is used to start or stop the real-time co unter operation, control the rtccl and rtc1hz pins, and set a 12- or 24-hour system and the constant-per iod interrupt function. rtcc0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h.
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 349 jun 20, 2011 figure 7-3. format of real-time c ounter control register 0 (rtcc0) address: fff9dh after reset: 00h r/w symbol <7> 6 <5> <4> 3 2 1 0 rtcc0 rtce 0 rcloe1 rcloe0 ampm ct2 ct1 ct0 rtce real-time counter operation control 0 stops counter operation. 1 starts counter operation. rcloe1 rtc1hz pin output control 0 disables output of rtc1hz pin (1 hz). 1 enables output of rtc1hz pin (1 hz). rcloe0 note rtccl pin output control 0 disables output of rtccl pin (32 khz). 1 enables output of rtccl pin (32 khz). ampm selection of 12-/24-hour system 0 12-hour system (a.m. and p.m. are displayed.) 1 24-hour system ? to change the value of ampm, set rwait (bit 0 of rtcc 1) to 1, and re-set the hour count register (hour). ? table 7-2 shows the displayed ti me digits that are displayed. ct2 ct1 ct0 constant-period interrupt (intrtc) selection 0 0 0 does not use constant-period interrupt function. 0 0 1 once per 0.5 s (synchronized with second count up) 0 1 0 once per 1 s (same time as second count up) 0 1 1 once per 1 m (second 00 of every minute) 1 0 0 once per 1 hour (minute 00 and second 00 of every hour) 1 0 1 once per 1 day (hour 00, minute 00, and second 00 of every day) 1 1 once per 1 month (day 1, hour 00 a.m., minute 00, and second 00 of every month) when changing the values of ct2 to ct0 while the counter operates (rtce = 1), rewrite the values of ct2 to ct0 after disabling interrupt servicing intrtc by using the inte rrupt mask flag register. furthermore, after rewriting the values of ct2 to ct0, enable interrupt serv icing after clearing the rifg and rtcif flags. note rcloe0 and rcloe2 must not be enabled at the same time. caution if rcloe0 and rcloe1 are changed when rtce = 1, the last wavefo rm of the 32.768 khz and 1 hz output signals may become short. remark : don?t care
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 350 jun 20, 2011 (3) real-time counter cont rol register 1 (rtcc1) the rtcc1 register is an 8-bit register that is used to control the alarm interr upt function and the wait time of the counter. rtcc1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-4. format of real-time count er control register 1 (rtcc1) (1/2) address: fff9eh after reset: 00h r/w symbol <7> <6> 5 <4> <3> 2 <1> <0> rtcc1 wale walie 0 wafg rifg 0 rwst rwait wale alarm operation control 0 match operation is invalid. 1 match operation is valid. when setting a value to the wale bit while the counter ope rates (rtce = 1) and walie = 1, rewrite the wale bit after disabling interrupt servicing intr tc by using the interrupt mask flag r egister. furthermore, clear the wafg and rtcif flags after rewriting the wale bit. when setti ng each alarm register (walie flag of rtcc1, the alarmwm register, the alarmwh register, and the alarmww register), set match operation to be invalid (?0?) for the wale bit. walie control of alarm interrupt (intrtc) function operation 0 does not generate interrupt on matching of alarm. 1 generates interrupt on matching of alarm. wafg alarm detection status flag 0 alarm mismatch 1 detection of matching of alarm this is a status flag that indicates detection of matching wi th the alarm. it is valid only when wale = 1 and is set to ?1? one clock (32.768 khz) after matching of the alarm is detec ted. this flag is cleared w hen ?0? is written to it. writing ?1? to it is invalid.
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 351 jun 20, 2011 figure 7-4. format of real-time count er control register 1 (rtcc1) (2/2) rifg constant-period interrupt status flag 0 constant-period interrupt is not generated. 1 constant-period interrupt is generated. this flag indicates the status of generation of the const ant-period interrupt. when the constant-period interrupt is generated, it is set to ?1?. this flag is cleared when ?0? is written to it. writing ?1? to it is invalid. rwst wait status flag of real-time counter 0 counter is operating. 1 mode to read or write counter value this status flag indicates whether the setting of rwait is valid. before reading or writing the counter value, confirm that the value of this flag is 1. rwait wait control of real-time counter 0 sets counter operation. 1 stops sec to year counters. mode to read or write counter value this bit controls the operation of the counter. be sure to write ?1? to it to read or write the counter value. because rsubc continues operation, complete reading or writ ing of it in 1 second, and clear this bit back to 0. when rwait = 1, it takes up to 1 clock (32.768 khz) until the counter value can be read or written. if rsubc overflows when rwait = 1, it counts up after rwai t = 0. if the second count register is written, however, it does not count up because rsubc is cleared. caution if writing is performed to the rtcc1 regist er with a 1-bit manipulation instruction, the rifg and wafg flags may be cleared. therefore, to perform writing to the rifg and wafg flags, be sure to use an 8-bit manipulation instruction. at th is time, set 1 to the rifg and wafg flags to invalidate writing and not to clear the rifg and wafg flags during writing. when the value may be rewritten because the rifg and wafg flags are not being u sed, the rtcc1 register may be written by using a 1-bit manipulation instruction. remark fixed-cycle interrupts and alarm match interrupts us e the same interrupt sour ce (intrtc). when using these two types of interrupts at the same time, wh ich interrupt occurred can be judged by checking the fixed-cycle interrupt status fl ag (rifg) and the alarm detection status flag (wafg) upon intrtc occurrence.
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 352 jun 20, 2011 (4) real-time counter cont rol register 2 (rtcc2) the rtcc2 register is an 8-bit register that is used to control the interval interrupt function and the rtcdiv pin. rtcc2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-5. format of real-time c ounter control register 2 (rtcc2) address: fff9fh after reset: 00h r/w symbol <7> <6> <5> 4 3 2 1 0 rtcc2 rinte rcloe2 rckdiv 0 0 ict2 ict1 ict0 rinte ict2 ict1 ict0 interval interrupt (intrtci) selection 0 interval interrupt is not generated. 1 0 0 0 2 6 /f sub (1.953125 ms) 1 0 0 1 2 7 /f sub (3.90625 ms) 1 0 1 0 2 8 /f sub (7.8125 ms) 1 0 1 1 2 9 /f sub (15.625 ms) 1 1 0 0 2 10 /f sub (31.25 ms) 1 1 0 1 2 11 /f sub (62.5 ms) 1 1 1 2 12 /f sub (125 ms) rcloe2 note rtcdiv pin output control 0 disables output of rtcdiv pin 1 enables output of rtcdiv pin rckdiv selection of rtcdiv pin output frequency 0 rtcdiv pin outputs 512 hz (1.95 ms). 1 rtcdiv pin outputs 16.384 khz (0.061 ms). note rcloe0 and rcloe2 must not be enabled at the same time. cautions 1. change ict2, ict1, and ict0 when rinte = 0. 2. when the output from rtcdiv pin is stoppe d, the output continues after a maximum of two clocks of f xt and enters the low level. while 512 hz is output, and when the output is stopped immediately after entering th e high level, a pulse of at least one clock width of f sub may be generated. 3. after the real-time counter starts operati ng, the output width of the rtcdiv pin may be shorter than as set during th e first interval period. remark f sub : subsystem clock frequency
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 353 jun 20, 2011 (5) sub-count regi ster (rsubc) the rsubc register is a 16-bit register t hat counts the reference time of 1 second of the real-time counter. it takes a value of 0000h to 7fffh and counts 1 second with a clock of 32.768 khz. rsubc can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. cautions 1. when a correction is made by using the subcud register , the value may become 8000h or more. 2. this register is also cl eared by reset effected by wr iting the second count register. 3. the value read from this register is not guaranteed if it is read during operation, because a value that is changing is read. figure 7-6. format of sub-count register (rsubc) address: fff90h after reset: 0000h r symbol 7 6 5 4 3 2 1 0 rsubc subc7 subc6 subc5 subc4 subc3 subc2 subc1 subc0 address: fff91h after reset: 0000h r symbol 7 6 5 4 3 2 1 0 rsubc subc15 subc14 subc13 subc12 subc11 subc10 subc9 subc8 (6) second count register (sec) the sec register is an 8-bit register that takes a value of 0 to 59 (dec imal) and indicates the count value of seconds. it counts up when the sub-counter overflows. when data is written to this register, it is written to a buff er and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 59 to this register in bcd code. sec can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-7. format of second count register (sec) address: fff92h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 sec 0 sec40 sec20 sec10 sec8 sec4 sec2 sec1
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 354 jun 20, 2011 (7) minute count register (min) the min register is an 8-bit register t hat takes a value of 0 to 59 (decimal) and indicates the count value of minutes. it counts up when the second counter overflows. when data is written to this register, it is written to a buff er and then to the counter up to 2 clocks (32.768 khz) later. even if the second count register overflows while this regist er is being written, this regi ster ignores the overflow and is set to the value written. set a decimal value of 00 to 59 to this register in bcd code. min can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-8. format of minute count register (min) address: fff93h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 min 0 min40 min20 min10 min8 min4 min2 min1 (8) hour count register (hour) the hour register is an 8-bi t register that takes a value of 00 to 23, or 01 to 12 and 21 to 32 (decimal) and indicates the count value of hours. it counts up when the minute counter overflows. when data is written to this register, it is written to a buff er and then to the counter up to 2 clocks (32.768 khz) later. even if the minute count register overflows while this register is being written, this register ignores the overflow and is set to the value written. set a decimal value of 00 to 23, or 01 to 12 and 21 to 32 to this register in bcd code. hour can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 12h. however, the value of this register is 00h if the ampm bit (bit 3 of the rtcc0 regist er) is set to 1 after reset. figure 7-9. format of hour count register (hour) address: fff94h after reset: 12h r/w symbol 7 6 5 4 3 2 1 0 hour 0 0 hour20 hour10 ho ur8 hour4 hour2 hour1 caution bit 5 (hour20) of hour in dicates am(0)/pm(1) if ampm = 0 (if the 12-hour system is selected).
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 355 jun 20, 2011 table 7-2. displayed time digits 24-hour display (ampm bit = 1) 12-hour display (ampm bit = 0) time hour register time hour register 0 00h 0 a.m. 12h 1 01h 1 a.m. 01h 2 02h 2 a.m. 02h 3 03h 3 a.m. 03h 4 04h 4 a.m. 04h 5 05h 5 a.m. 05h 6 06h 6 a.m. 06h 7 07h 7 a.m. 07h 8 08h 8 a.m. 08h 9 09h 9 a.m. 09h 10 10h 10 a.m. 10h 11 11h 11 a.m. 11h 12 12h 0 p.m. 32h 13 13h 1 p.m. 21h 14 14h 2 p.m. 22h 15 15h 3 p.m. 23h 16 16h 4 p.m. 24h 17 17h 5 p.m. 25h 18 18h 6 p.m. 26h 19 19h 7 p.m. 27h 20 20h 8 p.m. 28h 21 21h 9 p.m. 29h 22 22h 10 p.m. 30h 23 23h 11 p.m. 31h the hour register value is set to 12-hour display when the ampm bit is ?0? and to 24-hour display when the ampm bit is ?1?. in 12-hour display, the fifth bit of the ho ur register displays 0 for am and 1 for pm. (9) day count register (day) the day register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. it counts up when the hour counter overflows. this counter counts as follows. ? 01 to 31 (january, march, may, july, august, october, december) ? 01 to 30 (april, june, september, november) ? 01 to 29 (february, leap year) ? 01 to 28 (february, normal year) when data is written to this register, it is written to a buff er and then to the counter up to 2 clocks (32.768 khz) later. even if the hour count register overflows wh ile this register is being written, this register ignores the overflow and is set to the value written. set a decimal value of 01 to 31 to this register in bcd code. day can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 01h.
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 356 jun 20, 2011 figure 7-10. format of day count register (day) address: fff96h after reset: 01h r/w symbol 7 6 5 4 3 2 1 0 day 0 0 day20 day10 day8 day4 day2 day1 (10) week count register (week) the week register is an 8-bit register that takes a value of 0 to 6 (decim al) and indicates t he count value of weekdays. it counts up in synchronization with the day counter. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 06 to this register in bcd code. week can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-11. format of week count register (week) address: fff95h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 week 0 0 0 0 0 week4 week2 week1 caution the value corresponding to th e month count register or the day count register is not stored in the week count register automatica lly. after reset release, set the week count register as follow. day week sunday 00h monday 01h tuesday 02h wednesday 03h thursday 04h friday 05h saturday 06h
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 357 jun 20, 2011 (11) month count register (month) the month register is an 8-bi t register that takes a value of 1 to 12 (decimal) and indicates the count value of months. it counts up when the day counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. even if the day count register overflows while this r egister is being written, this register ignores the overflow and is set to the value written. set a decimal value of 01 to 12 to this register in bcd code. set a decimal value of 01 to 12 to this register in bcd code. month can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 01h. figure 7-12. format of month count register (month) address: fff97h after reset: 01h r/w symbol 7 6 5 4 3 2 1 0 month 0 0 0 month10 month8 month4 month2 month1 (12) year count register (year) the year register is an 8-bit register t hat takes a value of 0 to 99 (decimal) an d indicates the count value of years. it counts up when the month counter overflows. values 00, 04, 08, ?, 92, and 96 indicate a leap year. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. even if the month count register overflows while th is register is being written, this register ignores the overflow and is set to the value written. set a decimal valu e of 00 to 99 to this register in bcd code. set a decimal value of 00 to 99 to this register in bcd code. year can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-13. format of year count register (year) address: fff98h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 year year80 year40 year20 year10 year8 year4 year2 year1
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 358 jun 20, 2011 (13) watch error correction register (subcud) this register is used to correct the watch with high ac curacy when it is slow or fast by changing the value (reference value: 7fffh) that overflow s from the sub-count register (rsu bc) to the second count register. rewrite the subcud register after disabling interrupt servicing intrtc by using the interrupt mask flag register. furthermore, after rewriting the subcud register, enable interrupt servicing after clearing the interrupt request flag (rtcif) and constant-period interrupt status flag (rifg). subcud can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-14. format of watch e rror correction register (subcud) address: fff99h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 subcud dev f6 f5 f4 f3 f2 f1 f0 dev setting of watch error correction timing 0 corrects watch error when the second digits are at 00, 20, or 40 (every 20 seconds). 1 corrects watch error only when the second digits are at 00 (every 60 seconds). writing to the subcud register at the following timing is prohibited. ? when dev = 0 is set: for a period of sec = 00h, 20h, 40h ? when dev = 1 is set: for a period of sec = 00h f6 setting of watch error correction value 0 increases by {(f5, f4, f3, f2, f1, f0) ? 1} 2. 1 decreases by {(/f5, /f4, /f3, /f2, /f1, /f0) + 1} 2. when (f6, f5, f4, f3, f2, f1, f0) = (*, 0, 0, 0, 0, 0, *), the watch error is not corrected. * is 0 or 1. /f5 to /f0 are the inverted values of the corresponding bits (000011 when 111100). range of correction value: (when f6 = 0) 2, 4, 6, 8, ? , 120, 122, 124 (when f6 = 1) ? 2, ? 4, ? 6, ? 8, ? , ? 120, ? 122, ? 124 the range of value that can be corrected by using the watch error correction register (subcud) is shown below. dev = 0 (correction every 20 seconds) dev = 1 (correction every 60 seconds) correctable range ? 189.2 ppm to 189.2 ppm ? 63.1 ppm to 63.1 ppm maximum excludes quantization error 1.53 ppm 0.51 ppm minimum resolution 3.05 ppm 1.02 ppm remark if a correctable range is ? 63.1 ppm or lower and 63.1 ppm or higher, set 0 to dev.
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 359 jun 20, 2011 (14) alarm minute register (alarmwm) this register is used to set minutes of alarm. alarmwm can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. caution set a decimal value of 00 to 59 to this register in bcd code. if a value outside the range is set, the alarm is not detected. figure 7-15. format of ala rm minute register (alarmwm) address: fff9ah after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 alarmwm 0 wm40 wm20 wm10 wm8 wm4 wm2 wm1 (15) alarm hour register (alarmwh) this register is used to set hours of alarm. alarmwh can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 12h. however, the value of this register is 00h if the ampm bit (bit 3 of the rtcc0 regist er) is set to 1 after reset. caution set a decimal value of 00 to 23, or 01 to 12 and 21 to 32 to this register in bcd code. if a value outside the range is set, the alarm is not detected. figure 7-16. format of alarm hour register (alarmwh) address: fff9bh after reset: 12h r/w symbol 7 6 5 4 3 2 1 0 alarmwh 0 0 wh20 wh10 wh8 wh4 wh2 wh1 caution bit 5 (wh20) of alarmwh i ndicates am(0)/pm(1) if ampm = 0 (if the 12-hour system is selected).
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 360 jun 20, 2011 (16) alarm week register (alarmww) this register is used to set date of alarm. alarmww can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 7-17. format of alarm week register (alarmww) address: fff9ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 alarmww 0 ww6 ww5 ww4 ww3 ww2 ww1 ww0 here is an example of setting the alarm. day 12-hour display 24-hour display time of alarm sunday w w 0 monday w w 1 tuesday w w 2 wednesday w w 3 thursday w w 4 friday w w 5 saturday w w 6 hour 10 hour 1 minute 10 minute 1 hour 10 hour 1 minute 10 minute 1 every day, 0:00 a.m. 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 every day, 1:30 a.m. 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 every day, 11:59 a.m. 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 monday through friday, 0:00 p.m. 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 sunday, 1:30 p.m. 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 monday, wednesday, friday, 11:59 p.m. 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 361 jun 20, 2011 (17) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p30/rtc1hz/to00/ti03/intp1 pin for real-time counter correction clock output, the p31/rtcdiv/rtccl/ti00/to03/pclbuz1/intp2 pin for real -time counter clock output, set pm30, pm31 and the output latches of p30, p31 to 0. pm3 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generati on sets pm3 to ffh. figure 7-18. format of port mode register 3 (pm3) ? 78k0r/lf3 address: fff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 1 pm33 pm32 pm31 pm30 ? 78k0r/lg3, 78k0r/lh3 address: fff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 pm34 pm33 pm32 pm31 pm30 pm3n p3n pin i/o mode selection (n = 0 to 4) 0 output mode (output buffer on) 1 input mode (output buffer off)
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 362 jun 20, 2011 7.4 real-time counter operation 7.4.1 starting operation of real-time counter figure 7-19. procedure for starting operation of real-time counter setting ampm, ct2 to ct0 setting min rtce = 0 setting sec (clearing rsubc) start intrtc = 1? stops counter operation. selects 12-/24-hour system and interrupt (intrtc). sets second count register. sets minute count register. no yes setting hour sets hour count register. setting week sets week count register. setting day sets day count register. setting month sets month count register. setting year sets year count register. clearing if flags of interrupt clears interrupt request flags (rtcif, rtciif). clearing mk flags of interrupt clears interrupt mask flags (rtcmk, rtcimk). rtce = 1 note2 starts counter operation. reading counter rtcen = 1 note1 supplies input clock. notes 1. first set rtcen to 1, while o scillation of the subsystem clock (f sub ) is stable. 2. confirm the procedure described in 7.4.2 shifting to stop mode after starting operation when shifting to stop mode without waiting for intrtc = 1 after rtce = 1.
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 363 jun 20, 2011 yes rtce = 1 rwait = 1 no yes rwait = 0 no rwst = 1 ? rwst = 0 ? stop mode rtce = 1 stop mode waiting at least for 2 f sub clocks sets to counter operation start shifts to stop mode sets to counter operation start sets to stop the sec to year counters, reads the counter value, write mode checks the counter wait status sets the counter operation shifts to stop mode example 2 example 1 7.4.2 shifting to stop mode after starting operation perform one of the following processing when shifting to stop mode immediately after setting rtce to 1. however, after setting rtce to 1, this processing is not required when shifting to stop mode after the first intrtc interrupt has occurred. ? shifting to stop mode when at least two subsystem clocks (f sub ) (about 62 s) have elapsed after setting rtce to 1 (see figure 7-20 , example 1 ). ? checking by polling rwst to become 1, after setting rtce to 1 and then setting rwait to 1. afterward, setting rwait to 0 and shifting to stop mode after che cking again by polling that rwst has become 0 (see figure 7-20 , example 2 ). figure 7-20. procedure for shifting to stop mode after setting rtce to 1
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 364 jun 20, 2011 7.4.3 reading/writing real-time counter read or write the counter after setting 1 to rwait first. figure 7-21. procedure for reading real-time counter reading min rwait = 1 reading sec start rwst = 1? stops sec to year counters. mode to read and write count values reads second count register. reads minute count register. no yes reading hour reads hour count register. reading week reads week count register. reading day reads day count register. reading month reads month count register. reading year reads year count register. rwait = 0 rwst = 0? note no yes sets counter operation. checks wait status of counter. end note be sure to confirm that rwst = 0 before setting stop mode. caution complete the series of opera tions of setting rwait to 1 to cl earing rwait to 0 within 1 second. remark sec, min, hour, week, day, month, and year may be read in any sequence. all the registers do not have to be set and only some registers may be read.
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 365 jun 20, 2011 figure 7-22. procedure for writing real-time counter writing min rwait = 1 writing sec start rwst = 1? stops sec to year counters. mode to read and write count values no yes writing hour writing week writing day writing month writing year rwait = 0 rwst = 0? note no yes sets counter operation. checks wait status of counter. end writes second count register. writes minute count register. writes hour count register. writes week count register. writes day count register. writes month count register. writes year count register. note be sure to confirm that rwst = 0 before setting stop mode. caution complete the series of opera tions of setting rwait to 1 to cl earing rwait to 0 within 1 second. remark sec, min, hour, week, day, month, a nd year may be written in any sequence. all the registers do not have to be set an d only some registers may be written.
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 366 jun 20, 2011 7.4.4 setting alarm of real-time counter set time of alarm after setting 0 to wale first. figure 7-23. alarm setting procedure wale = 0 setting alarmwm start intrtc = 1? match operation of alarm is invalid. sets alarm minute register. alarm processing yes walie = 1 interrupt is generated when alarm matches. setting alarmwh sets alarm hour register. setting alarmww sets alarm week register. wale = 1 match operation of alarm is valid. wafg = 1? no yes constant-period interrupt servicing match detection of alarm no remarks 1. alarmwm, alarmwh, and alarmww may be written in any sequence. 2. fixed-cycle interrupts and alarm match interrupts us e the same interrupt source (intrtc). when using these two types of interrupts at the same time, wh ich interrupt occurred can be judged by checking the fixed-cycle interrupt status flag (rifg) and the alarm detection status flag (wafg) upon intrtc occurrence.
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 367 jun 20, 2011 7.4.5 1 hz output of real-time counter figure 7-24. 1 hz output setting procedure rcloe1 = 1 rtce = 0 rtce = 1 enables output of rtc1hz pin (1 hz). start output start from rtc1hz pin stops counter operation. starts counter operation. 7.4.6 32.768 khz output of real-time counter figure 7-25. 32.768 khz output setting procedure rcloe0 = 1 rtce = 0 rtce = 1 start 32.768 khz output start from rtccl pin stops counter operation. enables output of rtccl pin (32.768 khz). starts counter operation.
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 368 jun 20, 2011 7.4.7 512 hz or 16.384 khz output of real-time counter figure 7-26. 512 hz or 16.384 khz output setting procedure rtce = 0 rtce = 1 start stops counter operation. rcloe2 = 1 output of rtcdiv pin is enabled. 512 hz output: rckdiv = 0 16.384 khz output: rckdiv = 1 selects output frequency of rtcdiv pin. starts counter operation. 512 hz or 16.384 khz output start from rtcdiv pin
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 369 jun 20, 2011 7.4.8 example of watch error correction of real-time counter the watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction register. example of calculating the correction value the correction value used when correctin g the count value of the sub-count register (rsubc) is calculated by using the following expression. set dev to 0 when the correction range is ? 63.1 ppm or less, or 63.1 ppm or more. (when dev = 0) correction value note = number of correction counts in 1 minute 3 = (oscillation frequency target frequency ? 1) 32768 60 3 (when dev = 1) correction value note = number of correction counts in 1 minute = (oscillation frequency target frequency ? 1) 32768 60 note the correction value is the watch error correction value calculated by using bits 6 to 0 of the watch error correction regist er (subcud). (when f6 = 0) correction value = {(f5, f4, f3, f2, f1, f0) ? 1} 2 (when f6 = 1) correction value = ? {(/f5, /f4, /f3, /f 2, /f1, /f0) + 1} 2 when (f6, f5, f4, f3, f2, f1, f0) is (*, 0, 0, 0, 0, 0, *), watch error correct ion is not performed. ?*? is 0 or 1. /f5 to /f0 are bit-inverted values (000011 when 111100). remarks 1. the correction value is 2, 4, 6, 8, ? 120, 122, 124 or ? 2, ? 4, ? 6, ? 8, ? ? 120, ? 122, ? 124. 2. the oscillation frequency is the subsystem clock (f sub ). it can be calculated from the 32.768 khz output frequen cy of the rtccl pin or the output frequency of the rtc1hz pin 32768 when the watch error correction register is set to its initial value (00h). 3. the target frequency is the frequency resulting after correction performed by using the watch error correction register.
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 370 jun 20, 2011 correction example <1> example of correcting from 32772.3 hz to 32768 hz (32772.3 hz ? 131.2 ppm) [measuring the oscillation frequency] the oscillation frequency note of each product is measured by outputti ng about 32 khz from the rtccl pin or outputting about 1 hz from the rtc1hz pin when the watch erro r correction register is set to its initial value (00h). note see 7.4.5 1 hz output of real-time counter for the setting procedure of outputti ng about 1 hz from the rtc1hz pin, and 7.4.6 32.768 khz output of real-time counter for the setting procedure of outputting about 32 khz from the rtccl pin. [calculating the correction value] (when the output frequency from t he rtccl pin is 32772.3 hz) if the target frequency is assumed to be 32768 hz (32772.3 hz ? 131.2 ppm), the correction range for ? 131.2 ppm is ? 63.1 ppm or less, so assume dev to be 0. the expression for calculating the correct ion value when dev is 0 is applied. correction value = number of correction counts in 1 minute 3 = (oscillation frequency target frequency ? 1) 32768 60 3 = (32772.3 32768 ? 1) 32768 60 3 = 86 [calculating the values to be set to (f6 to f0)] (when the correction value is 86) if the correction value is 0 or more (w hen delaying), assume f6 to be 0. calculate (f5, f4, f3, f2, f1, f0) from the correction value. {(f5, f4, f3, f2, f1, f0) ? 1} 2 = 86 (f5, f4, f3, f2, f1, f0) = 44 (f5, f4, f3, f2, f1, f0) = (1, 0, 1, 1, 0, 0) consequently, when correcting from 32772.3 hz to 32768 hz (32772.3 hz ? 131.2 ppm), setting the correction register such that dev is 0 and the correction value is 86 (bits 6 to 0 of subcud: 0101100) results in 32768 hz (0 ppm). figure 7-27 shows the operation when (dev, f6, f5, f4, f3, f2, f1, f0) is (0, 0, 1, 0, 1, 1, 0, 0).
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 371 jun 20, 2011 figure 7-27. operation when (dev, f6, f5, f4, f3 , f2, f1, f0) = (0, 0, 1, 0, 1, 1, 0, 0) rsubc count value sec 00 01 8055h 0000h 0001h 7fffh 0000h 8054h 40 8055h 0000h 8054h 8055h 0000h 8054h 19 0000h 0001h 7fffh 20 39 0000h 0001h 7fffh 0000h 0001h 7fffh 59 00 8055h 0000h 8054h 7fffh + 56h (86) 7fffh + 56h (86) 7fffh + 56h (86) 7fffh+56h (86) count start
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 372 jun 20, 2011 correction example <2> example of correcting from 32767.4 hz to 32768 hz (32767.4 hz + 18.3 ppm) [measuring the oscillation frequency] the oscillation frequency note of each product is measured by outputti ng about 32 khz from the rtccl pin or outputting about 1 hz from the rtc1hz pin when the watch erro r correction register is set to its initial value (00h). note see 7.4.5 1 hz output of real-time counter for the setting procedure of outputti ng about 1 hz from the rtc1hz pin, and 7.4.6 32.768 khz output of real-time counter for the setting procedure of outputting about 32 khz from the rtccl pin. [calculating the correction value] (when the output frequency from the rtc1hz pin is 0.9999817 hz) oscillation frequency = 32768 0.9999817 32767.4 hz assume the target frequency to be 32768 hz (32767.4 hz + 18.3 ppm) and dev to be 1. the expression for calculating the correct ion value when dev is 1 is applied. correction value = number of correction counts in 1 minute = (oscillation frequency target frequency ? 1) 32768 60 = (32767.4 32768 ? 1) 32768 60 = ? 36 [calculating the values to be set to (f6 to f0)] (when the correction value is ? 36) if the correction value is 0 or less (when speeding up), assume f6 to be 1. calculate (f5, f4, f3, f2, f1, f0) from the correction value. ? {(/f5, /f4, /f3, /f2, /f1, /f0) + 1} 2 = ? 36 (/f5, /f4, /f3, /f2, /f1, /f0) = 17 (/f5, /f4, /f3, /f2, /f1, /f0) = (0, 1, 0, 0, 0, 1) (f5, f4, f3, f2, f1, f0) = (1, 0, 1, 1, 1, 0) consequently, when correcting from 32767.4 hz to 32768 hz (32767.4 hz + 18.3 ppm), setting the correction register such that dev is 1 and the correction value is ? 36 (bits 6 to 0 of subcud: 1101110) results in 32768 hz (0 ppm). figure 7-28 shows the operation when (dev, f6, f5, f4, f3, f2, f1, f0) is (1, 1, 1, 0, 1, 1, 1, 0).
78k0r/lx3 chapter 7 real-time counter r01uh0004ej0501 rev.5.01 373 jun 20, 2011 figure 7-28. operation when (dev, f6, f5, f4, f3 , f2, f1, f0) = (1, 1, 1, 0, 1, 1, 1, 0) rsubc count value sec 00 01 7fdbh 0000h 0001h 7fffh 0000h 7fdah 40 19 0000h 0001h 7fffh 0000h 0001h 7fffh 20 39 0000h 0001h 7fffh 0000h 0001h 7fffh 0000h 0001h 7fffh 59 00 7fdbh 0000h 7fdah 7fffh ? 24h (36) 7fffh ? 24h (36) count start
78k0r/lx3 chapter 8 watchdog timer r01uh0004ej0501 rev.5.01 374 jun 20, 2011 chapter 8 watchdog timer 8.1 functions of watchdog timer the watchdog timer is mounted onto all 78k0r/lx3 microcontroller products. the watchdog timer operates on the internal low-speed oscillation clock. the watchdog timer is used to detect an inadvertent program l oop. if a program loop is detected, an internal reset signal is generated. program loop is detected in the following cases. ? if the watchdog timer counter overflows ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte ? if data is written to wdte during a window close period when a reset occurs due to the watchdog timer, bit 4 (wdrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 22 reset function . when 75% of the overflow time is reached, an interval interrupt can be generated.
78k0r/lx3 chapter 8 watchdog timer r01uh0004ej0501 rev.5.01 375 jun 20, 2011 8.2 configuration of watchdog timer the watchdog timer includes the following hardware. table 8-1. configuration of watchdog timer item configuration control register watchdog timer enable register (wdte) how the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option byte. table 8-2. setting of option bytes and watchdog timer setting of watchdog timer option byte (000c0h) watchdog timer interval interrupt bit 7 (wdtint) window open period bits 6 and 5 (window1, window0) controlling counter operation of watchdog timer bit 4 (wdton) overflow time of watchdog timer bits 3 to 1 (wdcs2 to wdcs0) controlling counter operation of watchdog timer (in halt/stop mode) bit 0 (wdstbyon) remark for the option byte, see chapter 26 option byte . figure 8-1. block diagram of watchdog timer f il wdton of option byte (000c0h) wdtint of option byte (000c0h) interval time controller (count value overflow time 3/4) interval time interrupt wdcs2 to wdcs0 of option byte (000c0h) clock input controller 20-bit counter selector overflow signal reset output controller internal reset signal count clear signal window size decision signal window size check watchdog timer enable register (wdte) write detector to wdte except ach internal bus window1 and window0 of option byte (000c0h) f il /2 7 to f il /2 17
78k0r/lx3 chapter 8 watchdog timer r01uh0004ej0501 rev.5.01 376 jun 20, 2011 8.3 register controlling watchdog timer the watchdog timer is controlled by the watchdog timer enable register (wdte). (1) watchdog timer enable register (wdte) writing ?ach? to wdte clears the watchdog timer counter and starts counting again. this register can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 9ah or 1ah note . figure 8-2. format of watchdog timer enable register (wdte) 0 1 2 3 4 5 6 7 symbol wdte address: fffabh after reset: 9ah/1ah note r/w note the wdte reset value differs depending on the wdto n setting value of the option byte (000c0h). to operate watchdog timer, set wdton to 1. wdton setting value wdte reset value 0 (watchdog timer count operation disabled) 1ah 1 (watchdog timer count operation enabled) 9ah cautions 1. if a value other than ?ach? is writte n to wdte, an internal r eset signal is generated. 2. if a 1-bit memory manipulation instruction is executed for wdte, an internal reset signal is generated. 3. the value read from wdte is 9ah/1ah (this differs fr om the written value (ach)).
78k0r/lx3 chapter 8 watchdog timer r01uh0004ej0501 rev.5.01 377 jun 20, 2011 8.4 operation of watchdog timer 8.4.1 controlling operation of watchdog timer 1. when the watchdog timer is used, its operati on is specified by the option byte (000c0h). ? enable counting operation of the watchdog timer by setti ng bit 4 (wdton) of the option byte (000c0h) to 1 (the counter starts operating after a re set release) (for details, see chapter 26 ). wdton watchdog timer counter 0 counter operation disabled (counting stopped after reset) 1 counter operation enabled (counting started after reset) ? set an overflow time by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (000c0h) (for details, see 8.4.2 and chapter 26 ). ? set a window open period by using bits 6 and 5 (wi ndow1 and window0) of the option byte (000c0h) (for details, see 8.4.3 and chapter 26 ). 2. after a reset release, the watchdog timer starts counting. 3. by writing ?ach? to wdte after the watchdog timer star ts counting and before the overflow time set by the option byte, the watchdog timer is cleared and starts counting again. 4. after that, write wdte the second time or later a fter a reset release during the window open period. if wdte is written during a window close period, an internal reset signal is generated. 5. if the overflow time expires without ?ach? wri tten to wdte, an internal reset signal is generated. an internal reset signal is generated in the following cases. ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte cautions 1. when data is written to wdte for the first time after reset release, the wa tchdog timer is cleared in any timing regardless of the window open ti me, as long as the register is written before the overflow time, and the watchdog timer starts counting again. 2. if the watchdog timer is cleared by writi ng ?ach? to wdte, the actual overflow time may be different from the overflow time set by the option byte by up to 2/f il seconds. 3. the watchdog timer can be cleared imme diately before the c ount value overflows. when the overflow time is set to 2 10 /f il , writing ?ach? is valid up to count value 3fh.
78k0r/lx3 chapter 8 watchdog timer r01uh0004ej0501 rev.5.01 378 jun 20, 2011 cautions 4. the operation of th e watchdog timer in the halt and stop modes differs as follows depending on the set value of bit 0 (wdstbyon) of the option byte (000c0h). wdstbyon = 0 wdstbyon = 1 in halt mode in stop mode watchdog timer operation stops. watchdog timer operation continues. if wdstbyon = 0, the watchdog timer resum es counting after the halt or stop mode is released. at this time, the counter is cleared to 0 and counting starts. when operating with th e x1 oscillation clock after releasi ng the stop mode, the cpu starts operating after the oscillation stabilization time has elapsed. therefore, if the period be tween the stop mode release and the watchdog timer overflow is short, an overflow occurs during the oscilla tion stabilization time, causing a reset. consequently, set the overfl ow time in consideration of the oscillation stabilization time when operating with the x1 oscillation clock and when the watchdog timer is to be cleared after the stop mode release by an interval interrupt. 5. the watchdog timer continues its operati on during self-programming of the flash memory and eeprom tm emulation. during processing, the interr upt acknowledge time is delayed. set the overflow time and window size taki ng this delay into consideration. 8.4.2 setting overflow time of watchdog timer set the overflow time of the watchdog timer by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (000c0h). if an overflow occurs, an internal reset signal is generated. the present count is cleared and the watchdog timer starts counting again by writing ?ach? to wdte during the window open period before the overflow time. the following overflow time is set. table 8-3. setting of overflow time of watchdog timer wdcs2 wdcs1 wdcs0 overflow time of watchdog timer (f il = 33 khz (max.)) 0 0 0 2 7 /f il (3.88 ms) 0 0 1 2 8 /f il (7.76 ms) 0 1 0 2 9 /f il (15.52 ms) 0 1 1 2 10 /f il (31.03 ms) 1 0 0 2 12 /f il (124.12 ms) 1 0 1 2 14 /f il (496.48 ms) 1 1 0 2 15 /f il (992.97 ms) 1 1 1 2 17 /f il (3971.88 ms) caution the watchdog timer conti nues its operation during self-program ming of the flash memory and eeprom emulation. during processi ng, the interrupt acknowledge time is delayed. set the overflow time and window size taking th is delay into consideration. remark f il : internal low-speed oscillation clock frequency
78k0r/lx3 chapter 8 watchdog timer r01uh0004ej0501 rev.5.01 379 jun 20, 2011 8.4.3 setting window open period of watchdog timer set the window open period of the watchdog timer by usi ng bits 6 and 5 (window1, wi ndow0) of the option byte (000c0h). the outline of the window is as follows. ? if ?ach? is written to wdte during the window open period, the watchdog timer is cleared and starts counting again. ? even if ?ach? is written to wdte during the window clos e period, an abnormality is detected and an internal reset signal is generated. example : if the window open period is 50% window close period (50%) window close period (50%) counting starts overflow time counting starts again when "ach" is written to wdte. internal reset signal is generated if "ach" is written to wdte. caution when data is written to wdte for the first time after reset release, the watchdog timer is cleared in any timing regardless of the window open time, as long as the register is written before the overflow time, and the watchdog timer starts counting again. the window open period to be set is as follows. table 8-4. setting window op en period of watchdog timer window1 window0 window open period of watchdog timer 0 0 setting prohibited 0 1 50% 1 0 75% 1 1 100% cautions 1. the watchdog timer continues its ope ration during self-programming of the flash memory and eeprom emulation. during pro cessing, the interrupt acknowledge time is delayed. set the overflow time and window size taki ng this delay into consideration. 2. when bit 0 (wdstbyon) of the option byte (000c0h) = 0, the window open period is 100% regardless of the values of window1 and window0.
78k0r/lx3 chapter 8 watchdog timer r01uh0004ej0501 rev.5.01 380 jun 20, 2011 remark if the overflow time is set to 2 10 /f il , the window close time and open time are as follows. (2.7 v v dd 5.5 v) setting of window open period 50% 75% 100% window close time 0 to 18.96 ms 0 to 9.48 ms none window open time 18.96 to 31.03 ms 9.48 to 31.03 ms 0 to 31.03 ms ? overflow time: 2 10 /f il (max.) = 2 10 /33 khz (max.) = 31.03 ms ? window close time: 0 to 2 10 /f il (min.) (1 ? 0.5) = 0 to 2 10 /27 khz (min.) 0.5 = 0 to 18.96 ms ? window open time: 2 10 /f il (min.) (1 ? 0.5) to 2 10 /f il (max.) = 2 10 /27 khz (min.) 0.5 to 2 10 /33 khz (max.) = 18.96 to 31.03 ms 8.4.4 setting watchdog time r interval interrupt depending on the setting of bit 7 (wdtint) of an option byte (000c0h), an interval interrupt (intwdti) can be generated when 75% of the overflow time is reached. table 8-5. setting of watch dog timer interval interrupt wdtint use of watchdog timer interval interrupt 0 interval interrupt is used. 1 interval interrupt is generated when 75% of overflow time is reached. caution when operating with the x1 oscillation cl ock after releasing the stop mode, the cpu starts operating after the oscillation stabilization time has elapsed. therefore, if the period between th e stop mode release and the watc hdog timer overflow is short, an overflow occurs during the oscillati on stabilization time, causing a reset. consequently, set the overflow time in consider ation of the oscillation stabilization time when operating with the x1 oscillation clock and when th e watchdog timer is to be cleared after the stop mode release by an interval interrupt. remark the watchdog timer continues counting even after intw dti is generated (until ach is written to the wdte register). if ach is not written to the wdte register before the overflow time, an internal reset signal is generated.
78k0r/lx3 chapter 9 clock output/buzzer output controller r01uh0004ej0501 rev.5.01 381 jun 20, 2011 chapter 9 clock output/buzzer output controller 9.1 functions of clock output/buzzer output controller the clock output/buzzer output controller is mounted onto all 78k0r/ lx3 microcontroller products. the clock output controller is intended for carrier outpu t during remote controlled transmission and clock output for supply to peripheral ics. buzzer output is a function to output a square wave of buzzer frequency. one pin can be used to output a clock or buzzer sound. two output pins, pclbuz0 and pclbuz1, are available. pclbuz0 outputs a clock selected by cl ock output select register 0 (cks0). pclbuz1 outputs a clock selected by cl ock output select register 1 (cks1). figure 9-1 shows the block diagram of clock output/buzzer output controller. figure 9-1. block diagram of clo ck output/buzzer output controller f main f sub pcloe0 0 0 0 pcloe0 5 3 pclbuz0 note /p32/ ti01/to01/intp5 pclbuz1 note /p31/ ti00/to03/rtcdiv/ rtccl/intp2 csel0 ccs02 ccs01 ccs00 pm31 pcloe1 0 0 0 csel1 ccs12 ccs11 ccs10 8 pcloe1 8 f main /2 11 to f main /2 13 clock/buzzer controller internal bus clock output select register 1 (cks1) prescaler prescaler selector selector clock/buzzer controller output latch (p31) internal bus clock output select register 0 (cks0) output latch (p32) f main /2 11 to f main /2 13 f main to f main /2 4 f main to f main /2 4 f sub to f sub /2 7 f sub to f sub /2 7 pm32 note the pclbuz0 and pclbuz1 pins can out put a clock of up to 10 mhz at 2.7 v v dd . setting a clock exceeding 5 mhz at v dd < 2.7 v is prohibited.
78k0r/lx3 chapter 9 clock output/buzzer output controller r01uh0004ej0501 rev.5.01 382 jun 20, 2011 9.2 configuration of clock output/buzzer output controller the clock output/buzzer output controller includes the following hardware. table 9-1. configuration of clock output/buzzer output controller item configuration control registers clock output select registers 0, 1 (cks0, cks1) port mode register 3 (pm3) port register 3 (p3) 9.3 registers controlling clock ou tput/buzzer output controller the following two registers are used to control the clock output/buzzer output controller. ? clock output select registers 0, 1 (cks0, csk1) ? port mode register 3 (pm3) (1) clock output select regi sters 0, 1 (cks0, cks1) these registers set output enable/disable for clo ck output or for the buzzer frequency output pin (pclbuz0/pclbuz1), and set the output clock. select the clock to be output from pclbuz0 by using cks0. select the clock to be output from pclbuz1 by using cks1. cks0 and cks1 are set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h.
78k0r/lx3 chapter 9 clock output/buzzer output controller r01uh0004ej0501 rev.5.01 383 jun 20, 2011 figure 9-2. format of clock output select register n (cksn) address: fffa5h (cks0), fffa6h (cks1) after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 cksn pcloen 0 0 0 cseln ccsn2 ccsn1 ccsn0 pcloen pclbuzn output enabl e/disable specification 0 output disable (default) 1 output enable pclbuzn output clock selection cseln ccsn2 ccsn1 ccsn0 f main = 5 mhz f main = 10 mhz f main = 20 mhz 0 0 0 0 f main 5 mhz 10 mhz note setting prohibited note 0 0 0 1 f main /2 2.5 mhz 5 mhz 10 mhz note 0 0 1 0 f main /2 2 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f main /2 3 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f main /2 4 312.5 khz 625 khz 1.25 mhz 0 1 0 1 f main /2 11 2.44 khz 4.88 khz 9.76 khz 0 1 1 0 f main /2 12 1.22 khz 2.44 khz 4.88 khz 0 1 1 1 f main /2 13 610 hz 1.22 khz 2.44 khz 1 0 0 0 f sub 32.768 khz 1 0 0 1 f sub /2 16.384 khz 1 0 1 0 f sub /2 2 8.192 khz 1 0 1 1 f sub /2 3 4.096 khz 1 1 0 0 f sub /2 4 2.048 khz 1 1 0 1 f sub /2 5 1.024 khz 1 1 1 0 f sub /2 6 512 hz 1 1 1 1 f sub /2 7 256 hz note setting an output clock exceeding 10 mhz is prohibited when 2.7 v v dd . setting a clock exceeding 5 mhz at v dd < 2.7 v is also prohibited. cautions 1. change the output clock after disabling clock output (pcloen = 0). 2. if the selected clock (f main or f sub ) stops during clock output (pcloen = 1), the output becomes undefined. 3. to shift to stop mode when the main system clock is selected (cseln = 0), set pcloen = 0 before executing the stop instru ction. when the subsystem clock is selected (cseln = 1), pcloen = 1 can be set because the cl ock can be output in stop mode. remarks 1. n = 0, 1 2. f main : main system clock frequency 3. f sub : subsystem clock frequency
78k0r/lx3 chapter 9 clock output/buzzer output controller r01uh0004ej0501 rev.5.01 384 jun 20, 2011 (2) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p31/pclbuz1/ti00/ to03/rtcdiv/rtccl/intp2 and p32/pclb uz0/ti01/to01/intp5 pins for clock output/buzzer output, clear pm31 and pm32 and the output latches of p32 and p31 to 0. pm3 is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 9-3. format of port mode register 3 (pm3) address: fff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 pm34 pm33 pm32 pm31 pm30 pm3n p3n pin i/o mode selection (n = 0 to 4) 0 output mode (output buffer on) 1 input mode (output buffer off) 9.4 operations of clock output/buzzer output controller one pin can be used to output a clock or buzzer sound. two output pins, pclbuz0 and pclbuz1, are available. pclbuz0 outputs a clock/buzzer selected by clock output select register 0 (cks0). pclbuz1 outputs a clock/buzzer selected by clock output select register 1 (cks1). 9.4.1 operation as output pin pclbuzn is output as the following procedure. <1> select the output frequency with bits 0 to 3 (ccsn0 to cc sn2, cseln) of the clock out put select register (cksn) of the pclbuzn pin (output in disabled status). <2> set bit 7 (pcloen) of cksn to 1 to enable clock/buzzer output. remark the controller used for outputting t he clock starts or stops outputting the clock one clock after enabling or disabling clock output (pcloen) is switched. at this time, pulses with a narrow width are not output. figure 9-4 shows enabling or stopping output using pclo en and the timing of outputting the clock. figure 9-4. remote control output application example pcloen 1 clock elapsed narrow pulses are not recognized clock output remark n = 0, 1
78k0r/lx3 r01uh0004ej0501 rev.5.01 385 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) pd78f150xa pd78f151xa item 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) 78k0r/lf3 (80 pins) 78k0r/lg3 (100 pins) 78k0r/lh3 (128 pins) a/d converter 8 ch 12 ch 8 ch 12 ch resolution 12 bits 10 bits 10.1 function of a/d converter the a/d converter is a 12-bit resolution or 10-bit resolution c onverter that converts analog input signals into digital values, and consists of up to twelve channels of a/d converter analog inputs (ani0 to ani10, ani15). ani1, ani4, and ani7 are alternatively used with operati onal amplifier 0, 1, and 2 outputs (amp0o, amp1o, and amp2o) as pin functions. accordingly, operational amplifier outputs can be used as analog input sources. the following four a/d converter operation modes are available. ? software trigger mode (continuous conversion mode) ? software trigger mode (single conversion mode) ? timer trigger mode (continuous conversion mode) ? timer trigger mode (single conversion mode)
78k0r/lx3 r01uh0004ej0501 rev.5.01 386 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) figure 10-1. block diagra m of 12-bit a/d converter ( pd78f150xa) remark 78k0r/lf3: ani0-ani6, ani15 78k0r/lg3, 78k0r/lh3: ani0-ani10, ani15 intad adcs adscm fr2 fr1 adce fr0 av ss 4 lv1 lv0 5 adpc3 adpc2 adpc1 adpc0 5 adpc4 ads3 ads2 ads1 ads0 2 adtmd adtrs ani0/amp0-/p20 ani1/amp0o/p21 ani2/amp0+/p22 ani3/amp1-/p23 ani4/amp1o/p24 ani5/amp1+/p25 ani6/amp2-/p26 ani7/amp2o/p27 ani8/amp2+/p150 ani9/p151 ani10/p152 ani15/av refm /p157 av refp /v refout av ss adcs bit adref bit ad refm ad refp av refm / ani15/p157 vrsel bit vron, vrgv bit av dd0 adref vrgv vron tap selector series resistor string a/d voltage comparator successive approximation register (sar) controller timer trigger 0, 1 selector sample & hold circuit a/d conversion result register (adcr) a/d converter mode register (adm) analog reference voltage control register (advrc) internal bus analog input channel specification register (ads) a/d port configuration register (adpc) a/d converter mode register1 (adm1) selector voltage reference circuit
78k0r/lx3 r01uh0004ej0501 rev.5.01 387 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) figure 10-2. block diagram of 10-bit a/d converter ( pd78f151xa) intad adcs adscm fr2 fr1 adce fr0 av ss 4 lv1 lv0 5 adpc3 adpc2 adpc1 adpc0 5 adpc4 ads3 ads2 ads1 ads0 2 adtmd adtrs ani0/amp0-/p20 ani1/amp0o/p21 ani2/amp0+/p22 ani3/amp1-/p23 ani4/amp1o/p24 ani5/amp1+/p25 ani6/amp2-/p26 ani7/amp2o/p27 ani8/amp2+/p150 ani9/p151 ani10/p152 ani15/av refm /p157 av refp /v refout av ss adcs bit adref bit ad refm ad refp av refm / ani15/p157 vrsel bit vron, vrgv bit av dd0 vrgv tap selector series resistor string a/d voltage comparator successive approximation register (sar) controller timer trigger 0, 1 selector sample & hold circuit a/d conversion result register (adcr) a/d converter mode register (adm) analog reference voltage control register (advrc) internal bus analog input channel specification register (ads) a/d port configuration register (adpc) a/d converter mode register1 (adm1) selector voltage reference circuit r emarks 78k0r/lf3: ani0-ani6, ani15 78k0r/lg3, 78k0r/lh3: ani0-ani10, ani15
78k0r/lx3 r01uh0004ej0501 rev.5.01 388 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) 10.2 configuration of a/d converter the a/d converter includes the following hardware. (1) ani0 to ani10, ani15 pins these are the analog input pins of the a/d converter. they input analog signals to be converted into digital signals. pins other than the one selected as the anal og input pin can be used as i/o port pins. remark 78k0r/lf3: ani0-ani6, ani15 78k0r/lg3, 78k0r/lh3: ani0-ani10, ani15 (2) sample & hold circuit the sample & hold circuit samples each of the analog input voltages sequentially sent from the input circuit, and sends them to the a/d voltage comparat or. this circuit also holds the sampled analog input voltage during a/d conversion. (3) series resistor string the series resistor string is connected between ad refp and ad refm , and generates a voltage to be compared with the sampled voltage value. figure 10-3. circuit configuration of series resistor string adcs series resistor string ad refp p-ch ad refm (4) voltage comparator the voltage comparator compares the sampled voltage value and the output volt age of the series resistor string. (5) successive approximation register (sar) this register converts the result of comparison by the voltage comparator, star ting from the most significant bit (msb). when the voltage value is converted into a digital value down to the least significant bit (lsb) (end of a/d conversion), the contents of the sar register are transferred to the a/d conversion result register (adcr).
78k0r/lx3 r01uh0004ej0501 rev.5.01 389 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) (6) 12-bit a/d conversion result register, 10-bi t a/d conversion result register (adcr) the a/d conversion result is loaded from the successive approximation register to this register each time a/d conversion is completed, and the adcr regi ster holds the a/d conversion result in its lower 12 bits (the higher 4 bits are fixed to 0). 10-bit a/d conversion result register does not fix its lower 2 bits. (7) 8-bit a/d conversion result register (adcrh) the a/d conversion result is loaded from the successive approximation register to this register each time a/d conversion is completed, and the adcrh register stores the higher 8 bi ts of the a/d conversion result. (8) controller this circuit controls the conversion time of an input analog si gnal that is to be converted into a digital signal, as well as starting and stopping of the conver sion operation. when a/d conversion has been completed, this controller generates intad. (9) av dd0, av dd pin this pin inputs an analog power to the a/d converter. w hen one or more of the pins of ports 2 and 15 are used as the digital port pins, make av dd0 the same potential as ev dd or v dd . (10) av ss pin this is the ground potential pi n of the a/d converter. always use this pi n at the same potential as that of the v ss pin even when the a/d converter is not used. the ground potential (av ss ) can also be used as the negative reference voltage (ad refm ) of the a/d converter. to use av ss as ad refm , clear the adref bit of the advrc register to 0. (11) av refp /v refout pin this pin is used to externally input the reference voltage (av refp ) of the a/d converter or output the voltage (v refout ) generated by the voltage reference. to use av refp as the positive reference voltage (ad refp ) of the a/d converter, clear the vron bit of the advrc register to 0. to use v refout as ad refp , set the vron bit to 1. the analog signal input to ani0 to ani10, ani15 is conv erted into a digital signal, based on the voltage applied across ad refp and ad refm . (12) av refm pin this pin is used to externally input the reference voltage (av refm ) of the a/d converter. to use av refm as the negative reference voltage (ad refm ) of the a/d converter, set the adre f bit of the advrc register to 1. remark 78k0r/lf3: ani0-ani6, ani15 78k0r/lg3, 78k0r/lh3: ani0-ani10, ani15 (13) av ref pin this pin is used to externally input the reference voltage.
78k0r/lx3 r01uh0004ej0501 rev.5.01 390 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) 10.3 registers used in a/d converter the a/d converter uses t he following ten registers. ? peripheral enable register 0 (per0) ? a/d converter mode register (adm) ? a/d converter mode register 1 (adm1) ? analog reference voltage control register (advrc) ? 12-bit a/d conversion result register (adcr) ( pd78f150xa only) ? 10-bit a/d conversion result register (adcr) ( pd78f151xa only) ? 8-bit a/d conversion result register (adcrh) ? analog input channel specification register (ads) ? a/d port configuration register (adpc) ? port mode registers 2, 15 (pm2, pm15) (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to reduc e the power consumption and noise. when the a/d converter is used, be sure to se t bit 5 (adcen) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 10-4. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> per0 rtcen dacen adcen iicaen note sau1en sau0en tau1en tau0en adcen control of a/d converter, operational amplifier, and voltage reference input clock 0 stops supply of input clock. ? sfr used by the a/d converter, operational amplifier, and voltage reference cannot be written. ? the a/d converter, operational amplifier, and voltage reference is in the reset status. 1 supplies input clock. ? sfr used by the a/d converter can, operational amplifier, and voltage reference can be read/written. note 78k0r/lg3, 78k0r/lh3 only caution when setting the a/d converter, be sure to set adcen to 1 first. if adcen = 0, writing to a control register of the a/d conver ter is ignored, and, even if the re gister is read, only the default value is read.
78k0r/lx3 r01uh0004ej0501 rev.5.01 391 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) (2) a/d converter mode register (adm) this register sets the conversion time for analog inpu t to be a/d converted, and starts/stops conversion. adm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 10-5. format of a/d converter mode register (adm) address: fff30h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 <0> adm adcs adscm fr2 note 1 fr1 note 1 fr0 note 1 lv1 note 1 lv0 note 1 adce adcs a/d conversion operation control notes 2, 3, 4 0 stops conversion operation 1 enables conversion operation adscm a/d conversion operation mode specification 0 continuous conversion mode 1 single conversion mode adce a/d voltage comparator operation control note 4 0 stops a/d voltage comparator operation 1 enables a/d voltage comparator operation notes 1. for details of fr2 to fr0, lv 1, lv0, and a/d conversion, see table 10-2 a/d conversion time selection . 2. when using the a/d converter in timer trigger mode, do not set adcs to 1. (adcs automatically switches to 1 when a timer trigger signal is generated.) ho wever, adcs may be set to 0 to stop a/d conversion. 3. read adcs to determine whether a/ d conversion is under execution. 4. the operation of the a/ d voltage comparator is controlled by adcs and adce, and it takes 1 s from operation start to operation stabilization. th erefore, when adcs is set to 1 after 1 s or more has elapsed from the time adce is set to 1, t he conversion result at that time has priority over the first conversion result. otherwise, ignore data of the first conversion. table 10-1. settings of adcs and adce adcs adce a/d co nversion operation 0 0 stop status (dc power consumption path does not exist) 0 1 conversion waiting mode (a/d voltage co mparator operation, only comparator consumes power) 1 0 setting prohibited 1 1 conversion mode (a/d voltage comparator operation)
78k0r/lx3 r01uh0004ej0501 rev.5.01 392 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) figure 10-6. timing chart when a/ d voltage comparator is used adce a/d voltage comparator adcs conversion operation conversion operation conversion stopped conversion waiting a/d voltage comparator operation note note to stabilize the internal circuit, the time from the rising of the adce bit to the falling of the adcs bit must be 1 s or longer. cautions 1. a/d conversion must be stopped before re writing bits adscm, fr0 to fr2, lv1, and lv0 to values other than th e identical data. 2 when using the a/d con verter in normal mode 2 (lv1 = 0, lv0 = 1) or low voltage mode (lv1 = 1, lv0 = 0), enable the input gate voltage boost circ uit for the a/d converte r by using the analog reference voltage control register (advrc), and then set adce and adcs to 1. after the voltage boost circuit stabilization time (10 s) passes after the input gate voltage boost circuit for the a/d converter has been enab led, set adcs to 1.
78k0r/lx3 r01uh0004ej0501 rev.5.01 393 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) table 10-2. a/d conversion time selection a/d converter mode register (adm) conversion time selection fr2 fr1 fr0 lv1 lv0 mode f clk = 1 mhz f clk = 8 mhz f clk = 10 mhz f clk = 20 mhz conversion clock (f ad ) 0 0 0 240/f clk 30 s 24 s 12 s f clk /12 0 0 1 160/f clk 20 s 16 s 8 s f clk /8 0 1 0 120/f clk 15 s 12 s 6 s f clk /6 0 1 1 100/f clk 12.5 s 10 s 5 s f clk /5 1 0 0 80/f clk 10 s 8 s f clk /4 1 0 1 60/f clk setting prohibited 7.5 s 6 s f clk /3 1 1 0 40/f clk 40 s 5 s f clk /2 1 1 1 0 0 normal mode 1 note 1 20/f clk 20 s setting prohibited setting prohibited setting prohibited f clk 0 0 0 240/f clk 30 s 24 s 12 s f clk /12 0 0 1 160/f clk 20 s 16 s 8 s f clk /8 0 1 0 120/f clk 15 s 12 s 6 s f clk /6 0 1 1 100/f clk 12.5 s 10 s 5 s f clk /5 1 0 0 80/f clk 10 s 8 s f clk /4 1 0 1 60/f clk setting prohibited 7.5 s 6 s f clk /3 1 1 0 40/f clk 40 s 5 s f clk /2 1 1 1 0 1 normal mode 2 note 2 20/f clk 20 s setting prohibited setting prohibited setting prohibited f clk 0 0 0 300/f clk 37.5 s 30 s 15 s note 4 f clk /12 0 0 1 200/f clk 25 s 20 s note 4 10 s note 4 f clk /8 0 1 0 150/f clk 18.8 s note 4 15 s note 4 7.5 s note 4 f clk /6 0 1 1 125/f clk 15.6 s note 4 12.5 s note 4 6.25 s note 4 f clk /5 1 0 0 100/f clk 12.5 s note 4 10 s note 4 f clk /4 1 0 1 75/f clk setting prohibited 9.38 s note 4 7.5 s note 4 f clk /3 1 1 0 50/f clk 50 s 6.25 s note 4 f clk /2 1 1 1 1 0 low voltage mode note 3 25/f clk 25 s setting prohibited setting prohibited setting prohibited f clk other than above setting prohibited notes 1. normal mode 1: 2.7 v av dd0 5.5 v, when operation of the input gate voltage boost circuit for the a/d converter is stopped. 2. normal mode 2: 2.3 v av dd0 5.5 v, when operation of the input gate voltage boost circuit for the a/d converter is operating. 3. low voltage mode: 1.8 v av dd0 5.5 v, when operation of the input gate voltage boost circuit for the a/d converter is operating. 4. when t a = 0 to 50 c and 2.3 v av dd0 3.6 v. caution when using the a/d converter in no rmal mode 2 (lv1 = 0, lv0 = 1) or low voltage mode (lv1 = 1, lv0 = 0), enable the input gate voltage boost circuit fo r the a/d converter by us ing the analog reference voltage control register (advrc), and then set adce and adcs to 1. after the voltage boost circuit stabilization time (10 s) passes after the input gate voltage boost circuit for the a/d converter has been enabled, set adcs to 1. remark f clk : cpu/peripheral hardware clock frequency
78k0r/lx3 r01uh0004ej0501 rev.5.01 394 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) figure 10-7. a/d converter sa mpling and a/d conversion timing adcs wait period conversion time conversion time sampling sampling timing intad adcs 1 or ads rewrite sampling sar clear sar clear transfer to adcr, intad generation successive conversion (3) a/d converter mode register 1 (adm1) this register sets the a/d conversion start trigger. adm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 10-8. format of a/d con verter mode register 1 (adm1) address: fff32h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 adm1 adtmd 0 0 0 0 0 0 adtrs adtmd a/d trigger mode selection 0 software trigger mode 1 timer trigger mode (hardware trigger mode) adtrs timer trigger signal selection 0 inttm02 1 inttm03 caution rewriting adm1 during a/d conversion is prohi bited. rewrite it when conversion operation is stopped (adcs = 0).
78k0r/lx3 r01uh0004ej0501 rev.5.01 395 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) (4) analog reference voltage control register (advrc) this register is used to select the reference voltage supplies of the a/d and d/a converters , control the operation of the input gate voltage boost circuit for the a/d converter, and control the voltage reference (vr) operation. the electrical specifications of the a/d converter can be maintained even during low-voltage operation thanks to the operation of the input gate voltage boos t circuit for the a/d converter. advrc can be set by a 1-bit or 8-bi t memory manipulation instruction. reset signal generation clears this register to 00h. figure 10-9. format of analog referen ce voltage control register (advrc) address: fff36h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 advrc adref note 0 0 0 vrsel note 0 vrgv note vron note adref note negative reference voltage supply selection of a/d converter selection 0 av ss 1 av refm (external voltage reference input) vrsel note vrgv vron note positive reference voltage supplies selection of a/d and d/a converters operation control of voltage reference output voltage selection of voltage reference operation control of input gate voltage boost circuit for a/d converter relationship with the conversion mode used 0 0 0 2.5 v stops operation can be set in normal mode 1. 0 1 0 av refp (external voltage reference input) stops operation (hi-z) 2.0 v enables operation can be set in normal mode 2 or low voltage mode. 1 0 0 stops operation (pull-down output) 2.5 v stops operation ? 1 0 1 enables operation 2.5 v can be set in normal mode 2 or low voltage mode. 1 1 0 stops operation (pull-down output) 2.0 v ? 1 1 1 v refout (voltage reference output) enables operation 2.0 v enables operation can be set in normal mode 2 or low voltage mode. other than the above setting prohibited note these bits can be set only for pd78f150xa. they are fixed ?0? for pd78f151xa. caution 1. when using the a/ d converter in normal mode 2 (lv1 = 0, lv 0 = 1) or low voltage mode (lv1 = 1, lv0 = 0), enable the input gate voltage boost ci rcuit for the a/d conver ter by using the analog reference voltage control register (advrc), and then set adce and adcs to 1. after the voltage boost circuit stabilization time (10 s) passes after the input gate voltage boost circuit for the a/d converter has been enab led, set adcs to 1.
78k0r/lx3 r01uh0004ej0501 rev.5.01 396 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) cautions 2. to use voltage reference out put to the positive refere nce voltage of the a/d c onverter, be sure to set vron to 1 after setting vrsel to 1. 3. do not change the output vo ltage of the reference voltage by using vrgv during the voltage reference operation (vron = 1). remark the combinations of the selectabl e reference voltage supplies (positiv e side, negative side) of the a/d converter are as follows, according to the adref, vrsel and vron settings. table 10-3. settings of adref, vrsel and vron adref vrsel vron positive reference voltage of a/d converter (ad refp ) negative reference voltage of a/d converter (ad refm ) 0 0 0 av refp av ss 0 1 1 v refout (vr output) av ss 1 0 0 av refp av refm 1 1 1 v refout (vr output) av refm (5) 12-bit a/d conversion result register (adcr) ( pd78f150xa only) this register is a 16-bit register that st ores the a/d conversion result in the select mode. the higher 4 bits are fixed to 0. each time a/d conversion ends, the conversion result is loaded from the successive approximation register. the higher 4 bits of the conversion re sult are stored in fff1fh and the lower 8 bits are stored in the fff1eh. adcr can be read by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 10-10. format of 10-bit a/d conversion result register (adcr) symbol address: fff1eh, fff1fh after reset: 0000h r fff1fh fff1eh 0 0 0 0 adcr caution when writing to a/d conver ter mode register (adm), analog input channel speci fication register (ads), and a/d port configurati on register (adpc), the contents of adcr may become undefined. read the conversion result follow ing conversion completion before wr iting to adm, ads, and adpc. using timing other than the a bove may cause an incorrect c onversion result to be read.
78k0r/lx3 r01uh0004ej0501 rev.5.01 397 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) (6) 10-bit a/d conversion result register (adcr) ( pd78f151xa only) this register is a 16-bit register that st ores the a/d conversion result in the select mode. the higher 4 bits are fixed to 0. the lower 2 bits are undefined. ea ch time a/d conversion ends, the c onversion result is loaded from the successive approximation register. the higher 4 bits of the conversion result are stored in fff1fh and the lower 8 bits are stored in the fff1eh. adcr can be read by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 10-11. format of 12-bit a/d conversion result register (adcr) symbol address: fff1eh, fff1fh after reset: 0000h r fff1fh fff1eh 0 0 0 0 adcr * * *: undefined caution when writing to a/d conver ter mode register (adm), analog input channel speci fication register (ads), and a/d port configurati on register (adpc), the contents of adcr may become undefined. read the conversion result follow ing conversion completion before wr iting to adm, ads, and adpc. using timing other than the a bove may cause an incorrect c onversion result to be read. (7) 8-bit a/d conversion result register (adcrh) this register is an 8-bit register that st ores the a/d conversion result. the higher 8 bits of 12-bit resolution are stored. adcrh can be read by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 10-12. format of 8-bit a/d c onversion result register (adcrh) symbol address: fff1fh note after reset: 00h r fff1fh fff1eh adcrh 0 0 0 0 adcrh note if address fff1fh is read, the data of adcrh (lower four bits of fff1fh and higher four bits of fff1eh) will be read. caution when writing to a/d conver ter mode register (adm), analog input channel speci fication register (ads), and a/d port configurati on register (adpc), the contents of adcrh may become undefined. read the conversion result follow ing conversion completion before wr iting to adm, ads, and adpc. using timing other than the a bove may cause an incorrect c onversion result to be read.
78k0r/lx3 r01uh0004ej0501 rev.5.01 398 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) (8) analog input channel specification register (ads) this register specifies the input channel of the analog voltage to be a/d converted. ads can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 10-13. format of analog input channel specification register (ads) address: fff31h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 ads 0 0 0 0 ads3 ads2 ads1 ads0 ads3 ads2 ads1 ads0 analog input channel 0 0 0 0 ani0 0 0 0 1 ani1 0 0 1 0 ani2 0 0 1 1 ani3 0 1 0 0 ani4 0 1 0 1 ani5 0 1 1 0 ani6 0 1 1 1 ani7 1 0 0 0 ani8 1 0 0 1 ani9 1 0 1 0 ani10 1 1 1 1 ani15 other than the above setting prohibited note this setting is prohibited for 78k0r/lf3. cautions 1. be sure to cl ear bits 4 to 7 to ?0?. 2 set a channel to be used fo r a/d conversion in the input mode by using port mode registers 2 and 15 (pm2, pm15). 3. do not set the pin that is set by adpc as digital i/o by ads. 4. when using an operational amplifier n, the out put signal of an operational amplifier n can be used as an analog input. remark 78k0r/lf3: n = 0, 1 78k0r/lg3, 78k0r/lh3: n = 0 to 2 note note note note
78k0r/lx3 r01uh0004ej0501 rev.5.01 399 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) (9) a/d port configuration register (adpc) this register switches the ani0/amp0-/p20 to ani7/amp2o/p27, ani8/amp2+/p150 to ani10/p152 and ani15/av refm /p157 pins to analog input of a/ d converter or digital i/o of port. adpc can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 10h. remark 78k0r/lf3: ani0-ani6, ani15 78k0r/lg3, 78k0r/lh3: ani0-ani10, ani15 figure 10-14. format of a/d port configuration register (adpc) address: f0017h after reset: 10h r/w symbol 7 6 5 4 3 2 1 0 adpc 0 0 0 adpc4 adpc3 adpc2 adpc1 adpc0 analog input (a)/digita l i/o (d) switching port 15 port 2 adp c4 adp c3 adp c2 adp c1 adp c0 ani15 /av refm /p157 ani10 /p152 ani9 /p151 ani8 /amp2+ /p150 ani7 /amp2o /p27 ani6 /amp2- /p26 ani5 /amp1+ /p25 ani4 /amp1o /p24 ani3 /amp1- /p23 ani2 /amp0+ /p22 ani1 /amp0o /p21 ani0 /amp0- /p20 0 0 0 0 0 a a a a a a a a a a a a 0 0 0 0 1 a a a a a a a a a a a d 0 0 0 1 0 a a a a a a a a a a d d 0 0 0 1 1 a a a a a a a a a d d d 0 0 1 0 0 a a a a a a a a d d d d 0 0 1 0 1 a a a a a a a d d d d d 0 0 1 1 0 a a a a a a d d d d d d 0 0 1 1 1 a a a a a d d d d d d d 0 1 0 0 0 a a a a d d d d d d d d 0 1 0 0 1 a a a d d d d d d d d d 0 1 0 1 0 a a d d d d d d d d d d 0 1 1 1 1 a d d d d d d d d d d d 1 0 0 0 0 d d d d d d d d d d d d other than the above setting prohibited note this setting is prohibited for 78k0r/lf3. cautions 1. set a channel to be u sed for a/d conversion in the input mo de by using port mode registers 2 and 15 (pm2, pm15). 2. do not set the pin that is set by adpc as digital i/o by ads. note note note note
78k0r/lx3 r01uh0004ej0501 rev.5.01 400 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) (10) port mode registers 2, 15 (pm2, pm15) when using ani0/amp0-/p20 to ani7/amp2o/p 27, ani8/amp2+/p150 to ani10/p152 and ani15/av refm /p157 pins for analog input port, set pm20 to pm27, pm150 to pm152, and p157 to 1. the output latches of p20 to p27, p150 to p152 and p157 at this time may be 0 or 1. if pm20 to pm27, pm150 to pm152 and pm157 are set to 0, they cannot be used as analog input port pins. pm2 and pm15 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh. remark 78k0r/lf3: ani0-ani6, ani15 78k0r/lg3, 78k0r/lh3: ani0-ani10, ani15 caution if a pin is set as an analog input por t, not the pin level bu t ?0? is always read. figure 10-15. formats of port mode registers 2, 15 (pm2, pm15) ? 78k0r/lf3 address: fff22h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm2 1 pm26 pm25 pm24 pm23 pm22 pm21 pm20 address: fff2fh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm15 pm157 1 1 1 1 1 1 1 ? 78k0r/lg3, 78k0r/lh3 address: fff22h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 address: fff2fh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm15 pm157 1 1 1 1 pm152 pm151 pm150 pmmn pmn pin i/o mode selection (mn = 20 to 27, 150 to 152, 157) 0 output mode (output buffer on) 1 input mode (output buffer off)
78k0r/lx3 r01uh0004ej0501 rev.5.01 401 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) the ani0/amp0-/p20 to ani7/amp2o/p27, an i8/amp2+/p150 to ani10/p152 and ani15/av refm /p157 pins are as shown below depending on the settings of adpc , ads, pm2, pm15, oaenn bit and adref bit. caution when an operational ampl ifier is used, pins ampn+, ampn ? , and ampno are used, so the alternative analog input functions cannot be u sed. the operational amplifier output signals, however, can be used as analog inputs. table 10-4. setting functions of ani0/amp0-/p20, ani2/amp0+/p22, ani3/amp1-/p23, ani5/amp1+/p25, ani6/amp2-/p26, and ani8/amp2+/p150 pins adpc register pm2 and pm15 registers oaenn bit ads register ani0/amp0-/p20, ani2/amp0+/p22, ani3/amp1-/p23, ani5/amp1+/p25, ani6/amp2-/p26, and ani8/amp2+/p150 pins 0 ? digital input input mode 1 ? setting prohibited 0 ? digital output digital i/o selection output mode 1 ? setting prohibited selects ani. analog input (to be converted) 0 does not select ani. analog input (not to be converted) selects ani. setting prohibited input mode 1 does not select ani. operational amplifier input analog input selection output mode ? ? setting prohibited remark 78k0r/lf3: ani0/amp0-/p20, ani2/amp0+/p22, ani3/amp1-/p23, ani5/amp1+/p25, n = 0, 1 78k0r/lg3, 78k0r/lh3: ani0/amp0-/p20, ani2/amp0+/p22, ani3/amp1-/p23, ani5/amp1+/p25, ani6/amp2-/p26, ani8/amp2+/p150, n = 0 to 2 table 10-5. setting functions of ani1/amp0 o/p21, ani4/amp1o/p24, and ani7/amp2o/p27 pins adpc register pm2 register oaenn bit ads register ani1/amp0o/p21, ani4/amp1o/p24, and ani7/amp2o/p27 pins 0 ? digital input input mode 1 ? setting prohibited 0 ? digital output digital i/o selection output mode 1 ? setting prohibited selects ani. analog input (to be converted) 0 does not select ani. analog input (not to be converted) selects ani. operational amplifier output (not to be converted) input mode 1 does not select ani. operational amplifier output (to be converted) analog input selection output mode ? ? setting prohibited remark 78k0r/lf3: ani1/amp0o/p21, ani4/amp1o/p24, n = 0, 1 78k0r/lg3, 78k0r/lh3: ani1/amp0o/p21, ani4 /amp1o/p24, and ani7/amp2o/p27, n = 0 to 2
78k0r/lx3 r01uh0004ej0501 rev.5.01 402 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) table 10-6. setting functions of ani9/p151 and ani10/am152 pins adpc register pm15 register ads register ani9/p151 and ani10/am152 pins input mode ? digital input digital i/o selection output mode ? digital output selects ani. analog input (to be a/d converted) input mode does not select ani. analog input (not to be a/d converted) analog input selection output mode ? setting prohibited remark 78k0r/lf3: ani9/p151 and ani10/am152 are not mounted. 78k0r/lg3, 78k0r/lh3: ani9/p151, ani10/am152 table 10-7. setting functions of ani15/av refm /p157 pin adpc register pm15 register adref bit ads register ani15/av refm /p157 pin 0 ? digital input input mode 1 ? setting prohibited 0 ? digital output digital i/o selection output mode 1 ? setting prohibited selects ani. analog input (to be converted) 0 does not select ani. analog input (not to be converted) input mode 1 ? negative reference voltage input of a/d converter analog input selection output mode ? ? setting prohibited
78k0r/lx3 r01uh0004ej0501 rev.5.01 403 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) 10.4 a/d converter operations 10.4.1 basic operations of a/d converter <1> set bit 5 (adcen) of peripheral enable register 0 (per0) to 1 to start the supply of the input clock to the a/d converter. <2> set the a/d conversion time by using bits 5 to 1 (fr2 to fr0, lv1, and lv0) of a/d converter mode register (adm), and set the operation mode by using bit 6 (admd) of adm. <3> use bits 7, 3, 1, and 0 (adref, vrsel, vrgv, and vr on) of the analog reference voltage control register (advrc) to specify the reference volta ge source of the a/d converter and the operation of the input gate voltage boost circuit for the a/d converter. <4> set bit 0 (adce) of adm to 1 to star t the operation of the a/d voltage comparator. <5> set the channels for a/d conversion to analog input by using the a/d port configurat ion register (adpc) and set to input mode by using port mode registers (pm2 and pm15). <6> select one channel for a/d conversion using the analog input channel specification register (ads). <7> use the a/d converter mode register 1 (adm1) to set the trigger mode. <8> start the conversion operation by setting bit 7 (adcs) of adm to 1, if the software trigger mode has been set in step <7>. if timer trigger mode was specified in step <7>, adcs is automatically set to 1 and a/d conversion starts when the timer trigger signal is detected.(<9> to <15> are operations performed by hardware.) <9> the voltage input to the selected analog input c hannel is sampled by the sample & hold circuit. <10> when sampling has been done for a certain time, the sa mple & hold circuit is placed in the hold state and the sampled voltage is held until the a/ d conversion operation has ended. <11> bit 11 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <12> the voltage difference between the series resistor string voltage tap and sampled voltage is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set to 1. if the analog input is smaller than (1/2) av ref , the msb is reset to 0. <13> next, bit 10 of sar is automatically set to 1, and t he operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. ? bit 11 = 1: (3/4) av ref ? bit 11 = 0: (1/4) av ref the voltage tap and sampled voltage are compared and bit 8 of sar is manipulated as follows. ? sampled voltage voltage tap: bit 10 = 1 ? sampled voltage < voltage tap: bit 10 = 0 <14> comparison is continued in this way up to bit 0 of sar. <15> upon completion of the comparison of 12 bits, an effe ctive digital result value remains in sar, and the result value is transferred to the a/d conversion resu lt register (adcr, adcrh) and then latched. at the same time, the a/d conversion end in terrupt request (intad) can also be generated. <16> if single conversion mode has been set in step <2>, adcs is automatically cleared to 0 and enters a wait state after the first a/d conversion ends. if the continuous conversion mode has been set in step <2>, repeat steps <9> to <15>. to stop the a/d converter, clear adcs to 0. to restart a/d conversion from the status of adce = 1, start from <8>. to start a/d conversion again when adce = 0, set adce to 1, wait for 1 s or longer, and start step <8>. to change the channel to be a/d converted, perform step <6>.
78k0r/lx3 r01uh0004ej0501 rev.5.01 404 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) cautions 1. make sure the period of <4> to <8> is 1 s or more. 2. to use an operational amplifier output fo r an analog input, start operating the operational amplifier before setting the a/d conver sion operation (see chapter 12 operational amplifier). furthermore, do not change th e operational amplifier setting during the a/d conversion operation. 3. to use an output voltage of the voltage reference for a pos itive reference voltage of a/d converter, start operating the vo ltage reference before setting the a/d conversion operation (see chapter 13 voltage reference). furthermore, do not change the voltage reference setting during the a/d conversion operation. 4. when using the a/d converter in normal mode 2 (l v1 = 0, lv0 = 1) or low voltage mode (lv1 = 1, lv0 = 0), enable the input gate voltage boost circ uit for the a/d converte r by using the analog reference voltage control register (advrc), and then set adce and adcs to 1. after the voltage boost circuit stabilization time (10 s) passes after the input gate voltage boost circuit for the a/d converter has been enab led, set adcs to 1. remark two types of a/d conversion result registers are available. reset signal generation clears the a/d conversion result register (adcr, adcrh) to 0000h or 00h. ? adcr (16 bits): store 12-bit a/d conversion value ? adcrh (8 bits): store 8-bit a/d conversion value figure 10-16. basic operation of a/d converter sar adcr intad a/d converter operation conversion time sampling time sampling undefined a/d conversion conversion result conversion result
78k0r/lx3 r01uh0004ej0501 rev.5.01 405 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) 10.4.2 input voltage and conversion results the relationship between the analog i nput voltage input to the analog input pins (ani0 to ani10, ani15) and the theoretical a/d conversion result (stored in the 12-bit a/d conversion result regi ster (adcr)) is shown by the following expression. adcr = int ( 4096 + 0.5) or (adcr ? 0.5) v ain < (adcr + 0.5) where, int( ): function which returns integer part of value in parentheses v ain : analog input voltage av ref : reference voltage of a/d converter adcr: 12-bit a/d conversion result register (adcr) value remark 78k0r/lf3: ani0-ani6, ani15 78k0r/lg3, 78k0r/lh3: ani0-ani10, ani15 figure 10-16 shows the relationship between the analo g input voltage and the a/d conversion result. figure 10-17. relationship between analog i nput voltage and a/d conversion result 4095 4094 4093 3 2 1 0 0fffh 0ffeh 0ffdh 0003h 0002h 0001h 0000h a/d conversion result sar adcr 1 8192 1 4096 3 8192 2 4096 5 8192 input voltage/av ref 3 4096 8187 8192 4094 4096 8189 8192 4095 4096 8191 8192 1 v ain av ref av ref 4096 av ref 4096
78k0r/lx3 r01uh0004ej0501 rev.5.01 406 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) 10.4.3 a/d converter operation modes the following four a/d converter operation modes are available. ? software trigger mode (continuous conversion mode) ? software trigger mode (single conversion mode) ? timer trigger mode (continuous conversion mode) ? timer trigger mode (single conversion mode) (1) software trigger mode (c ontinuous conversion mode) <1> by setting bit 7 (adcs) of the a/d converter mode regi ster (adm) to 1, the a/d conversion operation of the voltage, which is applied to the analog input pin specif ied by the analog input chan nel specification register (ads), is started. <2> when a/d conversion has been completed, the result of the a/d conversion is stored in the a/d conversion result register (adcr, adcrh), and an interrupt request signal (intad) is generated. when one a/d conversion has been completed, the next a/d conversion operation is immediately started. <3> if 1 is written to adcs during a/d conversion, the a/ d conversion operation under execution is stopped and restarted from the beginning. at this time, th e conversion result immediately before is retained. <4> if ads is rewritten during a/d conversion, the a/d c onversion operation under exec ution is stopped and restarted from the beginning. at this time, the conv ersion result immediately before is retained. <5> if 0 is written to adcs during a/d conversion, a/d conversion is immediately stopped. at this time, the conversion result immediat ely before is retained. figure 10-18. software trigger m ode (continuous conversion mode) anin <1> adcs = 1 anin anin anim anin anim anim adcr, adcrh intad adcs <3> adcs = 1 <5> adcs = 0 a/d conversion conversion operation under execution is stopped, and restarted from the beginning conversion operation under execution is stopped <4> rewriting ads <2> a/d conversion is completed <2> a/d conversion is completed remark 78k0r/lf3: n = 0 to 6, 15, m = 0 to 6, 15 78k0r/lg3, 78k0r/lh3: n = 0 to 10, 15, m = 0 to 10, 15
78k0r/lx3 r01uh0004ej0501 rev.5.01 407 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) (2) software trigger mode (single conversion mode) <1> by setting bit 7 (adcs) of the a/d converter mode regi ster (adm) to 1, the a/d conversion operation of the voltage, which is applied to the analog input pin specif ied by the analog input chan nel specification register (ads), is started. <2> when a/d conversion has been completed, the result of the a/d conversion is stored in the a/d conversion result register (adcr, adcrh), and an interrupt request signal (intad) is generated. when one a/d conversion has been completed, adcs is automatically clear ed and an a/d conversion wa it state is entered. <3> if 1 is written to adcs during a/d conversion, the a/ d conversion operation under execution is stopped and restarted from the beginning. at this time, th e conversion result immediately before is retained. <4> if ads is rewritten during a/d conversion, the a/d c onversion operation under exec ution is stopped and restarted from the beginning. at this time, the conv ersion result immediately before is retained. <5> if 0 is written to adcs during a/d conversion, a/d conversion is immediately stopped. at this time, the conversion result immediat ely before is retained. figure 10-19. software trigger mode (single conversion mode) anin anin anin anim anin anim an im adcr, adcrh intad adcs <1> adcs = 1 <5> adcs = 0 <1> adcs = 1 <3> adcs = 1 <1> adcs = 1 a/d conversion <4> rewriting ads <2> a/d conversion is completed <2> a/d conversion is completed wait state wait state conversion operation under execution is stopped, and restarted from the beginning conversion operation under execution is stopped remark 78k0r/lf3: n = 0 to 6, 15, m = 0 to 6, 15 78k0r/lg3, 78k0r/lh3: n = 0 to 10, 15, m = 0 to 10, 15
78k0r/lx3 r01uh0004ej0501 rev.5.01 408 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) (3) timer trigger mode (c ontinuous conversion mode) <1> timer trigger mode is set and a timer trigger wait state is entered by setting bit 7 (adtmd) of a/d converter mode register 1 (adm1) to 1. <2> when the timer trigger signal is detected, bit 7 (adcs) of the a/d converter mode regi ster (adm) is automatically set to 1 and a/d conversion of the voltage applied to the analog input pin specified using the analog input channel specification register (ads) starts. <3> when a/d conversion has been completed, the result of the a/d conversion is stored in the a/d conversion result register (adcr, adcrh), and an interrupt request signal (intad) is generated. when one a/d conversion has been completed, the next a/d conversion operation is immediately started. <4> if 1 is written to ads during a/d conversion, the a/d conversion operation u nder execution is stopped and restarted from the beginning. at this time, th e conversion result immediately before is retained. <5> if a timer trigger signal is generated during a/d conv ersion, the a/d conversion o peration under execution is stopped and restarted from the beginning. at this time , the conversion result imm ediately before is retained. <6> if 0 is written to adcs during a/ d conversion, a/d conversion is immedi ately stopped, and a timer trigger wait state is entered. at this time, the conver sion result immediately before is retained. <7> when 0 is written to adtmd while a/d conversion oper ation is stopped (adcs = 0), the software trigger mode is set and a/d conversion operation is not started, even if a timer trigger signal is generated. figure 10-20. timer trigger m ode (continuous c onversion mode) anin <1> adtmd = 1 anin anin anim anin anim anim adcr, adcrh intad adcs <6> adcs = 0 anim <7> adtmd = 0 anin timer trigger adtmd a/d conversion <3> a/d conversion is completed <3> a/d conversion is completed <3> a/d conversion is completed <2> timer trigger generation <5> timer trigger generation wait state wait state <4> rewriting ads conversion operation under execution is stopped, and restarted from the beginning conversion operation under execution is stopped, and restarted from the beginning conversion operation under execution is stopped note note leave at least enough time for a/d conversion to finish between each generation of the timer trigger signal. remark 78k0r/lf3: n = 0 to 6, 15, m = 0 to 6, 15 78k0r/lg3, 78k0r/lh3: n = 0 to 10, 15, m = 0 to 10, 15
78k0r/lx3 r01uh0004ej0501 rev.5.01 409 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) (4) timer trigger mode (single conversion mode) <1> timer trigger mode is set and a timer trigger wait state is entered by setting bit 7 (adtmd) of a/d converter mode register 1 (adm1) to 1. <2> when the timer trigger signal is detected, bit 7 (adcs) of the a/d converter mode regi ster (adm) is automatically set to 1 and a/d conversion of the voltage applied to the analog input pin specified using the analog input channel specification register (ads) starts. <3> when a/d conversion has been completed, the result of the a/d conversion is stored in the a/d conversion result register (adcr, adcrh), and an interrupt request signal (intad) is generated. when one a/d conversion has been completed, adcs is automatically clear ed and a timer trigger wait state is entered. <4> even if ads is rewritten during an a/d conversion operat ion, the a/d conversion operat ion performed at that time is continued. the channel will be switched w hen the next a/d conver sion operation starts. <5> if a timer trigger signal is generated during a/d conv ersion, the a/d conversion o peration under execution is stopped and restarted from the beginning. at this time , the conversion result imm ediately before is retained. <6> when 0 is written to adtmd while a/d conversion oper ation is stopped (adcs = 0), the software trigger mode is set and a/d conversion operation is not started, even if a timer trigger signal is generated. figure 10-21. timer trigger m ode (single conversion mode) anin anin anim anin anim adcr, adcrh intad adcs anin adtmd anim timer trigger a/d conversion wait state wait state wait state wait state <1> adtmd = 1 <6> adtmd = 0 <2> timer trigger generation <2> timer trigger generation <2> timer trigger generation <5> timer trigger generation <3> a/d conversion is completed <3> a/d conversion is completed <3> a/d conversion is completed conversion operation under execution is stopped, and restarted from the beginning conversion is not stopped <4> rewriting ads note note leave at least enough time for a/d conversion to finish between each generation of the timer trigger signal. remark 78k0r/lf3: n = 0 to 6, 15, m = 0 to 6, 15 78k0r/lg3, 78k0r/lh3: n = 0 to 10, 15, m = 0 to 10, 15
78k0r/lx3 r01uh0004ej0501 rev.5.01 410 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) the setting methods are described below. <1> set bit 5 (adcen) of peripheral enable register 0 (per0) to 1. <2> select the conversion time by using bits 5 to 1 (fr2 to fr0, lv1, and lv0) of a/d converter mode register (adm), and select the operation mode by using bit 6 (adscm) of adm. <3> use bits 7, 3, 1, and 0 (adref, vrsel, vrgv, and vron) of the analog reference voltage control register (advrc) to specify the reference vo ltage source of the a/d converte r and the operation of the input gate voltage boost circuit for the a/d converter. <4> set bit 0 (adce) of adm to 1. <5> set the channel to be used in the analog input mode by using bits 4 to 0 (adpc4 to adpc0) of the a/d port configuration register (adpc), bits 7 to 0 (pm27 to pm 20) of port mode register 2 (pm2), and bits 7, 2 to 0 (pm157, pm152 to pm150) of port mode register 15 (pm15). <6> select a channel to be used by using bits 3 to 0 (ads3 to ads0) of the analog input channel specification register (ads). <7> use bits 0 and 7 (adtrs, adtmd) of a/d conver ter mode register 1 (adm1) to set the trigger mode. <8> in the software trigger mode start a/d conversion by setting bit 7 (adcs) of adm to 1. in the timer trigger mode adcs is automatically set to 1 and a/d conversion starts when the timer trigger signal is generated. <9> when one a/d conversion has been completed, an interrupt request signal (intad) is generated. <10> transfer the a/d conversion data to the a/d conversion result register (adcr, adcrh). <11> in the continuous conversion mode start the next a/d conversion automatically. in the single conversion mode adcs is automatically cleared to 0 and the a/d converter goes on standby. to start a/d conversion operation, go to step <8>. <12> change the channel using bits 3 to 0 (a ds3 to ads0) of ads to start a/d conversion. note <13> when one a/d conversion has been completed, an interrupt request signal (intad) is generated. <14> transfer the a/d conversion data to the a/d conversion result register (adcr, adcrh). <15> clear adcs to 0. <16> in the software trigger mode clear adce to 0. in the timer trigger mode clear adce and adtmd to 0. <17> clear bit 5 (adcen) of peripheral enable register 0 (per0) to 0. note when in timer trigger mode (single conversion mode), the a/d conversion operation is continued even if bits 3 to 0 of ads are set during a/d conversion. t he channel will be changed when the next a/d conversion operation starts. when in any other mode, a/d conver sion operation is aborted after bits 3 to 0 of ads have been set, and a/d conversion operation is st arted from the beginning after the channel has been changed.
78k0r/lx3 r01uh0004ej0501 rev.5.01 411 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) cautions 1. make sure the period of <4> to <8> is 1 s or more. 2. <4> may be done between <5> and <7>. 3. <4> can be omitted. howe ver, ignore data of the first con version after <8> in this case. 4. the period from <9> to <13> differs from the conversion time set using bits 5 to 1 (fr2 to fr0, lv1, lv0) of adm. the period from <12> to <13> is the conversion time set using fr2 to fr0, lv1, and lv0. 5. to use an operational amplifier output for an analog input, start operating the operational amplifier before setting the a/d conver sion operation (see chapter 12 operational amplifier). furthermore, do not change th e operational amplifier setting during the a/d conversion operation. 6. to use an output voltage of the voltage reference for a pos itive reference voltage of a/d converter, start operating the voltage referenc e before setting the a/d conversion operation (see chapter 13 voltage reference). fur thermore, do not change the voltage reference setting during the a/d conversion operation. 7. when using the a/d converter in normal mode 2 (lv1 = 0, lv0 = 1) or low voltage mode (lv1 = 1, lv0 = 0), enable the input gate voltage boost circuit for the a/d converter by using the analog reference voltage control register (advrc), and then set adce and adcs to 1. after the voltage boost circuit stabilization time (10 s) passes after the input gate voltage boost circuit for the a/d c onverter has been enab led, set adcs to 1.
78k0r/lx3 r01uh0004ej0501 rev.5.01 412 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) 10.5 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltage that can be identifi ed. that is, the percentage of the analog input voltage per bit of digital output is called 1lsb (least significant bi t). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 12 bits. 1lsb = 1/2 12 = 1/4096 = 0.024 %fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integr al linearity error, and differential linearit y errors that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digital co de, so a quantization error cannot be avoided. note that the quantization error is not included in the overall error, zero-scale error, full-scale erro r, integral linearity error, and differential linearity erro r in the characteristics table. figure 10-22. overall error figur e 10-23. quanti zation error ideal line 0 ...... 0 1 ...... 1 digital output overall error analog input av ref 0 0......0 1 ...... 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ref (4) zero-scale error this shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2lsb) when the digital output changes from 0......000 to 0......001. if the actual measurement value is gr eater than the theoretical value, it shows the difference between the actual measurement value of the analog inpu t voltage and the theoretical value (3/ 2lsb) when the digital output changes from 0??001 to 0??010.
78k0r/lx3 r01uh0004ej0501 rev.5.01 413 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) (5) full-scale error this shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full-scale ? 3/2lsb) when the digital output chan ges from 1......110 to 1......111. (6) integral linearity error this shows the degree to which the conversion characteristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual m easurement value and the ideal straight line when the zero- scale error and full-scale error are 0. (7) differential linearity error while the ideal width of code output is 1lsb, this indicate s the difference between the ac tual measurement value and the ideal value. figure 10-24. zero-scale error figure 10-25. full-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref ? 3 full-scale error ideal line analog input (lsb) digital output (lower 3 bits) av ref ? 2av ref ? 1 av ref figure 10-26. integral linearity error figure 10-27. differential linearity error 0 av ref digital output analog input integral linearity error ideal line 1 ...... 1 0 ...... 0 0 av ref digital output analog input differential linearity error 1 ...... 1 0 ...... 0 ideal 1lsb width (8) conversion time this expresses the time from the start of samp ling to when the digital output is obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the anal og voltage to be sampled by the sample & hold circuit. sampling time conversion time
78k0r/lx3 r01uh0004ej0501 rev.5.01 414 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) 10.6 cautions for a/d converter (1) operating current in stop mode shift to stop mode after stopping the a/d converter (b y setting bit 7 (adcs) of the a/d converter mode register (adm) to 0). the operating current can be reduced by setti ng bit 0 (adce) of the a/d conv erter mode register (adm) to 0 at the same time. when using normal mode 2 (lv1 = 0, lv0 = 1) or low voltage mode (lv1 = 1, lv0 = 0), clear bit 1 (vrgv) and bit 0 (vron) of the analog reference voltage control regi ster (advrc) to 0, and then shift to stop mode. to restart from the standby status, clear bit 0 (adif) of interrupt request flag regist er 1l (if1l) to 0 and start operation. (2) input range of ani0 to ani10, ani15 observe the rated range of the ani0 to ani1 0, ani15 input voltage. if a voltage of av dd0 or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an analog input channel, t he converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result register (adcr, adcrh) write and adcr or adcrh read by instruction upon the end of conversion adcr or adcrh read has priority. after the read operati on, the new conversion result is written to adcr or adcrh. <2> conflict between adcr or adcrh writ e and a/d converter mode register (adm) write, analog input channel specification register (ads), or a/ d port configuration register (adpc) write upon the end of conversion adm, ads, or adpc write has priority. adcr or a dcrh write is not performed, nor is the conversion end interrupt signal (intad) generated. (4) noise countermeasures to maintain the 12-bit resolution, attent ion must be paid to noise input to the av refp pin and pins ani0 to ani10, ani15. <1> connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. <2> the higher the output impedance of the analog input source, the greater the influence. to reduce the noise, connecting external c as shown in figure 10-26 is recommended. <3> do not switch these pins wit h other pins during conversion. <4> the accuracy is improved if the halt mode is set immediately after the start of conversion. remark 78k0r/lf3: ani0-ani6, ani15 78k0r/lg3, 78k0r/lh3: ani0-ani10, ani15
78k0r/lx3 r01uh0004ej0501 rev.5.01 415 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) figure 10-28. analog input pin connection reference voltage input c = 100 to 1,000 pf if there is a possibility that noise equal to or higher than av dd0 or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av refp av ss v ss ani0 to ani10, ani15 (5) ani0 to ani10, ani15 <1> the analog input pins (ani0 to ani7) are also used as input port pins (p20 to p27). the analog input pins (ani8 to ani10, ani15) are al so used as input port pins (p150 to p152, p157). when a/d conversion is performed with any of ani0 to ani10, and ani15 selected, do not access p20 to p27, p150 to p152, and p157 while conversion is in progre ss; otherwise the conversion resolution may be degraded. it is recommended to select pins used as p20 to p27, p150 to p152, and p157 star ting with the ani0/p20 that is the furthest from av dd0 . <2> if the pins adjacent to the pins currently used for a/ d conversion are used as digi tal i/o port, the expected value of the a/d conversion may not be obtained due to coupling noi se. therefore, make sure that digital pulses are not input to or output from the pins adjace nt to the pin undergoing a/d conversion. <3> if any pin among pins of ports 2 and 15 is used as di gital output port during a/d c onversion, the expected value of the a/d conversion may not be obtained due to coupling noi se. therefore, make sure that digital pulses are not output to pins of ports 2 and 15 during a/d conversion. (6) input impedance of ani0 to ani10, ani15 pins this a/d converter charges a sampling capacitor for sampling during sampling time. therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flows during sampling. consequently, the input impedanc e fluctuates depending on whether sampling is in progress, and on the other states. to make sure that sampling is effective, however, it is recommended to keep the ou tput impedance of the analog input source to within 1 k , and to connect a capacitor of about 100 pf to the ani0 to ani10 and ani15 pins (see figure 10-26 ). remark 78k0r/lf3: ani0-ani6, ani15 78k0r/lg3, 78k0r/lh3: ani0-ani10, ani15
78k0r/lx3 r01uh0004ej0501 rev.5.01 416 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) (7) av refp pin input impedance a series resistor string of several tens of k is connected between the av refp and av refm (or av ss ) pins. therefore, if the output impedance of the reference voltage supply is high, this will result in a series connection to the series resistor string between the av refp and av refm (or av ss ) pins, resulting in a large reference voltage (av ref ) error of a/d converter. (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the analog input channel spec ification register (ads) is changed. therefore, if an analog in put pin is changed during a/d conversion, the a/d conversion result and adif for the pre- change analog input may be set just before the ads rewrite. caution is therefor e required since, at this time, when adif is read immediately after the ad s rewrite, adif is set despite the fact a/d conversion for the post-change analog input has not ended. when a/d conversion is stopped and then resumed, clear ad if before the a/d conversion operation is resumed. figure 10-29. timing of a/d conver sion end interrupt request generation ads rewrite (start of anin conversion) a/d conversion adcr adif anin anin anim anim anin anin anim anim ads rewrite (start of anim conversion) adif is set but anim conversion has not ended. remark 78k0r/lf3: n = 0 to 6, 15, m = 0 to 6, 15 78k0r/lg3, 78k0r/lh3: n = 0 to 10, 15, m = 0 to 10, 15 (9) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conversi on starts may not fall within the rating range if the adcs bit is set to 1 within 1 s after the adce bit was set to 1, or if the adcs bit is set to 1 with the adce bit = 0. take measures such as polling the a/d conversion end interrupt request (intad) and removing the first conversion result.
78k0r/lx3 r01uh0004ej0501 rev.5.01 417 jun 20, 2011 chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) (10) a/d conversion result regist er (adcr, adcrh) read operation when a write operation is performed to a/d converter mode register (adm), a/d converter mode register 1 (adm1), analog input channel specification regist er (ads), and a/d port configuration re gister (adpc), the contents of adcr and adcrh may become undefined. read the conversion result following conversion completion before writing to adm, adm1, ads, or adpc. using a timing other than t he above may cause an incorrect conversion result to be read. (11) internal equivalent circuit the equivalent circuit of the analog input block is shown below. figure 10-30. internal equi valent circuit of anin pin anin c1 c2 r1 table 10-8. resistance and capacitance valu es of equivalent circui t (reference values) r1 c1 c2 11.5 k 8.0 pf 8.0 pf remarks 1. the resistance and capacitance values shown in table 10-8 are not guaranteed values. 2. 78k0r/lf3: n = 0 to 6, 15, 78k0r/lg3, 78k0r/lh3: n = 0 to 10, 15 (12) rewriting dacswn during a/d conversion rewriting dacswn (n = 0, 1) during a/d conversion is pr ohibited when both the positiv e reference voltage of a/d converter (ad refp ) and the positive reference voltage of the d/a converter (da refp ) are the voltage reference output (v refout ) (vrsel = 1 and daref = 1). rewrite it when conversion operation is stopped (adcs = 0).
78k0r/lx3 r01uh0004ej0501 rev.5.01 418 jun 20, 2011 chapter 11 d/a converter ( pd78f150xa only) chapter 11 d/a converter ( pd78f150xa only) 11.1 function of d/a converter the d/a converter with two channels is mounted onto all 78k0r/lx3 microcontroller products. the d/a converter has t he following features. { 12-bit resolution 2 channels { r-2r ladder method { output analog voltage ? 12-bit resolution: reference voltage for d/a converter m12/4096 (m12: value set to dacswn register) ? 8-bit resolution: reference voltage for d/a converter m8/256 (m8: value set to dacsn register) { supply voltage for d/a converter: av dd1 { ground for d/a converter: av ss { positive reference voltage for d/a converter: av dd1 , or av refp /v refout { negative reference voltage for d/a converter: av ss { operation mode ? normal mode ? real-time output mode remark n = 0, 1 11.2 configuration of d/a converter the d/a converter includes the following hardware. table 11-1. configuration of d/a converter item configuration control registers peripheral enable register 0 (per0) d/a converter mode register (dam) d/a conversion value setting regist ers w0, w1 (dacsw0, dacsw1) d/a conversion value setting regi sters 0, 1 (dacs0, dacs1)
78k0r/lx3 r01uh0004ej0501 rev.5.01 419 jun 20, 2011 chapter 11 d/a converter ( pd78f150xa only) figure 11-1. block diag ram of d/a converter ano0/p110 ano1/p111 dace0 dace1 damd0 damd1 av refp /v refout av ss daref dace1 dace0 dares1 dares0 damd1 damd0 av dd1 dares0 da refp write signal of dacsw0 register or write signal of dacs0 internal bus internal bus d/a conversion value setting register ( dacsw0 or dacs0) selector selector d/a conversion value setting register ( dacsw1 or dacs1) write signal of dacsw1 register or write signal of dacs1 inttm04 signal inttm05 signal d/a converter mode register (dam) selector voltege reference circuit vrsel bit vron, vrgv bit da refm remarks 1 . inttm04 and inttm05 are timer trigger signals (interr upt signals from timer channels 5 and 6) that are used in the real-time output mode. 2. channels 0 and 1 of the d/a converter share the av ref1 pin and the av refp /v refout pin. 3. channels 0 and 1 of the d/a converter share the av ss pin. the av ss pin is also shared with an a/d converter, an operational amplifier , and a voltage reference.
78k0r/lx3 r01uh0004ej0501 rev.5.01 420 jun 20, 2011 chapter 11 d/a converter ( pd78f150xa only) 11.3 registers used in d/a converter the d/a converter uses the following four registers. ? peripheral enable register 0 (per0) ? d/a converter mode register (dam) ? d/a conversion value setting registers w0, w1 (dacsw0, dacsw1) ? d/a conversion value setting registers 0, 1 (dacs0, dacs1) (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to reduc e the power consumption and noise. when the d/a converter is used, be sure to se t bit 6 (dacen) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. cautions when setting the d/ a converter, be sure to set dacen to 1 first. if dacen = 0, writing to a control register of the d/a conver ter is ignored, and, even if the register is read, only the default value is read. figure 11-2. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> per0 rtcen dacen adcen iicaen note sau1en sau0en tau1en tau0en dacen control of d/a converter input clock 0 stops supply of input clock. ? sfr used by the d/a converter cannot be written. ? the d/a converter is in the reset status. 1 supplies input clock. ? sfr used by the d/a converter can be read/written. note 78k0r/lg3, 78k0r/lh3 only
78k0r/lx3 r01uh0004ej0501 rev.5.01 421 jun 20, 2011 chapter 11 d/a converter ( pd78f150xa only) (2) d/a converter mode register (dam) this register controls the oper ation of the d/a converter. dam can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 11-3. format of d/a converter mode register (dam) address: fff5ch after reset: 00h r/w symbol 7 6 <5> <4> 3 2 1 0 dam 0 daref dace1 dace0 dares1 dares0 damd1 damd0 daref positive reference voltage supply selection of d/a converter note1 0 av dd1 (power supply for d/a co nverter analog circuit) 1 v refout (voltage reference output) note2 / av refp (external voltage reference input) dacen d/a conversion operation control (n = 0, 1) 0 stops conversion operation 1 enables conversion operation daresn d/a converter resolution selection (n = 0, 1) 0 8-bit 1 12-bit damdn d/a converter operation mode selection (n = 0, 1) 0 normal mode 1 real-time output mode notes 1. the reference voltage of the d/a converter cannot be specified separately for each channel because it is common to both channels. 2. to use an output voltage of the volt age reference for the positive refere nce voltage of the d/a converter (da refp ), start operating the voltage reference before setting the d/a conversion operation (see chapter 13 voltage reference ). furthermore, do not change the vo ltage reference setting during the d/a conversion operation. remark the positive reference voltage of the d/a converter is as follows, a ccording to the daref, vrsel and vron settings. table 11-2. settings of daref, vrsel and vron daref vrsel vron positive reference voltage of d/a converter (da refp ) 0 av dd1 1 0 0 av refp 1 1 1 v refout : don?t care
78k0r/lx3 r01uh0004ej0501 rev.5.01 422 jun 20, 2011 chapter 11 d/a converter ( pd78f150xa only) (3) d/a conversion value setting registers w0, w1 (dacsw0, dacsw1) these registers are used to set an analog voltage value to be output to the ano0 and ano1 pins, when the d/a converter is used. dacsw0 and dacsw1 can be read by a 16 -bit memory manipulation instruction. reset signal generation clears these registers to 0000h. figure 11-4. format of d/a conversion valu e setting registers w0, w1 (dacsw0, dacsw1) address: fff58h, fff59h (dacsw0), fff5ah, fff5bh (dacsw1) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dacswn 0 0 0 0 dacs wn11 dacs wn10 dacs wn9 dacs wn8 dacs wn7 dacs wn6 dacs wn5 dacs wn4 dacs wn3 dacs wn2 dacs wn1 dacs wn0 caution rewriting dacswn during a/d c onversion is prohibited when both the positive reference voltage of the a/d converter (ad refp ) and the positive reference volt age of the d/a converter (da refp ) are the voltage reference output (v refout ) (vrsel = 1 and daref = 1). rewrite it when conversion operation is stopped (adcs = 0). remarks 1. the relations between the resolutions and analog output voltages (v anon ) of the d/a converter are as follows. ? 8-bit resolution (daresn = 0) : v anon = reference voltage for d/a converter (dacswn7 to dacswn0) /256 ? 12-bit resolution (daresn = 1) : v anon = reference voltage for d/a converter (dacswn11 to dacswn0) /4096 2. n = 0, 1 (4) d/a conversion value setting registers 0, 1 (dacs0, dacs1) these registers are used to set the analog voltage values to be output to the ano0 and ano1 pins when the d/a converter is used at 8-bit resolution. dacs0 and dacs1 can be read by an 8- bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 11-5. format of d/a conversion valu e setting registers 0, 1 (dacs0, dacs1) address: fff58h (dacs0), fff5ah (dacs1) after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 dacsn dacsn7 dacsn6 dacsn5 dacs n4 dacsn3 dacsn2 dacsn1 dacsn0 remarks 1. the relations between the resolutions and analog output voltages (v anon ) of the d/a converter are as follows. ? 8-bit resolution (daresn = 0) : v anon = reference voltage for d/a converter (dacsn7 to dacsn0) /256 2. n = 0, 1
78k0r/lx3 r01uh0004ej0501 rev.5.01 423 jun 20, 2011 chapter 11 d/a converter ( pd78f150xa only) 11.4 operation of d/a converter 11.4.1 operation in normal mode d/a conversion is performed using write operation to t he dacsn register as the trigger. the setting method is described below. <1> set bit 6 (dacen) of peripheral enable register 0 (per0) to 1 to start the supply of the input clock to the d/a converter. <2> set the damdn bit of the d/a converter mode register (dam) to 0 (normal mode). <3> use the bit 6 (daref) of the dam register to select the d/a converter reference voltage supply on the positive side. <4> use the daresn bit of the dam register to select the resolution of the d/a converter. <5> set the analog voltage value to be output to the anon pin to the d/a conversion value setting register wn (dacswn) or d/a conversion value setting register n (dacsn). steps <1> and <5> above constitute the initial settings. <6> set the dacen bit of the dam regi ster to 1 (d/a conversion enable). after the wait time (20 s or more) elapses, d/a conversion starts , and then, after the settling time (18 s (max.)) elapses, the d/a converted analog voltage value is output from the anon pin. <7> to perform subsequent d/a conversions, wr ite to the dacswn or dacsn register. the previous d/a conversion result is he ld until the next d/a c onversion is performed. when the dacen bit of the dam register is set to 0 (d/a conversion operation stop) , d/a conversion stops, the anon pin goes into a high-impedance state when the pm11n bit of the pm11 register = 1 (input mode), and the anon pin outputs the set value of the p11 re gister when the pm11n bit = 0 (output mode). cautions 1. even if 1, 0, and then 1 is set to the dacen bit, there is a wait after 1 is set for the last time. 2. if the dacswn or dacsn register is rewritten du ring the settling time, d/a conversion is aborted and reconversion by using the rewritten values starts. remark n = 0, 1 11.4.2 operation in real-time output mode d/a conversion is performed using the inte rrupt request signals (inttm04 and inttm05) note of timer channels 4 and 5 as triggers. the setting method is described below. note channel 0 of the d/a converter: inttm04 channel 1 of the d/a converter: inttm05 <1> set bit 6 (dacen) of peripheral enable register 0 (per0) to 1 to start the supply of the input clock to the d/a converter. <2> set the damdn bit of the d/a converter mode register (dam) to 0 (normal mode). <3> use the bit 6 (daref) of the dam register to select the d/a converter reference voltage supply on the positive side. <4> use the daresn bit of the dam register to select the resolution of the d/a converter. <5> set the analog voltage value to be output to the anon pin to the d/a conversion value setting register wn (dacswn) or d/a conversion value setting register n (dacsn).
78k0r/lx3 r01uh0004ej0501 rev.5.01 424 jun 20, 2011 chapter 11 d/a converter ( pd78f150xa only) <6> set the dacen bit of the dam regi ster to 1 (d/a conversion enable). after the wait time ( 20 s or more ) elapses, d/a conversion starts, and then, after the settling time (18 s (max.)) elapses, the d/a converted analog voltage value is output from the anon pin. <7> set the damdn bit of the dam r egister to 1 (real-time output mode). steps <1> to <7> above constitute the initial settings. <8> operate timer channel m. <9> generation of the inttm0m signa ls starts d/a conversion and the d/ a converted analog voltage value will be output from the anon pin after a settling time (18 s ( max .)) has elapsed. <10> afterward, the value set to the dacswn or dacsn register will be output at t he generation timing of the inttm0m signals. set the analog voltage value to be output to the anon pin, to the dacswn or dacs n register before performing the next d/a conversion (inttm0m signal are generated). when the dacen bit of the dam register is set to 0 (d /a conversion operation stop) , d/a conversion stops, the anon pin goes into a high-impedance state when the pm11n bit of the pm11 register = 1 (input mode), and the anon pin outputs the set value of the p11 re gister when the pm11n bit = 0 (output mode). cautions 1. even if 1, 0, and then 1 is set to the dace n bit, there is a wait after 1 is set for the last time. 2. make the interval be tween each generation of the inttm0m si gnal longer than the settling time. if an inttm0m signal is generated during the se ttling time, d/a conver sion is aborted and reconversion starts. 3. even if the generation of the inttm0m signal and rewriting the dacswn or dacsn register conflict, the d/a conver sion result is output. remark n = 0, 1 11.5 cautions for d/a converter observe the following cautions when using the d/a converter. (1) the digital port i/o function, which is the alternate f unction of the ano0 and ano1 pins, does not operate during d/a conversion. when the p11 register is read during d/a conversion, 0 is r ead in input mode and the set value of the p11 register is read in output mode. if the digital output mo de is set, no output data is output to pins. (2) the operation of the d/a converter continues in the halt and stop mode. to lower the power consumption, therefore, clear the dacen bit of the dam register to 0 (d/a conversion st op), and execute halt or stop instruction. (3) rewriting dacswn (n = 0, 1) during a/d conversion is pr ohibited when both the positive reference voltage of the a/d converter (ad refp ) and the positive reference voltage of the d/a converter (da refp ) are the voltage reference output (v refout ) (vrsel = 1 and daref = 1). rewrite it when conversion operation is stopped (adcs = 0). remark n = 0, 1, m = 4, 5
78k0r/lx3 r01uh0004ej0501 rev.5.01 425 jun 20, 2011 chapter 12 operational amplifier ( pd78f150xa only) chapter 12 operational amplifier ( pd78f150xa only) 78k0r/lf3 ( pd78f150na: n = 0 to 2) 78k0r/fg3 ( pd78f150na: n = 3 to 5) 78k0r/lh3 ( pd78f150na: n = 6 to 8) item 80 pins 100 pins 128 pins operational amplifier 2 ch (operational amplifiers 0, 1) 3 ch (operational amplifiers 0 to 2) 12.1 function of operational amplifier operational amplifiers are mounted onto products of 78k0r/lx3 microcontrollers . the operational amplifiers have the following modes. ? single amp mode the difference in potential of analog vo ltages input from two pins (ampn ? and ampn+ pins) is amplified and the amplified voltage is output from the ampno pin. the amplified voltage can be used as an analog input of the a/d converter, because the ampno pin is alternatively used with analog input pin of the a/d converter. remark 78k0r/lf3: n = 0, 1 78k0r/lg3, 78k0r/lh3: n = 0 to 2 12.2 configuration of operational amplifier the operational amplifiers consist of the following hardware. table 12-1. configuration of operational amplifiers item configuration operational amplifier input ampn - pin, ampn+ pin operational amplifier output ampno pin control registers peripheral enable register 0 (per0) operational amplifier control register (oac) a/d configuration register (adpc) port mode registers 2, 15 (pm2, pm15) remark 78k0r/lf3: n = 0, 1 78k0r/lg3, 78k0r/lh3: n = 0 to 2
78k0r/lx3 r01uh0004ej0501 rev.5.01 426 jun 20, 2011 chapter 12 operational amplifier ( pd78f150xa only) figure 12-1. block diagram of operational amplifier internal bus oaen0 operational amplifier control register (oac) amp2+/ani8/p150 amp2-/ani6/p26 amp2o/ani7/p27 amp2 amp1+/ani5/p25 amp1-/ani3/p23 amp1o/ani4/p24 amp1 ? + to a/d converter amp0+/ani2/p22 amp0-/ani0/p20 amp0o/ani1/p21 amp0 operational amplifier 0 oaen1 oaen2 oaen1 bit oaen0 bit operational amplifier 1 operational amplifier 2 to a/d converter to a/d converter ? + ? + remark 78k0r/lf3: operational amplifiers 0, 1 78k0r/lg3, 78k0r/lh3: operational amplifiers 0 to 2
78k0r/lx3 r01uh0004ej0501 rev.5.01 427 jun 20, 2011 chapter 12 operational amplifier ( pd78f150xa only) 12.3 amplifier registers used in operational amplifier the operational amplifiers use the following four registers. ? peripheral enable register 0 (per0) ? operational amplifier control register (oac) ? a/d port configuration register (adpc) ? port mode registers 2, 15 (pm2, pm15) (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to reduc e the power consumption and noise. when the operational amplifier is used, be sure to set bit 5 (adcen) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 12-2. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> per0 rtcen dacen adcen iicaen note sau1en sau0en tau1en tau0en adcen control of a/d converter, operational amplifier, and voltage reference input clock 0 stops input clock supply. ? sfr used by the a/d converter, operational amplifier, and voltage reference cannot be written. ? the a/d converter, operational amplifier, and voltage reference is in the reset status. 1 supplies input clock. ? sfr used by the a/d converter, operational amplifier, and voltage reference can be read and written. note 78k0r/lg3, 78k0r/lh3 only caution when setting operational am plifier, be sure to set adcen to 1 first. if adcen = 0, writing to a control register of operational am plifier is ignored, and, even if the register is read, only the default value is read
78k0r/lx3 r01uh0004ej0501 rev.5.01 428 jun 20, 2011 chapter 12 operational amplifier ( pd78f150xa only) (2) operational amplifier control register (oac) this register controls the operations of operational amplifiers 0 to 2. oac can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark 78k0r/lf3: operational amplifiers 0, 1 78k0r/lg3, 78k0r/lh3: operational amplifiers 0 to 2 figure 12-3. format of operational amplifier control register (oac) address: fff33h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 oac 0 0 0 0 0 oaen2 oaen1 oaen0 oaen2 operational amplifier 2 operation control 0 stops operational amplifier 2 operation 1 enables operational amplifier 2 operation oaen1 operational amplifier 1 operation control 0 stops operational amplifier 1 operation 1 enables operational amplifier 1 operation oaen0 operational amplifier 1 operation control 0 stops operational amplifier 0 operation 1 enables operational amplifier 0 operation cautions 1. use the adpc register to specify as analog inpu ts the pins to be used with operational amplifiers. 2. when using as digital inputs the pins of ports 2 and 15, which are not used with operational amplifiers, when the ope rational amplifiers are used, make su re that the inpu t levels are fixed.
78k0r/lx3 r01uh0004ej0501 rev.5.01 429 jun 20, 2011 chapter 12 operational amplifier ( pd78f150xa only) (3) a/d port configuration register (adpc) this register switches the ani0/amp0-/p20 to an i7/amp2o/p27, ani8/amp2+/p150 to ani10/p152, and ani15/av refm /p157 pins to analog input of a/d converter or digi tal i/o of port. set pins to be used with operational amplifiers to the analog input. adpc can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 10h. remark 78k0r/lf3: ani0-ani6, ani15 78k0r/lg3, 78k0r/lh3: ani0-ani10, ani15 figure 12-4. format of a/d port configuration register (adpc) address: f0017h after reset: 10h r/w symbol 7 6 5 4 3 2 1 0 adpc 0 0 0 adpc4 adpc3 adpc2 adpc1 adpc0 analog input (a)/digita l i/o (d) switching port 15 port 2 adp c4 adp c3 adp c2 adp c1 adp c0 ani15 /av refm /p157 ani10 /p152 ani9 /p151 ani8 /amp2+ /p150 ani7 /amp2o /p27 ani6 /amp2- /p26 ani5 /amp1+ /p25 ani4 /amp1o /p24 ani3 /amp1- /p23 ani2 /amp0+ /p22 ani1 /amp0o /p21 ani0 /amp0- /p20 0 0 0 0 0 a a a a a a a a a a a a 0 0 0 0 1 a a a a a a a a a a a d 0 0 0 1 0 a a a a a a a a a a d d 0 0 0 1 1 a a a a a a a a a d d d 0 0 1 0 0 a a a a a a a a d d d d 0 0 1 0 1 a a a a a a a d d d d d 0 0 1 1 0 a a a a a a d d d d d d 0 0 1 1 1 a a a a a d d d d d d d 0 1 0 0 0 a a a a d d d d d d d d 0 1 0 0 1 a a a d d d d d d d d d 0 1 0 1 0 a a d d d d d d d d d d 0 1 1 1 1 a d d d d d d d d d d d 1 0 0 0 0 d d d d d d d d d d d d other than the above setting prohibited note this setting is prohibited for 78k0r/lf3. caution set pins to be used with oper ational amplifiers in the input mode by using port mode registers 2 and 15 (pm2, pm15). note note note note
78k0r/lx3 r01uh0004ej0501 rev.5.01 430 jun 20, 2011 chapter 12 operational amplifier ( pd78f150xa only) (4) port mode registers 2, 15 (pm2, pm15) when using ani0/amp0-/p20 to ani7/amp2o/p 27, ani8/amp2+/p150 to ani10/p152 and ani15/av refm /p157 pins for analog input port, set pm20 to pm27, pm150 to pm152, and p157 to 1. the output latches of p20 to p27, p150 to p152 and p157 at this time may be 0 or 1. if pm20 to pm27, pm150 to pm152 and pm157 are set to 0, they cannot be used as analog input port pins. pm2 and pm15 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh. remark 78k0r/lf3: ani0-ani6, ani15 78k0r/lg3, 78k0r/lh3: ani0-ani10, ani15 caution if a pin is set as an analog input por t, not the pin level bu t ?0? is always read. figure 12-5. formats of port mode registers 2, 15 (pm2, pm15) ? 78k0r/lf3 address: fff22h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm2 1 pm26 pm25 pm24 pm23 pm22 pm21 pm20 address: fff2fh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm15 pm157 1 1 1 1 1 1 1 ? 78k0r/lg3, 78k0r/lh3 address: fff22h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm2 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 address: fff2fh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm15 pm157 1 1 1 1 pm152 pm151 pm150 pmmn pmn pin i/o mode selection (mn = 20 to 27, 150 to 152, 157) 0 output mode (output buffer on) 1 input mode (output buffer off)
78k0r/lx3 r01uh0004ej0501 rev.5.01 431 jun 20, 2011 chapter 12 operational amplifier ( pd78f150xa only) the ani0/amp0-/p20 to ani7/amp2o/p27, an i8/amp2+/p150 to ani10/p152 and ani15/av refm /p157 pins are as shown below depending on the settings of adpc , ads, pm2, pm15, oaenn bit and adref bit. table 12-2. setting functions of ani0/amp0-/p20, ani2/amp0+/p22, ani3/amp1-/p23, ani5/amp1+/p25, ani6/amp2-/p26, and ani8/amp2+/p150 pins adpc register pm2 and pm15 registers oaenn bit ads register ani0/amp0-/p20, ani2/amp0+/p22, ani3/amp1- /p23, ani5/amp1+/p25, ani6/amp2-/p26, and ani8/amp2+/p150 pins 0 ? digital input input mode 1 ? setting prohibited 0 ? digital output digital i/o selection output mode 1 ? setting prohibited selects ani. analog input (to be converted) 0 does not select ani. analog input (not to be converted) selects ani. setting prohibited input mode 1 does not select ani. operational amplifier input analog input selection output mode ? ? setting prohibited remark 78k0r/lf3: ani0/amp0-/p20, ani2/amp0+/p22, ani3/amp1-/p23, ani5/amp1+/p25, n = 0, 1 78k0r/lg3, 78k0r/lh3: ani0/amp0-/p20, ani2/amp0+/p22, ani3/amp1-/p23, ani5/amp1+/p25, ani6/amp2-/p26, ani8/amp2+/p150, n = 0 to 2 caution when an operational amplifier is used, ampn+, ampn ? , and ampno pins are used, so the alternative analog input functions cannot be used. table 12-3. setting functions of ani1/amp0 o/p21, ani4/amp1o/p24, and ani7/amp2o/p27 pins adpc register pm2 register oaenn bit ads register ani1/amp0o/p21, ani4/amp1o/p24, and ani7/amp2o/p27 pins 0 ? digital input input mode 1 ? setting prohibited 0 ? digital output digital i/o selection output mode 1 ? setting prohibited selects ani. analog input (to be converted) 0 does not select ani. analog input (not to be converted) selects ani. operational amplifier output (not to be converted) input mode 1 does not select ani. operational amplifier output (to be converted) analog input selection output mode ? ? setting prohibited remark 78k0r/lf3: ani1/amp0o/p21, ani4/amp1o/p24, n = 0, 1 78k0r/lg3, 78k0r/lh3: ani1/amp0o/p21, ani4 /amp1o/p24, and ani7/amp2o/p27, n = 0 to 2
78k0r/lx3 r01uh0004ej0501 rev.5.01 432 jun 20, 2011 chapter 12 operational amplifier ( pd78f150xa only) caution when an operational amplifier is used, ampn+, ampn ? , and ampno pins are used, so the alternative analog input functions cannot be used. the operational amplifie r output signals, however, can be used as analog inputs. table 12-4. setting functions of ani9/p151 and ani10/am152 pins adpc register pm15 register ads register ani9/p151 and ani10/am152 pins input mode ? digital input digital i/o selection output mode ? digital output selects ani. analog input (to be converted) input mode does not select ani. analog input (not to be converted) analog input selection output mode ? setting prohibited remark 78k0r/lf3: ani9/p151 and ani10/am152 are not mounted. 78k0r/lg3, 78k0r/lh3: ani9/p151, ani10/am152 table 12-5. setting functions of ani15/av refm /p157 pin adpc register pm15 register adref bit ads register ani15/av refm /p157 pin 0 ? digital input input mode 1 ? setting prohibited 0 ? digital output digital i/o selection output mode 1 ? setting prohibited selects ani. analog input (to be converted) 0 does not select ani. analog input (not to be converted) input mode 1 ? negative reference voltage input of a/d converter analog input selection output mode ? ? setting prohibited
78k0r/lx3 r01uh0004ej0501 rev.5.01 433 jun 20, 2011 chapter 12 operational amplifier ( pd78f150xa only) 12.4 operational amplifier operations the operational amplifiers 0 to 2 have the following mode. ? single amp mode (operational amplifiers 0 to 2) 12.4.1 single amp mode in single amplifier mode, the difference in potentia l of analog voltages input from two pins (ampn ? and ampn+ pins) is amplified and the amplified voltage is output from the ampno pin. the gain is determined by externally connecting a resistor or the like. the amplified voltage can be used as an analog input of the a/d converter, because the ampno pin is alternatively used with analog input pin of the a/d converter. the procedure for starting operation in sing le amplifier mode is described below. <1> set bit 5 (adcen) of peripheral enable register 0 (per0) to 1 to start the supply of the input clock to the operational amplifier. <2> use the a/d port confi guration register (adpc) to set the pins (ampn ? , ampn+, ampno) to be used in single amplifier mode as analog inputs. <3> use the port mode register x (pmx) to set the pins (ampn ? , ampn+, ampno) to be used in single amplifier mode to input mode. <4> set (1) the oaenn bit of operational amplifier control regi ster (oac) and enable operation in single amplifier mode. <5> use software to wait until the operatio nal amplifier stabilizes (turn-on time: 20 s (max.)). caution to use as an input of the a/d converter a voltage that has been amplified in single amplifier mode, enable operation in single amplifie r mode before selecting an analog input channel by using the ads register. remark 78k0r/lf3: n = 0, 1, x = 2 78k0r/lg3, 78k0r/lh3: n = 0 to 2, x = 2, 15
78k0r/lx3 r01uh0004ej0501 rev.5.01 434 jun 20, 2011 chapter 13 voltage reference ( pd78f150xa only) chapter 13 voltage reference ( pd78f150xa only) 13.1 function of voltage reference the voltage reference is mounted onto all 78k0r/lx3 mi crocontroller products. the voltage reference has the following modes. ? reference voltage output mode a reference voltage is output from the v refout pin. furthermore, the generated re ference voltage is supplied to the internal a/d and d/a converters. 2.0 v (typ.) or 2.5 v (typ.) can be sele cted as the output voltage. 13.2 configuration of voltage reference the voltage reference consists of the following hardware. table 13-1. configuration of voltage reference item configuration reference voltage output v refout pin control registers peripheral enable registers 0 (per0) analog reference voltage control register (advrc) figure 13-1. block diagra m of voltage reference internal bus vrgv analog reference voltage control register (advrc) v refout /av refp vron voltage reference circuit positive reference voltage of a/d converter and d/a converter vrsel
78k0r/lx3 r01uh0004ej0501 rev.5.01 435 jun 20, 2011 chapter 13 voltage reference ( pd78f150xa only) 13.3 amplifier registers used in voltage reference the voltage reference uses the following two registers. ? peripheral enable register 0 (per0) ? analog reference voltage control register (advrc) (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to reduc e the power consumption and noise. when the voltage reference is used, be sure to set bit 5 (adcen) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 13-2. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> per0 rtcen dacen adcen iicaen note sau1en sau0en tau1en tau0en adcen control of a/d converter, operational amplifier, and voltage reference input clock 0 stops input clock supply. ? sfr used by the a/d converter, operational amplifier, and voltage reference cannot be written. ? the a/d converter, operational amplifier, and voltage reference is in the reset status. 1 supplies input clock. ? sfr used by the a/d converter, operational amplifier, and voltage reference can be read and written. note 78k0r/lg3, 78k0r/lh3 only caution when setting voltage referen ce, be sure to set adcen to 1 first. if adcen = 0, writing to a control register of voltage reference is igno red, and, even if the register is read, only the default value is read. (2) analog reference voltage control register (advrc) this register is used to select the reference voltage suppl ies of the a/d and d/a conver ters, control the operation of the input gate voltage boost circuit for the a/d converte r, and control the voltage reference (vr) operation. advrc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h.
78k0r/lx3 r01uh0004ej0501 rev.5.01 436 jun 20, 2011 chapter 13 voltage reference ( pd78f150xa only) figure 13-3. format of analog referen ce voltage control register (advrc) address: fff36h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 advrc adref 0 0 0 vrsel 0 vrgv vron adref negative reference voltage supply of a/d converter selection 0 av ss 1 av refm (external voltage reference input) vrsel vrgv vron positive reference voltage supplies selection of a/d and d/a converters operation control of voltage reference output voltage selection of voltage reference operation control of input gate voltage boost circuit for a/d converter relationship with the conversion mode used 0 0 0 2.5 v stops operation can be set in normal mode 1. 0 1 0 av refp (external voltage reference input) stops operation (hi-z) 2.0 v enables operation can be set in normal mode 2 or low voltage mode. 1 0 0 stops operation (pull-down output) 2.5 v stops operation ? 1 0 1 enables operation 2.5 v can be set in normal mode 2 or low voltage mode. 1 1 0 stops operation (pull-down output) 2.0 v ? 1 1 1 v refout (voltage reference output) enables operation 2.0 v enables operation can be set in normal mode 2 or low voltage mode. other than the above setting prohibited cautions 1. during voltage reference operation, be sure to connect a tantalum capacitor (capacitance: 10 f 30 %, esr: 2 (max.), esl: 10 nh (max.)) and a ceramic capacitor ( capacitance: 0.1 f 30 %, esr: 2 (max.), esl: 10 nh (max.)) to the v refout /av refp pin for stabilizing the reference voltage. furthermore, do not apply a voltage from the v refout /av refp pin during voltage reference operation. 2. to use voltage reference output (v refout ) to the positive reference vo ltage of the a/d converter (ad refp ) and the positive reference volt age of the d/a converter (da refp ), be sure to set vron to 1 after setting vrsel to 1.
78k0r/lx3 r01uh0004ej0501 rev.5.01 437 jun 20, 2011 chapter 13 voltage reference ( pd78f150xa only) cautions 3. rewriting dacswn (n = 0, 1) during a/ d conversion is prohibited when both the positive reference voltage of the a/d converter (ad refp ) and the positive refere nce voltage of the d/a converter (da refp ) are the voltage reference output (v refout ) (vrsel = 1 and daref = 1). rewrite it when conversion ope ration is stopped (adcs = 0). 4. do not change the output vo ltage of the reference voltage by using vrgv during the voltage reference operation (vron = 1). 13.4 voltage reference operations the voltage reference has the following mode. ? reference voltage output mode a reference voltage is output from the v refout pin. furthermore, the generated re ference voltage is supplied to the internal a/d and d/a converters. 2.0 v (typ.) or 2.5 v (typ.) can be sele cted as the output voltage. 13.4.1 reference voltage output mode the procedure for starting operation is described below. <1> set bit 5 (adcen) of peripheral enable register 0 (per0) to 1 to start the supply of the input clock to the voltage reference. <2> set bit 3 (vrsel) of the analog reference voltage control re gister (advrc) to 1. the positive reference voltage of both the a/d and d/a converters or only the a/d converter is set to voltage reference output. <3> specify the reference voltage val ue by using bit 1 (vrgv) of advrc. <4> enable voltage reference operation by setting bit 0 (vron) of advrc to 1. <5> use software to wait until the voltage referenc e operation stabilizes (settling time: 17 ms (max.)). 13.5 cautions for voltage reference observe the following cautions when using the voltage reference. ? the v refout output voltage can be used only as the positive reference voltage of t he internal a/d and d/a converters of the microcontroller. do not connect an external ci rcuit other than a tantalum capacitor (capacitance: 10 f 30 %, esr: 2 (max.), esl: 10 nh (max.)) and a ceramic capacitor (capacitance: 0.1 f 30 %, esr: 2 (max.), esl: 10 nh (max.)) to the v refout pin for stabilizing the reference voltage.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 438 jun 20, 2011 chapter 14 serial array unit the serial array unit has four serial channels per unit and can us e two or more of various serial interfaces (3-wire serial (csi), uart, and simplified i 2 c) in combination. function assignment of each channel su pported by the 78k0r/lx3 microcontroll ers is as shown below (channels 2 and 3 of unit 1 are dedicated to uart3 (supporting lin-bus)). ? 78k0r/lf3 unit channel used as csi used as uart used as simplified i 2 c 2 csi10 iic10 0 3 ? uart1 ? 0 csi20 iic20 1 ? uart2 ? 2 ? ? 1 3 ? uart3 (supporting lin-bus) ? ? 78k0r/lg3 unit channel used as csi used as uart used as simplified i 2 c 0 csi00 ? 1 ? uart0 ? 2 csi10 iic10 0 3 ? uart1 ? 0 csi20 iic20 1 ? uart2 ? 2 ? ? 1 3 ? uart3 (supporting lin-bus) ? ? 78k0r/lh3 unit channel used as csi used as uart used as simplified i 2 c 0 csi00 ? 1 csi01 uart0 ? 2 csi10 iic10 0 3 ? uart1 ? 0 csi20 iic20 1 ? uart2 ? 2 ? ? 1 3 ? uart3 (supporting lin-bus) ? (example of combination) when ?uart0? is used for c hannels 0 and 1 of unit 0, csi00 and csi01 cannot be used, but csi10, uart1, or iic10 can be used.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 439 jun 20, 2011 14.1 functions of serial array unit each serial interface supported by the 78k0r/lx3 microcontrollers has the following features. 14.1.1 3-wire serial i/o (csi00, csi01, csi10, csi20) this is a clocked communication function that uses thr ee lines: serial clock (sck) and serial data (si and so) lines. [data transmission/reception] ? data length of 7 or 8 bits ? phase control of transmit/receive data ? msb/lsb first selectable ? level setting of transmit/receive data [clock control] ? master/slave selection ? phase control of i/o clock ? setting of transfer period by prescaler and internal counter of each channel [interrupt function] ? transfer end interrupt/buffer empty interrupt [error detection flag] ? overrun error 14.1.2 uart (uart0, uart1, uart2, uart3) this is a start-stop synchronization function using two lines: serial data transmission (t x d) and serial data reception (r x d) lines. it transmits or receives data in asynchroniza tion with the party of communication (by using an internal baud rate). full-duplex uart communication can be realized by using two channels, one dedicated to transmission (even channel) and the other to reception (odd channel). [data transmission/reception] ? data length of 5, 7, or 8 bits ? select the msb/lsb first ? level setting of transmit/recei ve data and select of reverse ? parity bit appending and parity check functions ? stop bit appending [interrupt function] ? transfer end interrupt/buffer empty interrupt ? error interrupt in case of framing error, parity error, or overrun error [error detection flag] ? framing error, parity error, or overrun error the lin-bus is accepted in uart 3 (2 and 3 channels of unit 1) [lin-bus functions] ? wakeup signal detection ? sync break field (sbf) detection ? sync field measurement, baud rate calculation external interrupt (intp0) or timer array unit (tau) is used.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 440 jun 20, 2011 14.1.3 simplified i 2 c (iic10, iic20) this is a clocked communication function to communicate wit h two or more devices by using two lines: serial clock (scl) and serial data (sda). this simplified i 2 c is designed for single communica tion with a device such as eeprom, flash memory, or a/d converter, and ther efore, it functions only as a master an d does not have a function to detect wait states. make sure by using software, as well as operating the control registers, that the ac specif ications of the start and stop conditions are observed. [data transmission/reception] ? master transmission, master reception (onl y master function with a single master) ? ack output function note and ack detection function ? data length of 8 bits (when an address is transmitted, t he address is specified by the higher 7 bits, and the least significant bit is used for r/w control.) ? manual generation of start condition and stop condition [interrupt function] ? transfer end interrupt [error detection flag] ? parity error (ack error) [functions not supported by simplified i 2 c] ? slave transmission, slave reception ? arbitration loss detection function ? wait detection functions note an ack is not output when the la st data is being received by writing 0 to the soemn (soem register) bit and stopping the output of serial communication data. see 14.7.3 (2) processing flow for details. remarks 1. to use an i 2 c bus of full function, see chapter 15 serial interface iica . 2. m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 02, 10
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 441 jun 20, 2011 14.2 configuration of serial array unit serial array unit includes the following hardware. table 14-1. configuration of serial array unit item configuration shift register 8 bits buffer register lower 8 bits of serial data register mn (sdrmn) note serial clock i/o sck00, sck01, sck10, sck20 pins (for 3-wire serial i/o), scl10, scl20 pins (for simplified i 2 c) serial data input si00, si01, si10, si20 pins (for 3-wire serial i/o), r x d0, r x d1, r x d2 pins (for uart), r x d3 pin (for uart supporting lin-bus) serial data output so00, so01, so10, so20 pins (for 3-wire serial i/o), t x d0, t x d1, t x d2 pins (for uart), t x d3 pin (for uart supporting lin-bus), output controller serial data i/o sda10, sda20 pins (for simplified i 2 c) ? peripheral enable register 0 (per0) ? serial clock select register m (spsm) ? serial channel enable status register m (sem) ? serial channel start register m (ssm) ? serial channel stop register m (stm) ? serial output enable register m (soem) ? serial output register m (som) ? serial output level register m (solm) ? input switch control register (isc) ? noise filter enable register 0 (nfen0) control registers ? serial data register mn (sdrmn) ? serial mode register mn (smrmn) ? serial communication operation setting register mn (scrmn) ? serial status register mn (ssrmn) ? serial flag clear trigger register mn (sirmn) ? port input mode registers 1, 7 (pim1, pim7) ? port output mode registers 1, 7, 8 (pom1, pom7, pom8) ? port mode registers 1, 5, 7, 8 (pm1, pm5, pm7, pm8) ? port registers 1, 5, 7, 8 (p1, p5, p7, p8) note the lower 8 bits of the serial data register mn (sdrm n) can be read or written as the following sfr, depending on the communication mode. ? csip communication ? siop (csip data register) ? uartq reception ? rxdq (uartq receive data register) ? uartq transmission ? txdq (uartq transmit data register) ? iicr communication ? sior (iicr data register) remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3), p: csi number (p = 00, 01, 10, 20), q: uart number (q = 0 to 3), r: iic number (r = 10, 20)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 442 jun 20, 2011 figure 14-1 shows the block diagram of serial array unit 0. figure 14-1. block diagram of serial array unit 0 serial data input pin (when csi01: si01) serial transfer end interrupt (when csi01: intcsi01) (when uart0: intsr0) serial clock select register 0 (sps0) prs 013 4 prs 003 prs 012 prs 011 prs 010 prs 002 prs 001 prs 000 4 f clk f clk /2 0 to f clk /2 11 selector f clk /2 0 to f clk /2 11 selector cks00 md001 ccs00 sts00 md002 mode selection csi00 or uart0 (for transmission) edge detection communication controller shift register serial data register 00 (sdr00) interrupt controller edge/level detection serial output register 0 (so0) 0 soe02 soe01 soe00 serial output enable register 0 (soe0) serial clock i/o pin (when csi00: sck00) pm80 sau0en peripheral enable register 0 (per0) serial data input pin (when csi00: si00) (when uart0: rxd0) serial data output pin (when csi00: so00) (when uart0: t x d0) serial mode register 00 (smr00) se03 se02 se01 se00 serial channel enable status register 0 (se0) st03 st02 st01 st00 serial channel stop register 0 (st0) ss03 ss02 ss01 ss00 serial channel start register 0 (ss0) (buffer register block) (clock division setting block) error controller txe 00 rxe 00 dap 00 ckp 00 serial communication operation setting register 00 (scr00) eoc 00 fect 00 pect 00 serial flag clear trigger register 00 (sir00) ovct 00 ptc 001 slc 000 ptc 000 dir 00 slc 001 dls 002 dls 001 dls 000 tsf 00 ovf 00 bff 00 fef 00 pef 00 serial status register 00 (ssr00) output controller serial transfer end interrupt (when csi00: intcsi00) (when uart0: intst0) error information clear channel 0 mode selection csi01 or uart0 (for reception) communication controller channel 1 serial data input pin (when csi10: si10) (when iic10: sda10) (when uart1: r x d1) serial data output pin (when csi10: so10) (when iic10: sda10) (when uart1: t x d1) serial transfer end interrupt (when csi10: intcsi10) (when iic10: intiic10) (when uart1: intst1) mode selection csi10 or iic10 or uart1 (for transmission) communication controller channel 2 mode selection uart1 (for reception) communication controller channel 3 ck01 inttm02 ck00 mck tclk sck output latch (p80) serial clock i/o pin (when csi10: sck10) (when iic10: scl10) serial transfer error interrupt (intsre0) serial transfer end interrupt (when uart1: intsr1) serial transfer error interrupt (intsre1) serial data output pin (when csi01: so01) serial clock i/o pin (when csi01: sck01) ck01 ck00 ck01 ck00 ck01 ck00 snfen 10 noise filter enable register 0 (nfen0) snfen 00 noise elimination enabled/ disabled snfen00 edge/level detection selector when uart0 edge/level detection edge/level detection noise elimination enabled/ disabled snfen10 when uart1 pm82 output latch (p82) 0 sol02 0 sol00 serial output level register 0 (sol0) error controller error controller selector clock controller selector communication status prescaler 1 1 cko02 cko01 cko00 so02 so01 so00 0 0 00 0 0 00 remarks 1. for 78k0r/lf3, the channels 0 and 1 are not mounted. 2. for 78k0r/lg3, csi01 is not mounted.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 443 jun 20, 2011 figure 14-2 shows the block diagram of serial array unit 1. figure 14-2. block diagram of serial array unit 1 serial clock select register 1 (sps1) prs 113 4 prs 103 prs 112 prs 111 prs 110 prs 102 prs 101 prs 100 4 f clk f clk /2 0 to f clk /2 11 selector f clk /2 0 to f clk /2 11 selector cks10 md101 ccs10 sts10 md102 mode selection csi20 or iic20 or uart2 (for transmission) communication controller shift register serial data register 10 (sdr10) interrupt controller serial output register 1 (so1) sau1en peripheral enable register 0 (per0) serial data output pin (when csi20: so20) (when iic20: sda20) (when uart2: txd2) serial mode register 10 (smr10) (buffer register block) (clock division setting block) error controller txe 10 rxe 10 dap 10 ckp 10 serial communication operation setting register 10 (scr10) eoc 10 fect 10 pect 10 serial flag clear trigger register 10 (sir10) ovct 10 ptc 101 slc 100 ptc 100 dir 10 slc 101 dls 102 dls 101 dls 100 tsf 10 ovf 10 bff 10 fef 10 pef 10 serial status register 10 (ssr10) output controller serial transfer end interrupt (when csi20: intcsi20) (when iic20: intiic20) (when uart2: intst2) error information clear channel 0 ck11 ck10 mck tclk serial transfer end interrupt (when uart3: intsr3) serial transfer error interrupt (intsre3) mode selection uart2 (for reception) communication controller channel 1 mode selection uart3 (for transmission) communication controller channel 2 (lin-bus supported) mode selection uart3 (for reception) communication controller channel 3 (lin-bus supported) serial transfer end interrupt (when uart2: intsr2) serial transfer error interrupt (intsre2) serial data output pin (when uart3: t x d3) serial transfer end interrupt (when uart3: intst3) ck11 ck10 ck11 ck10 ck11 ck10 edge detection serial clock i/o pin (when csi20: sck20) (when iic20: scl20) pm10 sck output latch (p10) edge/level detection serial data input pin (when csi20: si20) (when iic20: sda20) (when uart2: rxd2) noise elimination enabled/ disabled snfen20 snfen 30 noise filter enable register 0 (nfen0) snfen 20 edge/level detection serial data input pin (when uart3: rxd3) snfen30 when uart3 edge/level detection when uart2 noise elimination enabled/ disabled pm11 or pm12 output latch ( p11 or p12) 0 soe12 0 soe10 serial output enable register 1 (soe1) se13 se12 se11 se10 serial channel enable status register 1 (se1) st13 st12 st11 st10 serial channel stop register 1 (st1) ss13 ss12 ss11 ss10 serial channel start register 1 (ss1) 0 sol12 0 sol10 serial output level register 1 (sol1) error controller error controller selector clock controller selector communication status inttm03 prescaler 11 1 1 cko10 so12 1 so10 000 0 000 0
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 444 jun 20, 2011 (1) shift register this is an 8-bit register that converts para llel data into serial data or vice versa. during reception, it converts data inpu t to the serial pin into parallel data. when data is transmitted, the value set to this register is output as serial data from the serial output pin. the shift register cannot be dire ctly manipulated by program. to read or write the shift register, use the lowe r 8 bits of serial data register mn (sdrmn). 7 6 5 4 3 2 1 0 shift register (2) lower 8 bits of the serial data register mn (sdrmn) sdrmn is the transmit/receive data regist er (16 bits) of channel n. bits 7 to 0 function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (mck). when data is received, parallel data conver ted by the shift register is stored in the lower 8 bits. when data is to be transmitted, set transmit to be transferred to the shift register to the lower 8 bits. the data stored in the lower 8 bits of th is register is as follows, depending on the setting of bits 0 to 2 (dlsmn0 to dlsmn2) of the scrmn register, regardle ss of the output sequ ence of the data. ? 5-bit data length (stored in bits 0 to 4 of sdrmn register) (settable in uart mode only) ? 7-bit data length (stored in bits 0 to 6 of sdrmn register) ? 8-bit data length (stored in bits 0 to 7 of sdrmn register) sdrmn can be read or written in 16-bit units. the lower 8 bits of sdrmn of sdrmn can be read or written note as the following sfr, depending on the communication mode. ? csip communication ? siop (csip data register) ? uartq reception ? rxdq (uartq receive data register) ? uartq transmission ? txdq (uartq transmit data register) ? iicr communication ? sior (iicr data register) reset signal generation clears this register to 0000h. remarks 1. after data is received, ?0? is stored in bits 0 to 7 in bit portions that exceed the data length. 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 3), p: csi number (p = 00, 01, 10, 20), q: uart number (q = 0 to 3), r: iic number (r = 10, 20) note writing in 8-bit units is prohibited when the operation is stopped (semn = 0).
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 445 jun 20, 2011 figure 14-3. format of serial data register mn (sdrmn) address: fff10h, fff11h (sdr00), fff12h, fff13h (sdr01), after reset: 0000h r/w fff44h, fff45h (sdr02), fff46h, fff47h (sdr03), fff48h, fff49h (sdr10), fff4ah, fff4bh (sdr11), fff14h, fff15h (sdr12), fff16h, fff17h (sdr13) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn 0 (m = 0, 1; n = 0 to 3) 7 6 5 4 3 2 1 0 shift register caution be sure to clear bit 8 to ?0?. remarks 1. for the function of the hi gher 7 bits of sdrmn, see 14.3 registers controlling serial array unit . 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 3), p: csi number (p = 00, 01, 10, 20), q: uart number (q = 0 to 3), r: iic number (r = 10, 20) fff11h (sdr00) fff10h (sdr00)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 446 jun 20, 2011 14.3 registers controlling serial array unit serial array unit is controlled by the following registers. ? peripheral enable register 0 (per0) ? serial clock select register m (spsm) ? serial mode register mn (smrmn) ? serial communication operation setting register mn (scrmn) ? serial data register mn (sdrmn) ? serial status register mn (ssrmn) ? serial flag clear trigger register mn (sirmn) ? serial channel enable status register m (sem) ? serial channel start register m (ssm) ? serial channel stop register m (stm) ? serial output enable register m (soem) ? serial output level register m (solm) ? serial output register m (som) ? input switch control register (isc) ? noise filter enable register 0 (nfen0) ? port input mode registers 1, 7 (pim1, pim7) ? port output mode registers 1, 7, 8 (pom1, pom7, pom8) ? port mode registers 1, 5, 7, 8 (pm1, pm5, pm7, pm8) ? port registers 1, 5, 7, 8 (p1, p5, p7, p8) remark m: unit number (m = 0, 1) n: channel number (n = 0 to 3)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 447 jun 20, 2011 (1) peripheral enable register 0 (per0) per0 is used to enable or disable use of each peripheral hardware macro. clock supply to a hardware macro that is not used is stopped in order to r educe the power consumption and noise. when serial array unit 0 is used, be sure to set bit 2 (sau0en) of this register to 1. when serial array unit 1 is used, be sure to set bit 3 (sau1en) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 14-4. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> per0 rtcen dacen adcen iicaen note sau1en sau0en tau1en tau0en saumen control of serial array unit m input clock 0 stops supply of input clock. ? sfr used by serial array unit m cannot be written. ? serial array unit m is in the reset status. 1 supplies input clock. ? sfr used by serial array unit m can be read/written. note 78k0r/lg3, 78k0r/lh3 only cautions 1. when setting serial array uni t m, be sure to set saumen to 1 first. if saumen = 0, writing to a control register of serial array unit m is ignored, and, even if the register is read, only the default value is read (except for input switch cont rol register (isc), noise filter enable register (nfen0), port input mode registers (pim1, pi m7), port output mode registers (pom1, pom7, pom8), port mode registers (pm1, pm5, pm7, pm8), and port registers (p1, p5, p7, p8)). 2. after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. remark m: unit number (m = 0, 1) (2) serial clock select register m (spsm) spsm is a 16-bit register that is used to select two types of operation clocks (ckm 0, ckm1) that are commonly supplied to each channel. ckm1 is selected by bits 7 to 4 of spsm, and ckm0 is selected by bits 3 to 0. rewriting spsm is prohibited when the register is in operation (when semn = 1). spsm can be set by a 16-bit memory manipulation instruction. the lower 8 bits of spsm can be set with an 8-bi t memory manipulation instruction with spsml. reset signal generation clears this register to 0000h.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 448 jun 20, 2011 figure 14-5. format of serial clock select register m (spsm) address: f0126h, f0127h (sps0), f0166h, f0167h (sps1) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spsm 0 0 0 0 0 0 0 0 prs m13 prs m12 prs m11 prs m10 prs m03 prs m02 prs m01 prs m00 section of operation clock (ckmp) note 1 prs mp3 prs mp2 prs mp1 prs mp0 f clk = 2 mhz f clk = 5 mhz f clk = 10 mhz f clk = 20 mhz 0 0 0 0 f clk 2 mhz 5 mhz 10 mhz 20 mhz 0 0 0 1 f clk /2 1 mhz 2.5 mhz 5 mhz 10 mhz 0 0 1 0 f clk /2 2 500 khz 1.25 mhz 2.5 mhz 5 mhz 0 0 1 1 f clk /2 3 250 khz 625 khz 1.25 mhz 2.5 mhz 0 1 0 0 f clk /2 4 125 khz 313 khz 625 khz 1.25 mhz 0 1 0 1 f clk /2 5 62.5 khz 156 khz 313 khz 625 khz 0 1 1 0 f clk /2 6 31.3 khz 78.1 khz 156 khz 313 khz 0 1 1 1 f clk /2 7 15.6 khz 39.1 khz 78.1 khz 156 khz 1 0 0 0 f clk /2 8 7.81 khz 19.5 khz 39.1 khz 78.1 khz 1 0 0 1 f clk /2 9 3.91 khz 9.77 khz 19.5 khz 39.1 khz 1 0 1 0 f clk /2 10 1.95 khz 4.88 khz 9.77 khz 19.5 khz 1 0 1 1 f clk /2 11 977 hz 2.44 khz 4.88 khz 9.77 khz 1 1 1 1 inttm02 if m = 0, inttm03 if m = 1 note 2 other than above setting prohibited notes 1. when changing the clock selected for f clk (by changing the system clock control register (ckc) value), do so after having stopped (stm = 000fh) the operation of the serial array unit (saum). when selecting inttm02 and inttm03 for the operation clock, also stop the timer array unit (tau0) (tt0 = 00ffh). 2. saum can be operated at a fixed division rati o of the subsystem clock, regardless of the f clk frequency (main system clock, subsystem clock), by operating the interval timer for which f sub /4 has been selected as the count clock (setting tis02 (if m = 0) or tis03 (if m = 1) of the tis0 register to 1) and selecting inttm02 and inttm03 by using the spsm register in channels 2 and 3 of tau0. when changing f clk , however, saum and tau0 must be stopped as described in note 1 above. cautions 1. be sure to clear bits 15 to 8 to ?0?. 2. after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. remarks 1. f clk : cpu/peripheral hardware clock frequency f sub : subsystem clock frequency 2. m: unit number (m = 0, 1), p = 0, 1
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 449 jun 20, 2011 (3) serial mode register mn (smrmn) smrmn is a register that se ts an operation mode of channel n. it is also used to select an operation clock (mck), specify whether the serial clock (sck) may be input or not, set a start trigger, an operation mode (csi, uart, or i 2 c), and an interrupt source. this register is also used to invert the level of the receive data only in the uart mode. rewriting smrmn is prohibited when the register is in operation (when semn = 1). however, the mdmn0 bit can be rewritten during operation. smrmn can be set by a 16-bit memory manipulation instruction. reset signal generation sets this register to 0020h. figure 14-6. format of serial m ode register mn (smrmn) (1/2) address: f0110h, f0111h (smr00) to f0116h, f0117h (smr03), after reset: 0020h r/w f0150h, f0151h (smr10), f0152h, f0153h (smr11), f0154h, f0155h (smr12), f0156h, f0157h (smr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cks mn ccs mn 0 0 0 0 0 sts mn 0 sis mn0 1 0 0 md mn2 md mn1 md mn0 cks mn selection of operation cl ock (mck) of channel n 0 prescaler output clock ckm0 set by spsm register 1 prescaler output clock ckm1 set by spsm register operation clock mck is used by the edge detector. in addition, depending on the setting of the ccsmn bit and the higher 7 bits of the sdrmn register, a transfer clock (tclk) is generated. ccs mn selection of transfer clock (tclk) of channel n 0 divided operation clock mck specified by cksmn bit 1 clock input from sck pin (slave transfer in csi mode) transfer clock tclk is used for the sh ift register, communication controller, output controller, interrupt controller, and error controller. when ccsmn = 0, the division ratio of mck is set by the higher 7 bits of the sdrmn register. sts mn selection of start trigger source 0 only software trigger is valid (selected for csi, uart transmission, and simplified i 2 c). 1 valid edge of r x d pin (selected for uart reception) transfer is started when the above source is satisfied after 1 is set to the ssm register. caution be sure to clear bits 13 to 9, 7, 4, and 3 to ?0?. be sure to set bit 5 to ?1?. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 450 jun 20, 2011 figure 14-6. format of serial m ode register mn (smrmn) (2/2) address: f0110h, f0111h (smr00) to f0116h, f0117h (smr03), after reset: 0020h r/w f0150h, f0151h (smr10), f0152h, f0153h (smr11), f0154h, f0155h (smr12), f0156h, f0157h (smr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cks mn ccs mn 0 0 0 0 0 sts mn 0 sis mn0 1 0 0 md mn2 md mn1 md mn0 sis mn0 controls inversion of level of receive data of channel n in uart mode 0 falling edge is detected as the start bit. the input communication data is captured as is. 1 rising edge is detected as the start bit. the input communication data is inverted and captured. md mn2 md mn1 setting of operation mode of channel n 0 0 csi mode 0 1 uart mode 1 0 simplified i 2 c mode 1 1 setting prohibited md mn0 selection of interrupt source of channel n 0 transfer end interrupt 1 buffer empty interrupt for successive transmission, the next transmit data is written by setting mdmn0 to 1 when sdrmn data has run out. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 451 jun 20, 2011 (4) serial communication operation setting register mn (scrmn) scrmn is a communication operation setting register of channel n. it is used to set a data transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data length. rewriting scrmn is prohibited when the register is in operation (when semn = 1). scrmn can be set by a 16-bit memory manipulation instruction. reset signal generation sets this register to 0087h. figure 14-7. format of serial communication operation setting register mn (scrmn) (1/3) address: f0118h, f0119h (scr00) to f011eh, f011fh (scr03), after reset: 0087h r/w f0158h, f0159h (scr10), f015ah, f015bh (scr11), f015ch, f015dh (scr12), f015eh, f015fh (scr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txe mn rxe mn dap mn ckp mn 0 eoc mn ptc mn1 ptc mn0 dir mn 0 slc mn1 slc mn0 0 dls mn2 dls mn1 dls mn0 txe mn rxe mn setting of operation mode of channel n 0 0 does not start communication. 0 1 reception only 1 0 transmission only 1 1 transmission/reception dap mn ckp mn selection of data and clock phase in csi mode type 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sckp sop si p input timing 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sckp sop si p input timing 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sckp sop si p input timing 3 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sckp sop si p input timing 4 be sure to set dapmn, ckpmn = 0, 0 in the uart mode and simplified i 2 c mode. caution be sure to clear bits 3, 6, and 11 to ?0?. be sure to set bit 2 to ?1?. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3), p: csi number (p = 00, 01, 10, 20)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 452 jun 20, 2011 figure 14-7. format of serial communication operation setting register mn (scrmn) (2/3) address: f0118h, f0119h (scr00) to f011eh, f011fh (scr03), after reset: 0087h r/w f0158h, f0159h (scr10), f015ah, f015bh (scr11), f015ch, f015dh (scr12), f015eh, f015fh (scr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txe mn rxe mn dap mn ckp mn 0 eoc mn ptc mn1 ptc mn0 dir mn 0 slc mn1 slc mn0 0 dls mn2 dls mn1 dls mn0 eoc mn selection of masking of error interr upt signal (intsrex (x = 0 to 3)) 0 masks error interrupt intsrex (intsrx is not masked). 1 enables generation of error interrupt intsre x (intsrx is masked if an error occurs). set eocmn = 0 in the csi mode, simplified i 2 c mode, and during uart transmission. note set eocmn = 1 during uart reception. setting of parity bit in uart mode ptc mn1 ptc mn0 transmission reception 0 0 does not output the parity bit. receives without parity 0 1 outputs 0 parity. no parity judgment 1 0 outputs even parity. judged as even parity. 1 1 outputs odd parity. judges as odd parity. be sure to set ptcmn1, ptcmn0 = 0, 0 in the csi mode and simplified i 2 c mode. dir mn selection of data transfer sequence in csi and uart modes 0 inputs/outputs data with msb first. 1 inputs/outputs data with lsb first. be sure to clear dirmn = 0 in the simplified i 2 c mode. slc mn1 slc mn0 setting of stop bit in uart mode 0 0 no stop bit 0 1 stop bit length = 1 bit 1 0 stop bit length = 2 bits 1 1 setting prohibited when the transfer end interrupt is selected, the interr upt is generated when all stop bits have been completely transferred. set 1 bit (slcmn1, slcmn0 = 0, 1) during uart reception and in the simplified i 2 c mode. set no stop bit (slcmn1, slcmn0 = 0, 0) in the csi mode. note when using csi01 not with eoc01 = 0, error interrupt intsre0 may be generated. caution be sure to clear bits 3, 6, and 11 to ?0?. be sure to set bit 2 to ?1?. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 453 jun 20, 2011 figure 14-7. format of serial communication operation setting register mn (scrmn) (3/3) address: f0118h, f0119h (scr00) to f011eh, f011fh (scr03), after reset: 0087h r/w f0158h, f0159h (scr10), f015ah, f015bh (scr11), f015ch, f015dh (scr12), f015eh, f015fh (scr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txe mn rxe mn dap mn ckp mn 0 eoc mn ptc mn1 ptc mn0 dir mn 0 slc mn1 slc mn0 0 dls mn2 dls mn1 dls mn0 dls mn2 dls mn1 dls mn0 setting of data length in csi and uart modes 1 0 0 5-bit data length (stored in bits 0 to 4 of sdrmn register) (settable in uart mode only) 1 1 0 7-bit data length (stored in bits 0 to 6 of sdrmn register) 1 1 1 8-bit data length (stored in bits 0 to 7 of sdrmn register) other than above setting prohibited be sure to set dlsmn0 = 1 in the simplified i 2 c mode. caution be sure to clear bits 3, 6, and 11 to ?0?. be sure to set bit 2 to ?1?. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 454 jun 20, 2011 (5) higher 7 bits of the serial data register mn (sdrmn) sdrmn is the transmit/receive data regist er (16 bits) of channel n. bits 7 to 0 function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (mck). if the ccsmn bit of serial mode register mn (smrmn) is clear ed to 0, the clock set by dividing the operating clock by the higher 7 bits of sdrmn is used as the transfer clock. for the function of the lower 8 bits of sdrmn, see 14.2 configuration of serial array unit . sdrmn can be read or written in 16-bit units. however, the higher 7 bits can be written or read only when the operation is stopped (semn = 0). during operation (semn = 1), a value is written only to the lower 8 bits of sdrmn. when sdrmn is r ead during operation, 0 is always read. reset signal generation clears this register to 0000h. figure 14-8. format of serial data register mn (sdrmn) address: fff10h, fff11h (sdr00), fff12h, fff13h (sdr01), after reset: 0000h r/w fff44h, fff45h (sdr02), fff46h, fff47h (sdr03), fff48h, fff49h (sdr10), fff4ah, fff4bh (sdr11), fff14h, fff15h (sdr12), fff16h, fff17h (sdr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn 0 sdrmn[15:9] transfer clock setting by dividing the oper ating clock (mck) 0 0 0 0 0 0 0 mck/2 0 0 0 0 0 0 1 mck/4 0 0 0 0 0 1 0 mck/6 0 0 0 0 0 1 1 mck/8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 mck/254 1 1 1 1 1 1 1 mck/256 cautions 1. be sure to clear bit 8 to ?0?. 2. setting sdrmn[15:9] = (0000000b, 0000001 b) is prohibited when uart is used. 3. setting sdrmn[15:9] = 0000000b is prohibited when the simplified i 2 c is used. set sdrmn[15:9] to 0000001b or greater. remarks 1. for the function of the lower 8 bits of sdrmn, see 14.2 configuration of serial array unit . 2. m: unit number (m = 0, 1) n: channel number (n = 0 to 3) fff11h (sdr00) fff10h (sdr00)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 455 jun 20, 2011 (6) serial status register mn (ssrmn) ssrmn is a register that indicates t he communication status and error occurrenc e status of channel n. the errors indicated by this register are a framing error, parity error, and overrun error. ssrmn can be read by a 16-bit memory manipulation instruction. the lower 8 bits of ssrmn can be set with an 8-bit memory manipulation instruction with ssrmnl. reset signal generation clears this register to 0000h. figure 14-9. format of serial st atus register mn (ssrmn) (1/2) address: f0100h, f0101h (ssr00) to f0106h, f0107h (ssr03), after reset: 0000h r f0140h, f0141h (ssr10), f0142h, f0143h (ssr11), f0144h, f0145h (ssr12), f0146h, f0147h (ssr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssrmn 0 0 0 0 0 0 0 0 0 tsf mn bff mn 0 0 fef mn note pef mn note ovf mn note tsf mn communication status indica tion flag of channel n 0 communication is not under execution. 1 communication is under execution. because this flag is an updating flag, it is automatically cleared when the communication operation is completed. this flag is cleared also when the stmn/ssmn bit is set to 1. bff mn buffer register status indication flag of channel n 0 valid data is not stored in the sdrmn register. 1 valid data is stored in the sdrmn register. this is an updating flag. it is automatic ally cleared when transfer from the sdrm n register to the shift register is completed. during reception, it is automatically clear ed when data has been read from the sdrmn register. this flag is cleared also when the stmn/ssmn bit is set to 1. this flag is automatically set if transmit data is written to the sdrmn register when the txemn bit of the scrmn register = 1 (transmission or reception mode in each communi cation mode). it is automatically set if receive data is stored in the sdrmn register when the rxemn bit of t he scrmn register = 1 (trans mission or reception mode in each communication mode). it is also set in case of a reception error. if data is written to the sdrmn register when bffmn = 1, the transmit/receive data stored in the register is discarded and an overrun error (ovfmn = 1) is detected. note only ssr12 register does not have fet12, pet12, and ovf12. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 456 jun 20, 2011 figure 14-9. format of serial st atus register mn (ssrmn) (2/2) address: f0100h, f0101h (ssr00) to f0106h, f0107h (ssr03), after reset: 0000h r f0140h, f0141h (ssr10), f0142h, f0143h (ssr11), f0144h, f0145h (ssr12), f0146h, f0147h (ssr13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssrmn 0 0 0 0 0 0 0 0 0 tsf mn bff mn 0 0 fef mn note pef mn note ovf mn note fef mn framing error detecti on flag of channel n 0 no error occurs. 1 a framing error occurs during uart reception. a framing error occurs if the stop bit is not detected upon completion of uart reception. this is a cumulative flag and is not cleared until 1 is written to the fectmn bit of the sirmn register. pef mn parity error detection flag of channel n 0 error does not occur. 1 a parity error occurs during uart reception or ack is not detected during i 2 c transmission. ? a parity error occurs if the parity of transmit dat a does not match the parity bit on completion of uart reception. ? ack is not detected if the ack signal is not retu rned from the slave in the timing of ack reception during i 2 c transmission. this is a cumulative flag and is not cleared until 1 is written to the pectmn bit of the sirmn register. ovf mn overrun error detection flag of channel n 0 no error occurs. 1 an overrun error occurs. ? receive data stored in the sdrmn register is not read and transmit data is written or the next receive data is written. ? transmit data is not ready for slave tr ansmission or reception in the csi mode. this is a cumulative flag and is not cleared until 1 is written to the ovctmn bit of the sirmn register. note only ssr12 register does not have fet12, pet12, and ovf12. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 457 jun 20, 2011 (7) serial flag clear trigger register mn (sirmn) sirmn is a trigger register that is used to clear each error flag of channel n. when each bit (fectmn, pectmn, ovctmn) of this regist er is set to 1, the corresponding bit (fefmn, pefmn, ovfmn) of serial status register mn is cleared to 0. be cause sirmn is a trigger register, it is cleared immediately when the corresponding bit of ssrmn is cleared. sirmn can be set by a 16-bit memory manipulation instruction. the lower 8 bits of sirmn can be set with an 8-bi t memory manipulation instruction with sirmnl. reset signal generation clears this register to 0000h. figure 14-10. format of serial flag clear trigger register mn (sirmn) address: f0108h, f0109h (sir00) to f010eh, f010fh (sir03), after reset: 0000h r/w f0148h, f0149h (sir10), f014ah, f014bh (sir11), f014eh, f014fh (sir13) symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sirmn 0 0 0 0 0 0 0 0 0 0 0 0 0 fec tmn pec tmn ovc tmn fec tmn clear trigger of fram ing error of channel n 0 no trigger operation 1 clears the fefmn bit of the ssrmn register to 0. pec tmn clear trigger of parity error flag of channel n 0 no trigger operation 1 clears the pefmn bit of the ssrmn register to 0. ovc tmn clear trigger of overrun error flag of channel n 0 no trigger operation 1 clears the ovfmn bit of the ssrmn register to 0. caution be sure to clear bits 15 to 3 to ?0?. remarks 1. m: unit number (m = 0, 1), n: channel number (n = 0 to 3) 2. when the sirmn register is read, 0000h is always read.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 458 jun 20, 2011 (8) serial channel enable status register m (sem) sem indicates whether data transmission/reception ope ration of each channel is enabled or stopped. when 1 is written a bit of serial channel start register 0 (ss m), the corresponding bit of this register is set to 1. when 1 is written a bit of serial channel stop regi ster 0 (stm), the corresponding bit is cleared to 0. channel n that is enabled to operate cannot rewrite by softw are the value of ckomn of t he serial output register m (som) to be described below, and a value reflected by a co mmunication operation is output from the serial clock pin. channel n that stops operation can set the value of ckomn of the som regist er by software and output its value from the serial clock pin. in this way, any waveform, su ch as that of a start conditi on/stop condition, can be created by software. sem can be read by a 16-bit memory manipulation instruction. the lower 8 bits of sem can be set with an 1-bit or 8-bit memory manipulation instruction with seml. reset signal generation clears this register to 0000h. figure 14-11. format of serial channe l enable status register m (sem) address: f0120h, f0121h (se0), f0160h, f0161h (se1) after reset: 0000h r symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sem 0 0 0 0 0 0 0 0 0 0 0 0 sem 3 sem 2 sem 1 sem 0 sem n indication of operation enable/stop status of channel n 0 operation stops (stops with the values of the control r egister and shift register, and the statuses of the serial clock i/o pin, serial data output pin, and the fef, pef, and ovf error flags retained note ). 1 operation is enabled. note bits 6 and 5 (tsfmn, bffmn) of the ssrmn register are cleared. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 459 jun 20, 2011 (9) serial channel start register m (ssm) ssm is a trigger register that is used to enab le starting communication/count by each channel. when 1 is written a bit of this regist er (ssmn), the corresponding bit (semn) of serial channel enable status register m (sem) is set to 1. because ssmn is a trigger bit, it is cleared immediately when semn = 1. ssm can be set by a 16-bit memory manipulation instruction. the lower 8 bits of ssm can be set with an 1-bit or 8-bit memory manipulation instruction with ssml. reset signal generation clears this register to 0000h. figure 14-12. format of serial channel start register m (ssm) address: f0122h, f0123h (ss0), f0162h, f0163h (ss1) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssm 0 0 0 0 0 0 0 0 0 0 0 0 ssm 3 ssm 2 ssm 1 ssm 0 ssmn operation start trigger of channel n 0 no trigger operation 1 sets semn to 1 and enters the communication wait st atus (if a communication operation is already under execution, the operation is stopped and the start condition is awaited). caution be sure to clear bits 15 to 4 to ?0?. remarks 1. m: unit number (m = 0, 1), n: channel number (n = 0 to 3) 2. when the ssm register is read, 0000h is always read.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 460 jun 20, 2011 (10) serial channel stop register m (stm) stm is a trigger register that is used to en able stopping communication/count by each channel. when 1 is written a bit of this register (stmn), the corre sponding bit (semn) of serial channel enable status register m (sem) is cleared to 0. because stmn is a trigger bit, it is cleared immediately when semn = 0. stm can set written by a 16-bit me mory manipulation instruction. the lower 8 bits of stm can be set with an 1-bit or 8-bit memory manipulation instruction with stml. reset signal generation clears this register to 0000h. figure 14-13. format of serial channel stop register m (stm) address: f0124h, f0125h (st0), f0164h, f0165h (st1) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stm 0 0 0 0 0 0 0 0 0 0 0 0 stm 3 stm 2 stm 1 stm 0 stm n operation stop trigger of channel n 0 no trigger operation 1 clears semn to 0 and stops the communication operation. (stops with the values of the contro l register and shift register, and the st atuses of the serial clock i/o pin, serial data output pin, and the fef, pef, and ovf error flags retained note .) note bits 6 and 5 (tsfmn, bffmn) of the ssrmn register are cleared. caution be sure to clear bits 15 to 4 to ?0?. remarks 1. m: unit number (m = 0, 1), n: channel number (n = 0 to 3) 2. when the stm register is read, 0000h is always read.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 461 jun 20, 2011 (11) serial output enable register m (soem) soem is a register that is used to enable or stop output of the serial comm unication operation of each channel. channel n that enables serial output cannot rewrite by software the value of so mn of the serial output register m (som) to be described below, and a value reflected by a co mmunication operation is output from the serial data output pin. for channel n, whose serial output is stopped, the somn value of the som register can be set by software, and that value can be output from the serial data output pin. in this way, any waveform of the start condition and stop condition can be created by software. soem can be set by a 16-bit memory manipulation instruction. the lower 8 bits of soem can be set with an 1-bit or 8-bit memory manipulation instruction with soeml. reset signal generation clears this register to 0000h. figure 14-14. format of serial output enable register m (soem) address: f012ah, f012bh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe 02 soe 01 soe 00 address: f016ah, f016bh after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe1 0 0 0 0 0 0 0 0 0 0 0 0 0 soe 12 0 soe 10 soe mn serial output enable/disable of channel n 0 stops output by serial communication operation. 1 enables output by serial communication operation. caution be sure to clear bits 15 to 3 of so e0, and bits 1 and 15 to 3 of soe1 to ?0?. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), mn = 00 to 02, 10, 12
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 462 jun 20, 2011 (12) serial output register m (som) som is a buffer register for serial output of each channel. the value of bit n of this regi ster is output from the serial data output pin of channel n. the value of bit (n + 8) of this register is outp ut from the serial clock output pin of channel n. somn of this register can be rewritten by software only wh en serial output is disabled (soemn = 0). when serial output is enabled (soemn = 1), rewriting by software is ig nored, and the value of the register can be changed only by a serial communication operation. ckomn of this register can be rewritten by softwar e only when the channel operation is stopped (semn = 0). while channel operation is enabled (semn = 1), rewriti ng by software is ignored, and the value of ckomn can be changed only by a serial communication operation. to use the p10/sck20/scl20, p11/si20/sda20/rxd2 /intp6, p12/so20/txd2/to 02, p13/so10/txd1/to04, p14/si10/sda10/rxd1/intp4, p15/sck1 0/scl10/intp7, p51/txd3/sdgx (78k0r/lf3: x = 29, 78k0r/lg3: x = 38, 78k0r/lh3: x = 52), p75/sck01/kr 5, p77/so01/kr7, p80/sck00/intp11, or p82/so00/txd0 pin as a port function pin, set the corresponding ckomn and somn bits to ?1?. som can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0f0fh. figure 14-15. format of serial output register m (som) address: f0128h, f0129h after reset: 0f0fh r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko 02 cko 01 cko 00 0 0 0 0 1 so 02 so 01 so 00 address: f0168h, f0169h after reset: 0f0fh r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so1 0 0 0 0 1 1 1 cko 10 0 0 0 0 1 so 12 1 so 10 cko mn serial clock output of channel n 0 serial clock output value is ?0?. 1 serial clock output value is ?1?. so mn serial data output of channel n 0 serial data output value is ?0?. 1 serial data output value is ?1?. caution be sure to set bits 11 and 3 of so0, and bits 11 to 9, 3, and 1 of so1 to ?1?. and be sure to clear bits 15 to 12 and 7 to 4 of som to ?0?. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), mn = 00 to 02, 10, 12
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 463 jun 20, 2011 (13) serial output level register m (solm) solm is a register that is used to set inve rsion of the data output level of each channel. this register can be set only in the uart mode. be sure to set 0000h in the csi mode and simplifies i 2 c mode. inverting channel n by using this register is reflect ed on pin output only when serial output is enabled (soemn = 1). when serial output is disabled (soemn = 0) , the value of the somn bit is output as is. rewriting solm is prohibited when the regi ster is in operation (when semn = 1). solm can be set by a 16-bit memory manipulation instruction. the lower 8 bits of solm can be set with an 8-bi t memory manipulation instruction with solml. reset signal generation clears this register to 0000h. figure 14-16. format of serial output level register m (solm) address: f0134h, f0135h (sol0), f0174h, f0175h (sol1) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 solm 0 0 0 0 0 0 0 0 0 0 0 0 0 sol m2 0 sol m0 sol mn selects inversion of the level of the transmit data of channel n in uart mode 0 communication data is output as is. 1 communication data is inverted and output. caution be sure to clear bits 15 to 3, 1 to ?0?. remark m: unit number (m = 0, 1), n: channel number (n = 0, 2)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 464 jun 20, 2011 (14) input switch control register (isc) isc is used to realize a lin-bus communication operation by uart3 in coordination with an external interrupt and the timer array unit. when bit 0 is set to 1, the input signal of the serial data input (r x d3) pin is selected as an external interrupt (intp0) that can be used to detect a wakeup signal. when bit 1 is set to 1, the input signal of the serial data input (r x d3) pin is selected as a timer input, so that the pulse widths of a sync break field and a sync field can be measured by the timer. isc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 14-17. format of input switch control register (isc) address: fff3ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 isc4 isc3 isc2 isc1 isc0 isc1 switching channel 7 input of timer array unit 0 uses the input signal of the ti07 pin as a timer input (normal operation). 1 input signal of r x d3 pin is used as timer input (wakeup signal detection). isc0 switching external interrupt (intp0) input 0 uses the input signal of the intp0 pin as an external interrupt (normal operation). 1 uses the input signal of the r x d3 pin as an external interrupt (to measure the pulse widths of t he sync break field and sync field). caution be sure to clear bits 7 to 5 to ?0?. remark bits 2 to 4 of isc are not used with sau1.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 465 jun 20, 2011 (15) noise filter enable register 0 (nfen0) nfen0 is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel. disable the noise filter of the pin used for csi or simplified i 2 c communication, by clearing the corresponding bit of this register to 0. enable the noise filter of the pin used for uart communication, by setting the corresponding bit of this register to 1. when the noise filter is enabled, cpu/peripheral operating clock (f clk ) is synchronized with 2-clock match detection. nfen0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 14-18. format of noise filter enable register 0 (nfen0) address: f0060h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 nfen0 0 snfen30 0 snfen20 0 snfen10 0 snfen00 snfen30 use of noise filter of r x d3/p50/segx (78k0r/lf3: x = 30, 78k0r/lg3: x = 39, 78k0r/lh3: x = 53) pin 0 noise filter off 1 noise filter on set snfen30 to 1 to use the r x d3 pin. clear snfen30 to 0 to use the p50 or segx pins. snfen20 use of noise filter of r x d2/p11/si20/sda20/intp6 pin 0 noise filter off 1 noise filter on set snfen20 to 1 to use the r x d2 pin. clear snfen20 to 0 to use the p11, si20, sda20 or intp6 pins. snfen10 use of noise filter of r x d1/p14/si10/sda10/intp4 pin 0 noise filter off 1 noise filter on set snfen10 to 1 to use the r x d1 pin. clear snfen10 to 0 to use the p14, si10, sda10 or intp4 pins. snfen00 use of noise filter of r x d0/p80/si00/intp9 pin 0 noise filter off 1 noise filter on set snfen00 to 1 to use the r x d0 pin. clear snfen00 to 0 to use the p80, si00 or intp9. caution be sure to clear bits 7, 5, 3, and 1 to ?0?.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 466 jun 20, 2011 (16) port input mode registers 1, 7 (pim1, pim7) these registers set the input buffer of p10, p 11, p14, p15, p75, and p76 in 1-bit units. pim1 and pim7 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 14-19. format of port input m ode registers 1, and 7 (pim1, pim7) ? 78k0r/lf3, 78k0r/lg3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pim1 0 0 pim15 pim14 0 0 pim11 pim10 f0041h 00h r/w ? 78k0r/lh3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pim1 0 0 pim15 pim14 0 0 pim11 pim10 f0041h 00h r/w pim7 0 pim76 pim75 0 0 0 0 0 f0047h 00h r/w pimmn pmn pin input buffer selection (m = 1 and 7; n = 0, 1, 4 to 6) 0 normal input buffer 1 ttl input buffer
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 467 jun 20, 2011 (17) port output mode registers 1, 7, 8 (pom1, pom7, pom8) these registers set the output mode of p10 to p 15, p75, p77, p80 and 82 in 1-bit units. pom1, pom7, and pom8 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 14-20. format of port output mode registers 1, 7, and 8 (pom1, pom7, pom8) ? 78k0r/lf3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pom1 0 0 pom15 pom14 pom13 po m12 pom11 pom10 f0051h 00h r/w ? 78k0r/lg3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pom1 0 0 pom15 pom14 pom13 po m12 pom11 pom10 f0051h 00h r/w pom8 0 0 0 0 0 pom82 0 pom80 f0058h 00h r/w ? 78k0r/lh3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pom1 0 0 pom15 pom14 pom13 po m12 pom11 pom10 f0051h 00h r/w pom7 pom77 0 pom75 0 0 0 0 0 f0057h 00h r/w pom8 0 0 0 0 0 pom82 0 pom80 f0058h 00h r/w pommn pmn pin output mode selection (m = 1, 7, and 8; n = 0 to 5 and 7) 0 normal output mode 1 n-ch open-drain output (v dd tolerance) mode
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 468 jun 20, 2011 (18) port mode registers 1, 5, 7, 8 (pm1, pm5, pm7, pm8) these registers set input/output of ports 1, 5, 7 and 8 in 1-bit units. when using the p10/sck20/scl20, p11/si20/sda20/rxd2/intp6, p12/so20/txd2/to02, p13/so10/txd1/to04, p14/si10/sda10/rxd1/intp4, p15/sck10/scl10/intp7, p51/txd3/segx (78k0r/lf3: x = 29, 78k0r/lg3: x = 38, 78k0r/lh3: x = 52), p75/sck01/kr5, p77/so01/kr7, p80/sck00/intp11, and p82/so00/txd0 pins for serial data output or serial clock output, clear the pm10, pm11, pm12, pm13, pm14, pm15, pm 51, pm75, pm77, pm80, and pm82 bits to 0, and set the output latches of p10, p11, p12, p13, p14, p15, p51, p75, p77, p80, and p82 to 1. when using the p10/sck20/scl20, p11/si20/sda20/rxd2/intp6, p14/si10/sda10/rxd1/intp4, p15/sck10/scl10/intp7, p50/rxd3/segx (78k0r/lf3: x = 30, 78k0r/lg3: x = 39, 78k0r/lh3: x = 53), p75/sck01/kr5, p76/si01/kr6, p80/sck00/intp11, and p81/ si00/rxd0/intp9 pins for serial data input or serial clock input, set the pm10, pm11, pm14, pm15, pm50, pm75, pm76, pm80, and pm81 bits to 1. at this time, the output latches of p10, p11, p14, p15, p 50, p75, p76, p80, and p81 may be 0 or 1. pm1, pm5, pm7, and pm8 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation se ts these registers to ffh. figure 14-21. format of port mode registers 1, 5, 7, and 8 (pm1, pm5, pm7, pm8) ? 78k0r/lf3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pm1 1 1 pm15 pm14 pm13 pm12 pm11 pm10 fff21h ffh r/w pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 fff25h ffh r/w ? 78k0r/lg3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pm1 1 pm16 pm15 pm14 pm13 pm12 pm11 pm10 fff21h ffh r/w pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 fff25h ffh r/w pm8 1 1 1 1 1 pm82 pm81 pm80 fff28h ffh r/w ? 78k0r/lh3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 fff21h ffh r/w pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 fff25h ffh r/w pm7 pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 fff27h ffh r/w pm8 pm87 pm86 pm85 pm84 pm83 pm82 pm81 pm80 fff28h ffh r/w pmmn pmn pin i/o mode selection (m = 1, 5, 7, 8; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 469 jun 20, 2011 14.4 operation stop mode each serial interface of serial array unit has the operation stop mode. in this mode, serial communication cannot be exec uted, thus reducing the power consumption. in addition, the p10/sck20/scl20, p11/si20/sda20/rxd2/intp6, p12/so20/txd2/to02, p13/so10/txd1/to04, p14/si10/sda10/rxd1/intp4, p15/sck10/ scl10/intp7, p50/rxd3/segx (78k0r/lf3: x = 30, 78k0r/lg3: x = 39, 78k0r/lh3: x = 53), p51/txd3/segx (78k0r/lf3: x = 29, 78k0r/lg3: x = 38, 78k0r/lh3: x = 52), p75/sck01/kr5, p76/si01/kr6, p77/so01/kr7, p80/sck00/intp11, p81/si00/rxd0/intp9, and p82/so00/txd0 pins can be used as ordinary port pins in this mode. 14.4.1 stopping the operation by units the stopping of the operation by units is set by using peripheral enable register 0 (per0). per0 is used to enable or disable use of each peripheral har dware macro. clock supply to a hardware macro that is not used is stopped in order to reduc e the power consumption and noise. to stop the operation of serial array unit 0, set bit 2 (sau0en) to 0. to stop the operation of serial array unit 1, set bit 3 (sau1en) to 0. figure 14-22. peripheral enable register 0 (per 0) setting when stopping the operation by units caution if saumen = 0, writing to a control register of serial array unit m is ignored, and, even if the register is read, only the default value is read (e xcept for input switch contro l register (isc), noise filter enable register (nfen0), port input mode re gisters (pim1, pim7), port output mode registers (pom1, pom7, pom8), port mode registers (pm1, pm5, pm7, pm8), and port registers (p1, p5, p7, p8)). remark m: unit number (m = 0, 1) : bits not used with serial array units (dependi ng on the settings of other peripheral functions) 0/1: set to 0 or 1 depending on the usage of the user (a) peripheral enable register 0 (per0) ? set only the bit of saum to be stopped to 0. 7 6 5 4 3 2 1 0 per0 rtcen dacen adcen iic0en sau1en 0/1 sau0en 0/1 tau 1 e n tau 0 e n control of saum input clock 0: stops supply of input clock 1: su pp lies in p ut cloc k
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 470 jun 20, 2011 14.4.2 stopping the operation by channels the stopping of the operation by channels is se t using each of the following registers. figure 14-23. each register setting when stopping the operation by channels (1/2) ? serial channel enable status register m ( sem) ? this register indicates whether data transmission/reception operation of eac h channel is enabled or stopped. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sem 0 0 0 0 0 0 0 0 0 0 0 0 sem3 0/1 sem2 0/1 sem1 0/1 sem0 0/1 0: operation stops ? the sem register is a read-only stat us register, whose operation is stopped by using the stm register. with a channel whose operation is stopped, the value of ckomn of the som register can be set by software. ? serial channel stop register m (stm) ? this register is a trigger register that is used to enable stopping communication/count by each channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stm 0 0 0 0 0 0 0 0 0 0 0 0 stm3 0/1 stm2 0/1 stm1 0/1 stm0 0/1 1: clears semn to 0 and stops the communication operation * because stmn is a trigger bit, it is cleared immediately when semn = 0. (c) serial output enable register m (soem) ? this regist er is a register that is used to enable or stop output of the serial communication operation of each channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe0 0 0 0 0 0 0 0 0 0 0 0 0 0 soe02 0/1 soe01 0/1 soe00 0/1 0: stops output by serial communication operation * for channel n, whose serial output is stopped, the so0n value of the so0 register can be set by software. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soe1 0 0 0 0 0 0 0 0 0 0 0 0 0 soe12 0/1 0 soe10 0/1 0: stops output by serial communication operation * for channel n, whose serial output is stopped, the so1n value of the so1 register can be set by software. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3) : setting disabled (fixed by hardware), 0/1: set to 0 or 1 depending on the usage of the user
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 471 jun 20, 2011 figure 14-23. each register setting when stopping the operation by channels (2/2) (d) serial output register m (som) ?thi s register is a buffer register for serial output of each channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so0 0 0 0 0 1 cko02 0/1 cko01 0/1 cko00 0/1 0 0 0 0 1 so02 0/1 so01 0/1 so00 0/1 1: serial clock output value is ?1? 1: serial data output value is ?1? * when using pins corresponding to each c hannel as port function pins, set the corresponding cko0n and so0n bits to ?1?. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so1 0 0 0 0 1 1 1 cko10 0/1 0 0 0 0 1 so12 0/1 1 so10 0/1 1: serial clock output value is ?1? 1: serial data output value is ?1? * when using pins corresponding to each channel as port function pins, set the corresponding cko10 and so1n bits to ?1?. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3) : setting disabled (fixed by hardware), 0/1: set to 0 or 1 depending on the usage of the user
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 472 jun 20, 2011 14.5 operation of 3-wire serial i/o (c si00, csi01, csi10, csi20) communication this is a clocked communication function that uses thr ee lines: serial clock (sck) and serial data (si and so) lines. [data transmission/reception] ? data length of 7 or 8 bits ? phase control of transmit/receive data ? msb/lsb first selectable ? level setting of transmit/receive data [clock control] ? master/slave selection ? phase control of i/o clock ? setting of transfer period by prescaler and internal counter of each channel [interrupt function] ? transfer end interrupt/buffer empty interrupt [error detection flag] ? overrun error the channels supporting 3-wire serial i/o (csi00, csi01, csi10, csi 20) are channels 0 to 2 of sau0 and channel 0 of sau1. unit channel used as csi used as uart used as simplified i 2 c 0 csi00 uart0 ? 1 csi01 ? 2 csi10 uart1 iic10 0 3 ? ? 0 csi20 uart2 iic20 1 ? ? 2 ? uart3 (supporting lin-bus) ? 1 3 ? ? remarks 1. for 78k0r/lf3, csi00 and csi01 are not mounted. 2. for 78k0r/lg3, csi01 is not mounted. 3-wire serial i/o (csi00, csi01, cis 10, csi20) performs the following six types of communic ation operations. ? master transmission (see 14.5.1 .) ? master reception (see 14.5.2 .) ? master transmission/reception (see 14.5.3 .) ? slave transmission (see 14.5.4 .) ? slave reception (see 14.5.5 .) ? slave transmission/reception (see 14.5.6 .)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 473 jun 20, 2011 14.5.1 master transmission master transmission is that the 78k0r/lx3 microcontrollers out put a transfer clock and transmit data to another device. 3-wire serial i/o csi00 csi01 csi10 csi20 target channel channel 0 of sau0 channel 1 of sau0 channel 2 of sau0 channel 0 of sau1 pins used sck00, so00 sck01, so01 sck10, so10 sck20, so20 intcsi00 intcsi01 intcsi10 intcsi20 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag none transfer data length 7 or 8 bits transfer rate max. f clk /4 [mhz], min. f clk /(2 2 11 128) [mhz] note f clk : system clock frequency data phase selectable by dapmn bit ? dapmn = 0: data output starts from the start of the operation of the serial clock. ? dapmn = 1: data output starts half a clock before the start of the serial clock operation. clock phase selectable by ckpmn bit ? ckpmn = 0: forward ? ckpmn = 1: reverse data direction msb or lsb first note use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 31 electrical specifications ). remarks 1. for 78k0r/lf3, csi00 and csi01 are not mounted. 2. for 78k0r/lg3, csi01 is not mounted.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 474 jun 20, 2011 (1) register setting figure 14-24. example of contents of registers for master transmission of 3-wire serial i/o (csi00, csi01, csi10, csi20) (a) serial output register m (som) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 som 0 0 0 0 1 ckom2 0/1 ckom1 0/1 ckom0 0/1 0 0 0 0 1 som2 0/1 som1 0/1 som0 0/1 communication starts when these bits are 1 if the data phase is forward (ckpmn = 0). if the phase is reversed (ckpmn = 1), communication starts when these bits are 0. (b) serial output enable register m (soem) ? se ts only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soem 0 0 0 0 0 0 0 0 0 0 0 0 0 soem2 0/1 soem1 0/1 soem0 0/1 (c) serial channel start register m (ssm) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssm 0 0 0 0 0 0 0 0 0 0 0 0 ssm3 ssm2 0/1 ssm1 0/1 ssm0 0/1 (d) serial mode register mn (smrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cksmn 0/1 ccsmn 0 0 0 0 0 0 stsmn 0 0 sism0 0 1 0 0 mdmn2 0 mdmn1 0 mdmn0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt (e) serial communication operati on setting register mn (scrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txemn 1 rxemn 0 dapmn 0/1 ckpmn 0/1 0 eocmn 0 ptcmn1 0 ptcmn0 0 dirmn 0/1 0 slcmn1 0 slcmn0 0 0 dlsmn2 1 dlsmn1 1 dlsmn0 0/1 (f) serial data register mn (sdrmn) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn baud rate setting 0 transmit data setting remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20) : setting is fixed in the csi ma ster transmission mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 475 jun 20, 2011 (2) operation procedure figure 14-25. initial setting pr ocedure for master transmission caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. starting initial setting setting per0 register setting spsm register setting smrmn register setting scrmn register setting sdrmn register setting som register changing setting of soem register setting port writing to ssm register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the somn and ckomn bits and set an initial output level. set the soemn bit to 1 and enable data output of the target channel. enable data output and clock output of the target channel by setting a port register and a port mode register. set transmit data to the siop register (bits 7 to 0 of the sdrmn register) and start communication. set the ssmn bit of the target channel to 1 to set semn = 1.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 476 jun 20, 2011 figure 14-26. procedure for stopping master transmission remarks 1. even after communication is stopped, the pin level is retained. to resume the operation, re-set the som register (see figure 14-27 procedure for r esuming master transmission ). 2. p: csi number (p = 00, 01, 10, 20) starting setting to stop setting stm register stopping communication write 1 to the stmn bit of the target channel. stop communication in midway. set the soem register and stop the output of the target channel changing setting of soem register
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 477 jun 20, 2011 figure 14-27. procedure for resuming master transmission starting setting for resumption port manipulation changing setting of spsm register changing setting of sdrmn register changing setting of smrmn register changing setting of som register port manipulation writing to ssm register starting communication disable data output and clock output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smrmn register is incorrect. manipulate the somn and ckomn bits and set an initial output level. enable data output and clock output of the target channel by setting a port register and a port mode register. set the ssmn bit of the target channel to 1 to set semn = 1. sets transmit data to the siop register (bits 7 to 0 of the sdrmn register) and start communication. (essential) (selective) (selective) (selective) (selective) ( essential ) (essential) (essential) change the setting if the setting of the scrmn register is incorrect. (selective) changing setting of scrmn register cleared by using sirmn registe r if fef, pef, or ovf flag remains set. (selective) clearing error flag set the soem register and enable data output of the target channel. (selective) changing setting of soem register set the soem register and stop the output of the target channel. (selective) changing setting of soem register
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 478 jun 20, 2011 (3) processing flow (in si ngle-transmission mode) figure 14-28. timing chart of master transmission (in single-transmission mode) ssmn stmn semn sdrmn sckp pin sop pin shift register mn intcsip tsfmn data transmission (8-bit length) data transmission (8-bit length) data transmission (8-bit length) transmit data 3 transmit data 2 transmit data 1 transmit data 1 transmit data 2 transmit data 3 shift operation shift operation shift operation remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 479 jun 20, 2011 figure 14-29. flowchart of master tr ansmission (in single-transmission mode) caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. starting csi communication writing 1 to ssmn bit writing transmit data to siop (=sdrmn[7:0]) writing 1 to stmn bit perform initial setting when semn = 0. smrmn, scrmn: sett ing communication sdrmn[15:9]: setting transfer rate som, soem: setting output transfer end interrupt g enerated? transmission completed? no no yes yes setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register port manipulation clearing sau1en and sau0en bits of per0 register to 0 end of communication
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 480 jun 20, 2011 (4) processing flow (in continuous transmission mode) figure 14-30. timing chart of master tran smission (in continuous transmission mode) ssmn semn sdrmn sckp pin sop pin shift register mn intcsip tsfmn data transmission (8-bit length) data transmission (8-bit length) transmit data 2 transmit data 1 transmit data 3 bffmn mdmn0 transmit data 2 <1> <2> <2> <2> <3> <3> <3> <5> <6> <4> ( note ) shift operation shift operation shift operation transmit data 3 data transmission (8-bit length) stmn transmit data 1 note when transmit data is written to the sdrmn register while bffmn = 1, the transmit data is overwritten. caution the mdmn0 bit can be rewr itten even during operation. however, rewrite it before transfer of the last bit is started, so that it will be rewritten before the transfer end interrupt of the last transmit data. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 481 jun 20, 2011 figure 14-31. flowchart of master transm ission (in continuous transmission mode) starting csi communication writing 1 to ssmn bit writing transmit data to siop (=sdrmn[7:0]) writing 1 to stmn bit perform initial setting when semn = 0. <1> select the buffer empty interrupt. smrmn, scrmn: setting communication sdrmn[15:9]: setting transfer rate som, soem; setting output n o n o n o y es setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register port manipulation end of communication clearing 0 to mdmn0 bit y es n o y es n o communication continued? y es y es clearing sau1en and sau0en bits of per0 register to 0 <2> <3> <4> <5> transmitting next data? buffer empty interrupt generated? transfer end interrupt generated? tsfmn = 1? writing 1 to mdmn0 bit <6> caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. remark <1> to <6> in the figure correspond to <1> to <6> in figure 14-30 timing chart of master transmission (in continuous transmission mode) .
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 482 jun 20, 2011 14.5.2 master reception master reception is that the 78k0r/lx 3 microcontrollers output a transfer clock and receive data from other device. 3-wire serial i/o csi00 csi01 csi10 csi20 target channel channel 0 of sau0 channel 1 of sau0 channel 2 of sau0 channel 0 of sau1 pins used sck00, si00 sck01, si01 sck10, si10 sck20, si20 intcsi00 intcsi01 intcsi10 intcsi20 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag overrun error detection flag (ovfmn) only transfer data length 7 or 8 bits transfer rate max. f clk /4 [mhz], min. f clk /(2 2 11 128) [mhz] note f clk : system clock frequency data phase selectable by dapmn bit ? dapmn = 0: data input starts from the start of the operation of the serial clock. ? dapmn = 1: data input starts half a clock bef ore the start of the serial clock operation. clock phase selectable by ckpmn bit ? ckpmn = 0: forward ? ckpmn = 1: reverse data direction msb or lsb first note use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 31 electrical specifications ). remarks 1. for 78k0r/lf3, csi00 and csi01 are not mounted. 2. for 78k0r/lg3, csi01 is not mounted.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 483 jun 20, 2011 (1) register setting figure 14-32. example of contents of register s for master reception of 3-wire serial i/o (csi00, csi01, csi10, csi20) (a) serial output register m (som) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 som 0 0 0 0 1 ckom2 0/1 ckom1 0/1 ckom0 0/1 0 0 0 0 1 som2 som1 som0 communication starts when these bits are 1 if the data phase is forward (ckpmn = 0). if the phase is reversed (ckpmn = 1), communication starts when these bits are 0. (b) serial output enable register m (soem) ? cl ears only the bits of the target channel to 0. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soem 0 0 0 0 0 0 0 0 0 0 0 0 0 soem2 0/1 soem1 0/1 soem0 0/1 (c) serial channel start register m (ssm) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssm 0 0 0 0 0 0 0 0 0 0 0 0 ssm3 ssm2 0/1 ssm1 0/1 ssm0 0/1 (d) serial mode register mn (smrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cksmn 0/1 ccsmn 0 0 0 0 0 0 stsmn 0 0 sismn0 0 1 0 0 mdmn2 0 mdmn1 0 mdmn0 0 operation mode of channel n 0: transfer end interrupt (e) serial communication operati on setting register mn (scrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txemn 0 rxemn 1 dapmn 0/1 ckpmn 0/1 0 eocmn 0 ptcmn1 0 ptcmn0 0 dirmn 0/1 0 slcmn1 0 slcmn0 0 0 dlsmn2 1 dlsmn1 1 dlsmn0 0/1 (f) serial data register mn (sdrmn) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn baud rate setting 0 receive data register (write ffh as dummy data.) remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20) : setting is fixed in the csi master reception mode , : setting disabled (s et to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 484 jun 20, 2011 (2) operation procedure figure 14-33. initial setting procedure for master reception caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. figure 14-34. procedure for stopping master reception remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the som register (see figure 14-35 procedure for resuming master reception ). starting initial setting setting per0 register setting spsm register setting smrmn register setting scrmn register setting sdrmn register setting som register setting port writing to ssm register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the ckomn bit and set an initial output level. enable clock output of the target channel by setting a port register and a port mode register. set the ssmn bit of the target channel to 1 to set semn = 1. set dummy data to the siop register (bits 7 to 0 of the sdrmn register) and start communication. starting setting to stop setting stm register stopping communication write 1 to the stmn bit of the target channel. stop communication in midway.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 485 jun 20, 2011 figure 14-35. procedure for resuming master reception starting setting for resumption port manipulation changing setting of spsm register changing setting of sdrmn register changing setting of smrmn register changing setting of som register port manipulation writing to ssm register starting communication disable clock output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smrmn register is incorrect. manipulate the ckomn bit and set a clock output level. enable clock output of the target channel by setting a port register and a port mode register. set the ssmn bit of the target channel to 1 to set semn = 1. sets dummy data to the siop register (bits 7 to 0 of the sdrmn register) and start communication. (essential) (selective) (selective) ( selective ) (selective) ( essential ) (essential) (essential) change the setting if the setting of the scrmn register is incorrect. (selective) changing setting of scrmn register cleared by using sirmn register if fef, pef, or ovf flag remains set. (selective) clearing error flag clear the soem register to 0 and stop data output of the target channel. (essential) changing setting of soem register
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 486 jun 20, 2011 (3) processing flow (in single-reception mode) figure 14-36. timing chart of master reception (in si ngle-reception mode) (type 1: dapmn = 0, ckpmn = 0) ssmn semn sdrmn sckp pin sip pin shift register mn intcsip tsfmn data reception (8-bit length) data reception (8-bit length) data reception (8-bit length) reception & shift operation reception & shift operation reception & shift operation stmn receive data 3 receive data 2 receive data 1 dummy data for reception dummy data dummy data receive data 1 receive data 2 receive data 3 write read write read read write remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 487 jun 20, 2011 figure 14-37. flowchart of master reception (in single-reception mode) starting csi communication writing 1 to ssmn bit writing dummy data to siop (=sdrmn[7:0]) writing 1 to stmn bit perform initial setting when semn = 0. smrmn, scrmn: setting communication sdrmn[15:9]: setting transfer rate som, soem: setting sckp output transfer end interrupt generated? reception completed? no no yes yes setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register port manipulation clearing sau1en and sau0en bits of per0 register to 0 end of communication reading siop (= sdrmn[7:0]) register starting reception caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 488 jun 20, 2011 14.5.3 master transmission/reception master transmission/reception is that the 78k0r/lx3 microcontrollers output a transfer clock and transmit/receive data to/from other device. 3-wire serial i/o csi00 csi01 csi10 csi20 target channel channel 0 of sau0 channel 1 of sau0 channel 2 of sau0 channel 0 of sau1 pins used sck00, si00, so00 sck01, si01, so01 sck10, si10, so10 sck20, si20, so20 intcsi00 intcsi01 intcsi10 intcsi20 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag overrun error detection flag (ovfmn) only transfer data length 7 or 8 bits transfer rate max. f clk /4 [mhz], min. f clk /(2 2 11 128) [mhz] note f clk : system clock frequency data phase selectable by dapmn bit ? dapmn = 0: data i/o starts at the start of the operation of the serial clock. ? dapmn = 1: data i/o starts half a clock befo re the start of the serial clock operation. clock phase selectable by ckpmn bit ? ckpmn = 0: forward ? ckpmn = 1: reverse data direction msb or lsb first note use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 31 electrical specifications ). remarks 1. for 78k0r/lf3, csi00 and csi01 are not mounted. 2. for 78k0r/lg3, csi01 is not mounted.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 489 jun 20, 2011 (1) register setting figure 14-38. example of contents of registers for master transmission/reception of 3-wire serial i/o (csi00, csi01, csi10, csi20) (a) serial output register m (som) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 som 0 0 0 0 1 ckom2 0/1 ckom1 0/1 ckom0 0/1 0 0 0 0 1 som2 0/1 som1 0/1 som0 0/1 communication starts when these bits are 1 if the data phase is forward (ckpmn = 0). if the phase is reversed (ckpmn = 1), communication starts when these bits are 0. (b) serial output enable register m (soem) ? se ts only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soem 0 0 0 0 0 0 0 0 0 0 0 0 0 soem2 0/1 soem1 0/1 soem0 0/1 (c) serial channel start register m (ssm) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssm 0 0 0 0 0 0 0 0 0 0 0 0 ssm3 ssm2 0/1 ssm1 0/1 ssm0 0/1 (d) serial mode register mn (smrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cksmn 0/1 ccsmn 0 0 0 0 0 0 stsmn 0 0 sismn0 0 1 0 0 mdmn2 0 mdmn1 0 mdmn0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt (e) serial communication operati on setting register mn (scrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txemn 1 rxemn 1 dapmn 0/1 ckpmn 0/1 0 eocmn 0 ptcmn1 0 ptcmn0 0 dirmn 0/1 0 slcmn1 0 slcmn0 0 0 dlsmn2 1 dlsmn1 1 dlsmn0 0/1 (f) serial data register mn (sdrmn) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn baud rate setting 0 transmit data setting/receive data register remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20) : setting is fixed in the csi mast er transmission/reception mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 490 jun 20, 2011 (2) operation procedure figure 14-39. initial setting procedur e for master transmission/reception caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. figure 14-40. procedure for stoppi ng master transmission/reception remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the som register (see figure 14-41 procedure for resumi ng master transmission/reception ). starting setting to stop setting stm register write 1 to the stmn bit of the target channel. changing setting of soem register stopping communication set the soem register and stop the output of the target channel. stop communication in midway. starting initial setting setting per0 register setting spsm register setting smrmn register setting scrmn register setting sdrmn register setting som register changing setting of soem register setting port writing to ssm register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the somn and ckomn bits and set an initial output level. set the soemn bit to 1 and enable data output of the target channel. enable data output and clock output of the target channel by setting a port register and a port mode register. set the ssmn bit of the target channel to 1 to set semn = 1. set transmit data to the siop register (bits 7 to 0 of the sdrmn register) and start communication.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 491 jun 20, 2011 figure 14-41. procedure for resumi ng master transmission/reception starting setting for resumption port manipulation changing setting of spsm register changing setting of sdrmn register changing setting of smrmn register changing setting of som register disable data output and clock output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smrmn register is incorrect. manipulate the somn and ckomn bits and set an initial output level. (essential) (selective) (selective) (selective) (selective) change the setting if the setting of the scrmn register is incorrect. (selective) changing setting of scrmn register cleared by using sirmn registe r if fef, pef, or ovf flag remains set. (selective) clearing error flag set the soem register and stop the output of the target channel. (selective) changing setting of soem register changing setting of soem register port manipulation writing to ssm register starting communication set the soem register and enable the output of the target channel. enable data output and clock output of the target channel by setting a port register and a port mode register. set the ssmn bit of the target channel to 1 and set semn to 1. set transmit data to the siop register (bits 7 to 0 of the sdrmn register) and start communication. (selective) ( essential ) (essential) (essential)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 492 jun 20, 2011 (3) processing flow (in single -transmission/reception mode) figure 14-42. timing chart of master transmission/ reception (in single-trans mission/reception mode) (type 1: dapmn = 0, ckpmn = 0) ssmn semn sdrmn sckp pin sip pin shift register mn intcsip tsfmn data transmission/reception (8-bit length) data transmission/reception (8-bit length) data transmission/reception (8-bit length) sop pin reception & shift operation reception & shift operation reception & shift operation stmn receive data 3 receive data 2 receive data 1 transmit data 1 transmit data 2 receive data 1 receive data 2 receive data 3 write read write read read write transmit data 3 transmit data 2 transmit data 1 transmit data 2 remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 493 jun 20, 2011 figure 14-43. flowchart of master transmission/ reception (in single- tr ansmission/reception mode) starting csi communication writing 1 to ssmn bit writing transmit data to siop (=sdrmn[7:0]) writing 1 to stmn bit perform initial setting when semn = 0. smrmn, scrmn: setting communication sdrmn[15:9]: setting transfer rate som, soem: setting output and sckp output transfer end interrupt generated? transmission/reception completed? no no yes yes setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register port manipulation clearing sau1en and sau0en bits of per0 register to 0 end of communication reading siop (=sdrmn[7:0]) register starting transmission/reception caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 494 jun 20, 2011 (4) processing flow (in continu ous transmission/reception mode) figure 14-44. timing chart of master transmission/ reception (in continuous tr ansmission/reception mode) (type 1: dapmn = 0, ckpmn = 0) ssmn semn sdrmn sckp pin sip pin shift register mn intcsip tsfmn sop pin reception & shift operation reception & shift operation bffmn reception & shift operation mdmn0 data transmission/reception (8-bit length) data transmission/reception (8-bit length) data transmission/reception (8-bit length) stmn <4> <5> transmit data 1 transmit data 3 receive data 3 write read read read write <1> <2> <3> <2> <3> <4> <2> <7> <8> ( note 1 ) transmit data 2 write <6> <3> ( note 2 ) ( note 2 ) receive data 2 receive data 1 receive data 1 receive data 2 receive data 3 transmit data 3 transmit data 2 transmit data 1 notes 1. when transmit data is written to the sdrmn register while bffmn = 1, the transmit data is overwritten. 2. the transmit data can be read by r eading the sdrmn register during this period. at this time, the transfer operation is not affected. caution the mdmn0 bit can be rewr itten even during operation. however, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data. remarks 1. <1> to <8> in the figure correspond to <1> to <8> in figure 14-45 flowchart of master transmission/reception (in contin uous transmission/reception mode ). 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 495 jun 20, 2011 figure 14-45. flowchart of master transmission/r eception (in continuous tr ansmission/reception mode) starting csi communication writing 1 to ssmn bit reading receive data to siop (=sdrmn[7:0]) writing 1 to stmn bit perform initial setting when semn = 0. <1> select the buffer empty interrupt. smrmn, scrmn: setting communication sdrmn[15:9]: setting transfer rate som, soem: setting output and sckp output y es y es n o n o setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register port manipulation end of communication clearing 0 to mdmn0 bit n o transfer end interrupt generated? y es n o communication continued? y es y es clearing sau1en and sau0en bits of per0 register to 0 communication data exists? writing transmit data to siop (=sdrmn[7:0]) tsfmn = 1? reading receive data to siop (=sdrmn[7:0]) writing 1 to mdmn0 bit buffer empty interrupt generated? <2> <3> <5> <6> <7> <4> <8> n o caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. remark <1> to <8> in the figure correspond to <1> to <8> in figure 14-44 timing chart of master transmission/reception (in continuo us transmission/reception mode) .
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 496 jun 20, 2011 14.5.4 slave transmission slave transmission is that the 78k0r/lx3 microcontrollers trans mit data to another device in the state of a transfer clock being input from another device. 3-wire serial i/o csi00 csi01 csi10 csi20 target channel channel 0 of sau0 channel 1 of sau0 channel 2 of sau0 channel 0 of sau1 pins used sck00, so00 sck01, so01 sck10, so10 sck20, so20 intcsi00 intcsi01 intcsi10 intcsi20 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag overrun error detection flag (ovfmn) only transfer data length 7 or 8 bits transfer rate max. f mck /6 [mhz] notes 1, 2 data phase selectable by dapmn bit ? dapmn = 0: data output starts from the start of the operation of the serial clock. ? dapmn = 1: data output starts half a clock before the start of the serial clock operation. clock phase selectable by ckpmn bit ? ckpmn = 0: forward ? ckpmn = 1: reverse data direction msb or lsb first notes 1. because the external serial clock input to pins sck 00, sck01, sck10, and sck20 is sampled internally and used, the fastest transfer rate is f mck /6 [mhz]. 2. use this operation within a range t hat satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 31 electrical specifications ). remarks 1. f mck : operation clock (mck) frequency of target channel 2. for 78k0r/lf3, csi00 and csi01 are not mounted. 3. for 78k0r/lg3, csi01 is not mounted.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 497 jun 20, 2011 (1) register setting figure 14-46. example of contents of register s for slave transmission of 3-wire serial i/o (csi00, csi01, csi10, csi20) (a) serial output register m (som) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 som 0 0 0 0 1 ckom2 ckom1 ckom0 0 0 0 0 1 som2 0/1 som1 0/1 som0 0/1 (b) serial output enable register m (soem) ? se ts only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soem 0 0 0 0 0 0 0 0 0 0 0 0 0 soem2 0/1 soem1 0/1 soem0 0/1 (c) serial channel start register m (ssm) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssm 0 0 0 0 0 0 0 0 0 0 0 0 ssm3 ssm2 0/1 ssm1 0/1 ssm0 0/1 (d) serial mode register mn (smrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cksmn 0/1 ccsmn 1 0 0 0 0 0 stsmn 0 0 sismn0 0 1 0 0 mdmn2 0 mdmn1 0 mdmn0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt (e) serial communication operati on setting register mn (scrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txemn 1 rxemn 0 dapmn 0/1 ckpmn 0/1 0 eocmn 0 ptcmn1 0 ptcmn0 0 dirmn 0/1 0 slcmn1 0 slcmn0 0 0 dlsmn2 1 dlsmn1 1 dlsmn0 0/1 (f) serial data register mn (sdrmn) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn baud rate setting 0 transmit data setting remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20) : setting is fixed in the csi slave transmission mode , : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 498 jun 20, 2011 (2) operation procedure figure 14-47. initial setting pr ocedure for slave transmission caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. starting initial setting setting per0 register setting spsm register setting smrmn register setting scrmn register setting sdrmn register setting som register changing setting of soem register setting port writing to ssm register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set bits 15 to 9 to 0000000b for baud rate setting. manipulate the somn bit and set an initial output level. set the soemn bit to 1 and enable data output of the target channel. enable data output of the target channel by setting a port register and a port mode register. set the ssmn bit of the target channel to 1 to set semn = 1. set transmit data to the siop register (bits 7 to 0 of the sdrmn register) and wait for a clock from the master.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 499 jun 20, 2011 figure 14-48. procedure for stopping slave transmission remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the som register (see figure 14-49 procedure for resuming slave transmission ). starting setting to stop setting stm register write 1 to the stmn bit of the target channel. changing setting of soem register stopping communication set the soem register and stop the output of the target channel. stop communication in midway.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 500 jun 20, 2011 figure 14-49. procedure for resuming slave transmission starting setting for resumption port manipulation changing setting of spsm register changing setting of smrmn register disable data output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if the setting of the smrmn register is incorrect. (selective) (selective) ( selective ) change the setting if the setting of the scrmn register is incorrect. (selective) changing setting of scrmn register cleared by using sirmn registe r if fef, pef, or ovf flag remains set. (selective) clearing error flag stop the target fo r communication or wait until the target completes its operation. (essential) manipulating target for communication changing setting of som register port manipulation writing to ssm register manipulate the somn and ckomn bits and set an initial output level. enable data output of the target channel by setting a port register and a port mode register. set the ssmn bit of the target channel to 1 to set semn = 1. set transmit data to the siop register (bits 7 to 0 of the sdrmn register) and wait for a clock from the master. (selective) ( essential ) (essential) (essential) set the soem register and stop the output of the target channel. (selective) changing setting of soem register set the soem register and enable the output of the target channel. (selective) changing setting of soem register starting target for communication start the target for communication. (essential) starting communication
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 501 jun 20, 2011 (3) processing flow (in si ngle-transmission mode) figure 14-50. timing chart of slave tr ansmission (in single-transmission mode) (type 1: dapmn = 0, ckpmn = 0) ssmn semn sdrmn sckp pin sop pin shift register mn intcsip tsfmn stmn data transmission (8-bit length) data transmission (8-bit length) data transmission (8-bit length) transmit data 3 transmit data 2 transmit data 1 transmit data 1 transmit data 2 transmit data 3 shift operation shift operation shift operation remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 502 jun 20, 2011 figure 14-51. flowchart of slave tran smission (in single-transmission mode) caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. starting csi communication writing 1 to ssmn bit writing transmit data to siop (=sdrmn[7:0]) writing 1 to stmn bit perform initial setting when semn = 0. smrmn, scrmn: setting communication sdrmn[15:9]: setting transfer rate som, soem: setting output transfer end interrupt generated? transmission completed? no no yes yes setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register port manipulation clearing sau1en and sau0en bits of per0 register to 0 end of communication
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 503 jun 20, 2011 (4) processing flow (in continuous transmission mode) figure 14-52. timing chart of slave transm ission (in continuous transmission mode) (type 1: dapmn = 0, ckpmn = 0) ssmn semn sdrmn sckp pin sop pin shift register mn intcsip tsfmn bffmn mdmn0 stmn data transmission (8-bit length) data transmission (8-bit length) transmit data 2 transmit data 1 transmit data 3 transmit data 2 <1> <2> <2> <2> <3> <3> <3> <5> <4> ( note ) shift operation shift operation shift operation transmit data 3 data transmission (8-bit length) transmit data 1 <6> note when transmit data is written to the sdrmn register while bffmn = 1, the transmit data is overwritten. caution the mdmn0 bit can be rewritten even during opera tion. however, rewrite it before transfer of the last bit is started.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 504 jun 20, 2011 figure 14-53. flowchart of slave transmission (in continuous transmission mode) starting csi communication writing 1 to ssmn bit writing transmit data to siop (=sdrmn[7:0]) writing 1 to stmn bit perform initial setting when semn = 0. <1> select the buffer empty interrupt. smrmn, scrmn: setting communication sdrmn[15:9]: setting transfer rate som, soem: setting output n o n o n o y es setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register port manipulation end of communication clearing 0 to mdmn0 bit y es n o y es n o communication continued? y es y es clearing sau1en and sau0en bits of per0 register to 0 <2> <3> <4> <5> transmitting next data? buffer empty interrupt generated? transfer end interrupt generated? tsfmn = 1? writing 1 to mdmn0 bit <6> caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. remark <1> to <6> in the figure correspond to <1> to <6> in figure 14-52 timing chart of slave transmission (in continuous transmission mode) .
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 505 jun 20, 2011 14.5.5 slave reception slave reception is that the 78k0r/lx3 microcontrollers receiv e data from another device in the state of a transfer clock being input from another device. 3-wire serial i/o csi00 csi01 csi10 csi20 target channel channel 0 of sau0 channel 1 of sau0 channel 2 of sau0 channel 0 of sau1 pins used sck00, si00 sck01, si01 sck10, si10 sck20, si20 intcsi00 intcsi01 intcsi10 intcsi20 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag overrun error detection flag (ovfmn) only transfer data length 7 or 8 bits transfer rate max. f mck /6 [mhz] notes 1, 2 data phase selectable by dapmn bit ? dapmn = 0: data input starts from the start of the operation of the serial clock. ? dapmn = 1: data input starts half a clock bef ore the start of the serial clock operation. clock phase selectable by ckpmn bit ? ckpmn = 0: forward ? ckpmn = 1: reverse data direction msb or lsb first notes 1. because the external serial clock input to pins sck 00, sck01, sck10, and sck20 is sampled internally and used, the fastest transfer rate is f mck /6 [mhz]. 2. use this operation within a range that satisfies t he conditions above and the ac characteristics in the electrical specifications (see chapter 31 electrical specifications ). remarks 1. f mck : operation clock (mck) frequency of target channel 2. for 78k0r/lf3, csi00 and csi01 are not mounted. 3. for 78k0r/lg3, csi01 is not mounted.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 506 jun 20, 2011 (1) register setting figure 14-54. example of contents of regist ers for slave reception of 3-wire serial i/o (csi00, csi01, csi10, csi20) (a) serial output register m (som) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 som 0 0 0 0 1 ckom2 ckom1 ckom0 0 0 0 0 1 som2 som1 som0 (b) serial output enable register m (soem) ? cl ears only the bits of the target channel to 0. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soem 0 0 0 0 0 0 0 0 0 0 0 0 0 soem2 0/1 soem1 0/1 soem0 0/1 (c) serial channel start register m (ssm) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssm 0 0 0 0 0 0 0 0 0 0 0 0 ssm3 ssm2 0/1 ssm1 0/1 ssm0 0/1 (d) serial mode register mn (smrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cksmn 0/1 ccsmn 1 0 0 0 0 0 stsmn 0 0 sismn0 0 1 0 0 mdmn2 0 mdmn1 0 mdmn0 0 operation mode of channel n 0: transfer end interrupt (e) serial communication operati on setting register mn (scrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txemn 0 rxemn 1 dapmn 0/1 ckpmn 0/1 0 eocmn 0 ptcmn1 0 ptcmn0 0 dirmn 0/1 0 slcmn1 0 slcmn0 0 0 dlsmn2 1 dlsmn1 1 dlsmn0 0/1 (f) serial data register mn (sdrmn) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn 0000000 (baud rate setting) 0 receive data register remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20) : setting is fixed in the csi slave reception mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 507 jun 20, 2011 (2) operation procedure figure 14-55. initial setting procedure for slave reception caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. figure 14-56. procedure for stopping slave reception starting initial settings setting per0 register setting spsm register setting smrmn register setting scrmn register setting sdrmn register setting port writing to ssm register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set bits 15 to 9 to 0000000b for baud rate setting. enable data input and clock input of the target channel by setting a port register and a port mode register. set the ssmn bit of the target channel to 1 to set semn = 1. wait for a clock from the master. starting setting to stop setting stm register stopping communication write 1 to the stmn bit of the target channel. stop communication in midway.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 508 jun 20, 2011 figure 14-57. procedure for resuming slave reception starting setting for resumption port manipulation changing setting of spsm register changing setting of smrmn register changing setting of som register port manipulation writing to ssm register starting communication disable clock output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if the setting of the smrmn register is incorrect. manipulate the ckomn bit and enable reception. enable clock output of the target channel by setting a port register and a port mode register. set the ssmn bit of the target channel to 1 to set semn = 1. wait for a clock from the master. (essential) (selective) (selective) (selective) (essential) (essential) (essential) change the setting if the setting of the scrmn register is incorrect. (selective) changing setting of scrmn register cleared by using sirmn register if fef, pef, or ovf flag remains set. (selective) clearing error flag clear the soem register to 0 and stop data output of the target channel. (essential) changing setting of soem register manipulating target for communication stop the target for communication or wait until the target completes its operation. change the setting if the setting of the sdrmn register is incorrect. (selective) changing setting of sdrmn register (essential)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 509 jun 20, 2011 (3) processing flow (in single-reception mode) figure 14-58. timing chart of slave reception (in single-rec eption mode) (type 1: dapmn = 0, ckpmn = 0) ssmn semn sdrmn sckp pin sip pin shift register mn intcsip tsfmn stmn data reception (8-bit length) data reception (8-bit length) data reception (8-bit length) receive data 3 receive data 2 receive data 1 receive data 1 receive data 2 receive data 3 read read read reception & shift operation reception & shift operation reception & shift operation remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 510 jun 20, 2011 figure 14-59. flowchart of slave reception (in singl e-reception mode) starting csi communication writing 1 to ssmn bit writing 1 to stmn bit perform initial setting when semn = 0. smrmn, scrmn: setting communication sdrmn[15:9]: setting transfer rate som, soem: setting sckp output transfer end interrupt generated? reception completed? no no yes yes setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register port manipulation clearing sau1en and sau0en bits of per0 register to 0 end of communication reading siop (=sdrmn[7:0]) register starting reception caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 511 jun 20, 2011 14.5.6 slave transmission/reception slave transmission/reception is that t he 78k0r/lx3 microcontrollers transmit/receive data to/from another device in the state of a transfer clock being input from another device. 3-wire serial i/o csi00 csi01 csi10 csi20 target channel channel 0 of sau0 channel 1 of sau0 channel 2 of sau0 channel 0 of sau1 pins used sck00, si00, so00 sck01, si01, so01 sck10, si10, so10 sck20, si20, so20 intcsi00 intcsi01 intcsi10 intcsi20 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag overrun error detection flag (ovfmn) only transfer data length 7 or 8 bits transfer rate max. f mck /6 [mhz] notes 1, 2 data phase selectable by dapmn bit ? dapmn = 0: data i/o starts from the start of the operation of the serial clock. ? dapmn = 1: data i/o starts half a clock befo re the start of the serial clock operation. clock phase selectable by ckpmn bit ? ckpmn = 0: forward ? ckpmn = 1: reverse data direction msb or lsb first notes 1. because the external serial clock input to pins sck 00, sck01, sck10, and sck20 is sampled internally and used, the fastest transfer rate is f mck /6 [mhz]. 2. use this operation within a range t hat satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 31 electrical specifications ). remarks 1. f mck : operation clock (mck) frequency of target channel 2. for 78k0r/lf3, csi00 and csi01 are not mounted. 3. for 78k0r/lg3, csi01 is not mounted.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 512 jun 20, 2011 (1) register setting figure 14-60. example of contents of registers fo r slave transmission/recepti on of 3-wire serial i/o (csi00, csi01, csi10, csi20) (a) serial output register m (som) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 som 0 0 0 0 1 ckom2 ckom1 ckom0 0 0 0 0 1 som2 0/1 som1 0/1 som0 0/1 (b) serial output enable register m (soem) ? se ts only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soem 0 0 0 0 0 0 0 0 0 0 0 0 0 soem2 0/1 soem1 0/1 soem0 0/1 (c) serial channel start register m (ssm) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssm 0 0 0 0 0 0 0 0 0 0 0 0 ssm3 ssm2 0/1 ssm1 0/1 ssm0 0/1 (d) serial mode register mn (smrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cksmn 0/1 ccsmn 1 0 0 0 0 0 stsmn 0 0 sismn0 0 1 0 0 mdmn2 0 mdmn1 0 mdmn0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt (e) serial communication operati on setting register mn (scrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txemn 1 rxemn 1 dapmn 0/1 ckpmn 0/1 0 eocmn 0 ptcmn1 0 ptcmn0 0 dirmn 0/1 0 slcmn1 0 slcmn0 0 0 dlsmn2 1 dlsmn1 1 dlsmn0 0/1 (f) serial data register mn (sdrmn) (lower 8 bits: siop) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn 0000000 (baud rate setting) 0 transmit data setting/receive data register remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20) : setting is fixed in the csi slave transmission/reception mode, : setting di sabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user siop
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 513 jun 20, 2011 (2) operation procedure figure 14-61. initial setting proce dure for slave transmission/reception caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. starting initial setting setting per0 register setting spsm register setting smrmn register setting scrmn register setting sdrmn register setting som register changing setting of soem register setting port writing to ssm register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set bits 15 to 9 to 0000000b for baud rate setting. manipulate the somn bit and set an initial output level. set the soemn bit to 1 and enable data output of the target channel. enable data output of the target channel by setting a port register and a port mode register. set the ssmn bit of the target channel to 1 to set semn = 1. set transmit data to the siop register (bits 7 to 0 of the sdrmn register) and wait for a clock from the master.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 514 jun 20, 2011 figure 14-62. procedure for stopping slave transmission/reception remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the som register (see figure 14-63 procedure for resu ming slave transmission/reception ). starting setting to stop setting stm register write 1 to the stmn bit of the target channel. changing setting of soem register stopping communication set the soem register and stop the output of the target channel. stop communication in midway.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 515 jun 20, 2011 figure 14-63. procedure for resu ming slave transmission/reception starting setting for resumption manipulating target for communication port manipulation changing setting of spsm register changing setting of smrmn register changing setting of som register stop the target fo r communication or wait until the target completes its operation. disable data output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if the setting of the smrmn register is incorrect. manipulate the somn bit and set an initial output level. (essential) (essential) ( selective ) (selective) (selective) clearing error flag (selective) cleared by using sirmn registe r if fef, pef, or ovf flag remains set. changing setting of sdrm register change the setting if an incorrect division ratio of the operation clock is set. ( selective ) changing setting of scrmn register change the setting if the setting of the scrmn register is incorrect. ( selective ) changing setting of soem register set the soem register and stop the output of the target channel. (selective) changing setting of soem register port manipulation writing to ssm register set the soem register and enable the output of the target channel. enable data output of the target channel by setting a port register and a port mode register. set the ssmn bit of the target channel to 1 to set semn = 1. (selective) (essential) (essential) starting communication starting target for communication set transmit data to the siop register (bits 7 to 0 of the sdrmn register) and wait for a clock from the master. start the target for communication. (essential) (essential)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 516 jun 20, 2011 (3) processing flow (in single -transmission/reception mode) figure 14-64. timing chart of sl ave transmission/recept ion (in single-transmi ssion/reception mode) (type 1: dapmn = 0, ckpmn = 0) ssmn semn sdrmn sckp pin sip pin shift register mn intcsip tsfmn sop pin stmn data transmission/reception (8-bit length) receive data 3 receive data 2 receive data 1 transmit data 1 transmit data 2 transmit data 3 receive data 2 receive data 3 write read write read read write transmit data 3 transmit data 2 transmit data 1 reception & shift operation reception & shift operation reception & shift operation receive data 1 data transmission/reception (8-bit length) data transmission/reception (8-bit length) remark m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 517 jun 20, 2011 figure 14-65. flowchart of slave transmission/ reception (in single- tran smission/reception mode) starting csi communication writing 1 to ssmn bit writing transmit data to siop (=sdrmn[7:0]) writing 1 to stmn bit perform initial setting when semn = 0. smrmn, scrmn: setting communication sdrmn[15:9] : setting transfer rate som, soem : setting output transfer end interrupt generated? transmission/reception completed? no no yes yes setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register port manipulation clearing sau1en and sau0en bits of per0 register to 0 end of communication reading siop (=sdrmn[7:0]) register starting transmission/reception caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 518 jun 20, 2011 (4) processing flow (in continu ous transmission/reception mode) figure 14-66. timing chart of sla ve transmission/reception (in continuous transmission/reception mode) (type 1: dapmn = 0, ckpmn = 0) ssmn semn sdrmn sckp pin sip pin shift register mn intcsip tsfmn sop pin bffmn mdmn0 stmn <4> <5> transmit data 1 transmit data 3 receive data 3 write read read read write <1> <2> <3> <2> <3> <4> <2> <7> <8> ( note 1 ) transmit data 2 write <6> <3> ( note 2 ) ( note 2 ) reception & shift operation receive data 2 receive data 1 receive data 1 receive data 2 receive data 3 transmit data 3 transmit data 2 transmit data 1 data transmission/reception (8-bit length) reception & shift operation reception & shift operation data transmission/reception (8-bit length) data transmission/reception (8-bit length) notes 1. when transmit data is written to the sdrmn register while bffmn = 1, the transmit data is overwritten. 2. the transmit data can be read by r eading the sdrmn register during this period. at this time, the transfer operation is not affected. caution the mdmn0 bit can be rewr itten even during operation. however, rewrite it before transfer of the last bit is started, so that it will be rewritten before the transfer end interrupt of the last transmit data. remarks 1. <1> to <8> in the figure correspond to <1> to <8> in figure 14-67 flowchart of slave transmission/reception (in contin uous transmission/reception mode ). 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 2), p: csi number (p = 00, 01, 10, 20)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 519 jun 20, 2011 figure 14-67. flowchart of slave transmission/recep tion (in continuous transmission/reception mode) starting csi communication writing 1 to ssmn bit reading receive data to siop (=sdrmn[7:0]) writing 1 to stmn bit perform initial setting when semn = 0. <1> select the buffer empty interrupt. smrmn, scrmn: setting communication sdrmn[15:9]: setting transfer rate som, soem: setting output y es y es n o n o setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register port manipulation end of communication clearing 0 to mdmn0 bit n o transfer end interrupt generated? y es n o communication continued? y es y es clearing sau1en and sau0en bits of per0 register to 0 communication data exists? writing transmit data to siop (=sdrmn[7:0]) tsfmn = 1? reading receive data to siop (=sdrmn[7:0]) writing 1 to mdmn0 bit buffer empty interrupt generated? <2> <3> <5> <6> <7> <4> <8> n o caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. remark <1> to <8> in the figure correspond to <1> to <8> in figure 14-66 timing chart of slave transmission/reception (in continuo us transmission/reception mode) .
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 520 jun 20, 2011 14.5.7 calculating transfer clock frequency the transfer clock frequency for 3-wire serial i/o (csi00, csi 01, csi10, csi20) communic ation can be calculated by the following expressions. (1) master (transfer clock frequency) = {operation clock (mck) frequency of target channel} (sdrmn[15:9] + 1) 2 [hz] (2) slave (transfer clock frequency) = {frequency of serial clock (sck) supplied by master} note [hz] note the permissible maximum frequency is the smaller of f clk /6 and f mck /2. remarks 1. the value of sdrmn[15:9] is t he value of bits 15 to 9 of t he sdrmn register (0000000b to 1111111b) and therefore is 0 to 127. 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 2) the operation clock (mck) is determined by serial clock se lect register m (spsm) and bit 15 (cksmn) of serial mode register mn (smrmn).
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 521 jun 20, 2011 table 14-2. selection of operation clock smrmn register spsm register operation clock (mck) note1 cksmn prs m13 prs m12 prs m11 prs m10 prs m03 prs m02 prs m01 prs m00 f clk = 20 mhz x x x x 0 0 0 0 f clk 20 mhz x x x x 0 0 0 1 f clk /2 10 mhz x x x x 0 0 1 0 f clk /2 2 5 mhz x x x x 0 0 1 1 f clk /2 3 2.5 mhz x x x x 0 1 0 0 f clk /2 4 1.25 mhz x x x x 0 1 0 1 f clk /2 5 625 khz x x x x 0 1 1 0 f clk /2 6 313 khz x x x x 0 1 1 1 f clk /2 7 156 khz x x x x 1 0 0 0 f clk /2 8 78.1 khz x x x x 1 0 0 1 f clk /2 9 39.1 khz x x x x 1 0 1 0 f clk /2 10 19.5 khz x x x x 1 0 1 1 f clk /2 11 9.77 khz 0 x x x x 1 1 1 1 inttm02 if m = 0, inttm03 if m = 1 note2 0 0 0 0 x x x x f clk 20 mhz 0 0 0 1 x x x x f clk /2 10 mhz 0 0 1 0 x x x x f clk /2 2 5 mhz 0 0 1 1 x x x x f clk /2 3 2.5 mhz 0 1 0 0 x x x x f clk /2 4 1.25 mhz 0 1 0 1 x x x x f clk /2 5 625 khz 0 1 1 0 x x x x f clk /2 6 313 khz 0 1 1 1 x x x x f clk /2 7 156 khz 1 0 0 0 x x x x f clk /2 8 78.1 khz 1 0 0 1 x x x x f clk /2 9 39.1 khz 1 0 1 0 x x x x f clk /2 10 19.5 khz 1 0 1 1 x x x x f clk /2 11 9.77 khz 1 1 1 1 1 x x x x inttm02 if m = 0, inttm03 if m = 1 note2 other than above setting prohibited notes 1. when changing the clock selected for f clk (by changing the system clock control register (ckc) value), do so after having stopped (stm = 000fh) the opera tion of the serial array unit (saum). when selecting inttm02 and inttm03 for the operation clock, also stop the timer array unit (tau0) (tt0 = 00ffh). 2. saum can be operated at a fixed division rati o of the subsystem clock, regardless of the f clk frequency (main system clock, subsystem clock), by operating the interval timer for which f sub /4 has been selected as the count clock (setting tis02 (if m = 0) or tis03 (if m = 1) of the tis0 register to 1) and selecting inttm02 and inttm03 by using the spsm r egister in channels 2 and 3 of tau0. when changing f clk , however, saum and tau0 must be stopped as described in note 1 above. remarks 1. x: don?t care 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 2)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 522 jun 20, 2011 14.6 operation of uart (uart0, uart1, uart2, uart3) communication this is a start-stop synchronization function using two line s: serial data transmission (txd) and serial data reception (rxd) lines. it transmits or receives data in asynchronization with the party of communication (by using an internal baud rate). full-duplex uart communication can be realized by using two channels, one dedicated to transmission (even channel) and the other to reception (odd channel). [data transmission/reception] ? data length of 5, 7, or 8 bits ? select the msb/lsb first ? level setting of transmit/recei ve data and select of reverse ? parity bit appending and parity check functions ? stop bit appending [interrupt function] ? transfer end interrupt/buffer empty interrupt ? error interrupt in case of framing error, parity error, or overrun error [error detection flag] ? framing error, parity error, or overrun error the lin-bus is supported in uart3 (2, 3 channels of unit 1) [lin-bus functions] ? wakeup signal detection ? sync break field (sbf) detection ? sync field measurement, baud rate calculation uart0 uses channels 0 and 1 of sau0. uart1 uses channels 2 and 3 of sau0. uart2 uses channels 0 and 1 of sau1. uart3 uses channels 2 and 3 of sau1. unit channel used as csi used as uart used as simplified i 2 c 0 csi00 uart0 ? 1 csi01 ? 2 csi10 uart1 iic10 0 3 ? ? 0 csi20 iic20 1 ? uart2 ? 2 ? uart3 (supporting lin-bus) ? 1 3 ? ? caution when using serial array units 0 and 1 as uart s, the channels of both th e transmitting side (even- number channel) and the receiving side (odd-n umber channel) can be used only as uarts. remark for 78k0r/lf3, uart0 is not mounted. external interrupt (intp0) or timer array unit (tau) is used.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 523 jun 20, 2011 uart performs the following four types of communication operations. ? uart transmission (see 14.6.1 .) ? uart reception (see 14.6.2 .) ? lin transmission (uart3 only) (see 14.6.3 .) ? lin reception (uart 3 only) (see 14.6.4 .) 14.6.1 uart transmission uart transmission is an operation to transmit data fr om the 78k0r/lx3 microcontrollers to another device asynchronously (start-stop synchronization). of two channels used for uart, the even channel is used for uart transmission. uart uart0 uart1 uart2 uart3 target channel channel 0 of sau0 channel 2 of sau0 channel 0 of sau1 channel 2 of sau1 pins used txd0 txd1 txd2 txd3 intst0 intst1 intst2 intst3 interrupt transfer end interrupt (in single-transfer mode) or buff er empty interrupt (in continuous transfer mode) can be selected. error detection flag none transfer data length 5, 7, or 8 bits transfer rate max. f mck /6 [bps] (sdrmn [15:9] = 2 or more), min. f clk /(2 2 11 128) [bps] note data phase forward output (default: high level) reverse output (default: low level) parity bit the following selectable ? no parity bit ? appending 0 parity ? appending even parity ? appending odd parity stop bit the following selectable ? appending 1 bit ? appending 2 bits data direction msb or lsb first note use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 31 electrical specifications ). remarks 1. f mck : operation clock (mck) frequency of target channel f clk : system clock frequency 2. for 78k0r/lf3, uart0 is not mounted.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 524 jun 20, 2011 (1) register setting figure 14-68. example of contents of registers for uart transmission of uart (uart0, uart1, uart2, uart3) (1/2) (a) serial output register m (som) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 som 0 0 0 0 1 ckom2 ckom1 ckom0 0 0 0 0 1 som2 0/1 note som1 som0 0/1 note (b) serial output enable register m (soem) ? se ts only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soem 0 0 0 0 0 0 0 0 0 0 0 0 0 soem2 0/1 soem1 soem0 0/1 (c) serial channel start register m (ssm) ? sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssm 0 0 0 0 0 0 0 0 0 0 0 0 ssm3 ssm2 0/1 ssm1 ssm0 0/1 (d) serial output level register m (solm) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 solm 0 0 0 0 0 0 0 0 0 0 0 0 0 solm2 0/1 0 solm0 0/1 0: forward (normal) transmission 1: reverse transmission (e) serial mode register mn (smrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cksmn 0/1 ccsmn 0 0 0 0 0 0 stsmn 0 0 sismn0 0 1 0 0 mdmn2 0 mdmn1 1 mdmn0 0/1 operation mode of channel n 0: transfer end interrupt 1: buffer empty interrupt note before transmission is started, be sure to set to 1 when the solmn bit of the target channel is set to 0, and set to 0 when the solmn bit of the target channel is set to 1. the value varies depending on the communication data during communication operation. remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), q: uart number (q = 0 to 3) : setting is fixed in the uart transmission mode, : setting disabled (fixed by hardware) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 525 jun 20, 2011 figure 14-68. example of contents of registers for uart transmission of uart (uart0, uart1, uart2, uart3) (2/2) (f) serial communication operation setting register mn (scrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txemn 1 rxemn 0 dapmn 0 ckpmn 0 0 eocmn 0 ptcmn1 0/1 ptcmn0 0/1 dirmn 0/1 0 slcmn1 0/1 slcmn0 0/1 0 dlsmn2 1 dlsmn1 0/1 dlsmn0 0/1 setting of stop bit 01b: appending 1 bit 10b: appending 2 bits setting of parity bit 00b: no parity 01b: 0 parity 10b: even parity 11b: odd parity (g) serial data register mn (sdrmn) (lower 8 bits: txdq) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn baud rate setting 0 transmit data setting remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), q: uart number (q = 0 to 3) : setting is fixed in the uart transmission mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user txdq
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 526 jun 20, 2011 (2) operation procedure figure 14-69. initial setting procedure for uart transmission caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. starting initial setting setting per0 register setting spsm register setting smrmn register setting scrmn register setting sdrmn register setting som register setting port changing setting of soem register writing to ssm register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the somn bit and set an initial output level. enable data output of the target channel by setting a port register and a port mode register. set the soemn bit to 1 and enable data output of the target channel. set the ssmn bit of the target channel to 1 to set semn = 1. set transmit data to the txdq register (bits 7 to 0 of the sdrmn register) and start communication. changing setting of solm register set an output data level.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 527 jun 20, 2011 figure 14-70. procedure for stopping uart transmission remark even after communication is stopped, the pin level is retained. to resume the operation, re-set the som register (see figure 14-71 procedure for resuming uart transmission ). starting setting to stop setting stm register write 1 to the stmn bit of the target channel. changing setting of soem register stopping communication set the soemn bit to 0 and stop the output. stop communication in midway.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 528 jun 20, 2011 figure 14-71. procedure for resuming uart transmission port manipulation changing setting of spsm register changing setting of sdrm register changing setting of smrmn register changing setting of som register port manipulation writing to ssm register starting communication disable data output of the target channel by setting a port register and a port mode register. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smrmn register is incorrect. manipulate the somn bit and set an initial output level. enable data output of the target channel by setting a port register and a port mode register. set the ssmn bit of the target channel to 1 to set semn = 1. sets transmit data to the txdq register (bits 7 to 0 of the sdrmn register) and start communication. (essential) (selective) (essential) changing setting of soem register set the soemn bit to 1 and enable output. changing setting of soem register clear the soemn bit to 0 and stop output. (essential) changing setting of scrmn register change the setting if the setting of the scrmn register is incorrect. changing setting of solmn register change the setting if the setting of the solmn register is incorrect. starting setting for resumption (essential) (essential) (essential) (essential) (selective) (selective) (selective) (selective)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 529 jun 20, 2011 (3) processing flow (in si ngle-transmission mode) figure 14-72. timing chart of uart tr ansmission (in single-transmission mode) ssmn semn sdrmn txdq pin shift register mn intstq tsfmn p sp st st p sp st p sp stmn data transmission (7-bit length) data transmission (7-bit length) data transmission (7-bit length) transmit data 1 transmit data 2 transmit data 3 transmit data 3 transmit data 2 transmit data 1 shift operation shift operation shift operation remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), q: uart number (q = 0 to 3)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 530 jun 20, 2011 figure 14-73. flowchart of uart tran smission (in single-transmission mode) caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. starting uart communication writing 1 to ssmn bit writing transmit data to txdq (=sdrmn[7:0]) writing 1 to stmn bit perform initial setting when semn = 0. smrmn, scrmn: setting communication sdrmn[15:9]: setting transfer rate solmn: setting output data level som, soem: setting output transfer end interrupt generated? transmission completed? no no yes yes setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register port manipulation end of communication clearing sau1en and sau0en bits of per0 register to 0
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 531 jun 20, 2011 (4) processing flow (in continuous transmission mode) figure 14-74. timing chart of uart transmission (in continuous transmission mode) ssmn semn sdrmn txdq pin shift register mn intstq tsfmn p st st p st p sp bffmn mdmn0 stmn sp sp data transmission (7-bit length) data transmission (7-bit length) transmit data 1 transmit data 2 transmit data 3 transmit data 3 transmit data 2 transmit data 1 shift operation shift operation shift operation <1> <2> <2> <3> ( note ) <2> <3> <5> <3> <4> data transmission (7-bit length) <6> note when transmit data is written to the sdrmn register while bffmn = 1, the transmit data is overwritten. caution the mdmn0 bit can be rewr itten even during operation. however, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data. remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), q: uart number (q = 0 to 3)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 532 jun 20, 2011 figure 14-75. flowchart of uart transmission (in continuous transmission mode) starting uart communication writing 1 to ssmn bit writing transmit data to txdq (=sdrmn[7:0]) writing 1 to stmn bit perform initial setting when semn = 0. <1> select the buffer empty interrupt. smrmn, scrmn: setting communication sdrmn[15:9]: setting transfer rate solmn: setting output data level som, soem: setting output n o n o n o y es setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register port manipulation end of communication clearing 0 to mdmn0 bit y es tsfmn = 1? transfer end interrupt g enerated? n o y es n o communication continued? y es y es clearing sau1en and sau0en bits of per0 register to 0 transmitting next data? <2> <3> buffer empty interrupt generated? writing 1 to mdmn0 bit <4> <5> caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. remark <1> to <5> in the figure correspond to <1> to <5> in figure 14-74 timing chart of uart transmission (in continuous transmission mode) .
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 533 jun 20, 2011 14.6.2 uart reception uart reception is an operation wherein the 78k0r/lx3 mi crocontrollers asynchronously receive data from another device (start-stop synchronization). for uart reception, the odd-number channel of the two c hannels used for uart is used. the smr register of both the odd- and even-numbered channels must be set. uart uart0 uart1 uart2 uart3 target channel channel 1 of sau0 channel 3 of sau0 channel 1 of sau1 channel 3 of sau1 pins used rxd0 rxd1 rxd2 rxd3 intsr0 intsr1 intsr2 intsr3 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error interrupt intsre0 intsre1 intsre2 intsre3 error detection flag ? framing error detection flag (fefmn) ? parity error detection flag (pefmn) ? overrun error detection flag (ovfmn) transfer data length 5, 7 or 8 bits transfer rate max. f mck /6 [bps] (sdrmn [15:9] = 2 or more), min. f clk /(2 2 11 128) [bps] note data phase forward output (default: high level) reverse output (default: low level) parity bit the following selectable ? no parity bit (no parity check) ? appending 0 parity (no parity check) ? appending even parity ? appending odd parity stop bit appending 1 bit data direction msb or lsb first note use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 31 electrical specifications ). remarks 1. f mck : operation clock (mck) frequency of target channel f clk : system clock frequency 2. for 78k0r/lf3, uart0 is not mounted.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 534 jun 20, 2011 (1) register setting figure 14-76. example of contents of registers for uart reception of uart (uart0, uart1, uart2, uart3) (1/2) (a) serial output register m (som) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 som 0 0 0 0 1 ckom2 ckom1 ckom0 0 0 0 0 1 som2 som1 som0 (b) serial output enable register m (soem) ? sets the bits of the target channel to 0. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soem 0 0 0 0 0 0 0 0 0 0 0 0 0 soem2 soem1 0/1 soem0 (c) serial channel start register m (ssm) ? sets only the bits of the target channel is 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssm 0 0 0 0 0 0 0 0 0 0 0 0 ssm3 0/1 ssm2 ssm1 0/1 ssm0 (d) serial mode register mn (smrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cksmn 0/1 ccsmn 0 0 0 0 0 0 stsmn 1 0 sismn0 0/1 1 0 0 mdmn2 0 mdmn1 1 mdmn0 0 0: forward (normal) reception 1: reverse reception operation mode of channel n 0: transfer end interrupt (e) serial mode register mr (smrmr) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmr cksmr 0/1 ccsmr 0 0 0 0 0 0 stsmr 0 0 sismr0 0 1 0 0 mdmr2 0 mdmr1 1 mdmr0 0/1 same setting value as cksmn operation mode of channel r 0: transfer end interrupt 1: buffer empty interrupt (f) serial communication operation setting register mn (scrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txemn 0 rxemn 1 dapmn 0 ckpmn 0 0 eocmn 1 ptcmn1 0/1 ptcmn0 0/1 dirmn 0/1 0 slcmn1 0 slcmn0 1 0 dlsmn2 1 dlsmn1 0/1 dlsmn0 0/1 caution for the uart reception, be sure to set smrmr of channel r that is to be paired with channel n. remark m: unit number (m = 0, 1), n: channel number (n = 1, 3), r: channel number (r = n ? 1), q: uart number (q = 0 to 3) : setting is fixed in the uart reception mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 535 jun 20, 2011 figure 14-76. example of contents of registers for uart reception of uart (uart0, uart1, uart2, uart3) (2/2) (g) serial data register mn (sdrmn) (lower 8 bits: rxdq) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn baud rate setting 0 receive data register caution for the uart reception, be sure to set smrmr of channel r that is to be paired with channel n. remark m: unit number (m = 0, 1), n: channel number (n = 1, 3), r: channel number (r = n ? 1), q: uart number (q = 0 to 3) : setting is fixed in the uart reception mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user rxdq
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 536 jun 20, 2011 (2) operation procedure figure 14-77. initial setting procedure for uart reception caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. figure 14-78. procedure for stopping uart reception starting initial setting setting per0 register setting spsm register setting smrmn and smrmr registers setting scrmn register setting sdrmn register writing to ssm register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. set the ssmn bit of the target channel to 1 to set semn = 1. the start bit is detected. starting setting to stop setting stm register stopping communication write 1 to the stmn bit of the target channel. stop communication in midway.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 537 jun 20, 2011 figure 14-79. procedure for resuming uart reception starting setting for resumption manipulating target for communication changing setting of spsm register changing setting of sdrmn register writing to ssm register starting communication stop the target for communication or wait until the target completes its operation. change the setting if an incorrect division ratio of the operation clock is set. change the setting if an incorrect transfer baud rate is set. change the setting if the setting of the smrmn and smrmr registers is incorrect. set the ssmn bit of the target channel to 1 to set semn = 1. the start bit is detected. (essential) (selective) change the setting if the setting of the scrmn register is incorrect. changing setting of scrmn register cleared by using sirm register if fef, pef, or ovf flag remains set. clearing error flag clear the soem register to 0 and stop data output of the target channel. changing setting of soem register changing setting of smrmn and smrmr registers (essential) (essential) (essential) (selective) (selective) (selective) (selective)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 538 jun 20, 2011 (3) processing flow figure 14-80. timing chart of uart reception ssmn semn sdrmn rxdq pin shift register mn intsrq tsfmn p st st p st p stmn sp sp sp data reception (7-bit length) data reception (7-bit length) data reception (7-bit length) receive data 1 receive data 2 receive data 3 receive data 2 receive data 1 shift operation shift operation shift operation receive data 3 remark m: unit number (m = 0, 1), n: channel number (n = 1, 3), q: uart number (q = 0 to 3)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 539 jun 20, 2011 figure 14-81. flowchart of uart reception caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. starting uart communication writing 1 to ssmn bit writing 1 to stmn bit end of uart communication perform initial setting when semn = 0. smrmn, smrmr, scrmn: setting communication sdrmn[15:9]: setting transfer rate som: set ckomn and somn bits to 1 transfer end interrupt generated? reception completed? no no yes yes starting reception reading rxdq register (sdrmn[7:0]) detecting start bit error interrupt generated? error processing no yes port manipulation clearing sau1en and sau0en bits of per0 register to 0 setting sau1en and sau0en bits of per0 register to 1 setting transfer rate by spsm register
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 540 jun 20, 2011 14.6.3 lin transmission of uart transmission, uart3 supports lin communication. for lin transmission, channel 2 of unit 1 (sau1) is used. uart uart0 uart1 uart2 uart3 support of lin communication not supported not supported not supported supported target channel ? ? ? channel 2 of sau1 pins used ? ? ? txd3 ? ? ? intst3 interrupt transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. error detection flag none transfer data length 8 bits transfer rate max. f mck /6 [bps] (sdrmn [15:9] = 2 or more), min. f clk /(2 2 11 128) [bps] note data phase forward output (default: high level) reverse output (default: low level) parity bit the following selectable ? no parity bit ? appending 0 parity ? appending even parity ? appending odd parity stop bit the following selectable ? appending 1 bit ? appending 2 bits data direction msb or lsb first note use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 31 electrical specifications ). remarks 1. f mck : operation clock (mck) frequency of target channel f clk : system clock frequency 2. for 78k0r/lf3, uart0 is not mounted. lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol designed to reduce the cost of an automobile network. communication of lin is single-master communicatio n and up to 15 slaves can be connected to one master. the slaves are used to control switches, actuators, and sensors, which are connect ed to the master via lin. usually, the master is connected to a network such as can (controller area network). a lin bus is a single-wire bus to which nodes are connected via transceiver conforming to iso9141. according to the protocol of li n, the master transmits a frame by attaching baud rate information to it. a slave receives this frame and corrects a baud rate error from the master. if the baud rate error of a slave is within 15%, communication can be established. figure 14-82 outlines a trans mission operation of lin.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 541 jun 20, 2011 figure 14-82. transmission operation of lin lin bus wakeup signal frame 8 bits note 1 55h transmission data transmission data transmission data transmission data transmission 13-bit sbf transmission note 2 sync break field sync field identification field data field data field checksum field t x d3 (output) intst3 note 3 notes 1. the baud rate is set so as to satisfy the standard of the wakeup signal and data of 00h is transmitted. 2. a sync break field is defined to have a width of 13 bi ts and output a low level. where the baud rate for main transfer is n [bps], therefore, the baud rate of the sync break field is calculated as follows. (baud rate of sync break field) = 9/13 n by transmitting data of 00h at this baud rate, a sync break field is generated. 3. intst3 is output upon completion of transmission. intst3 is also output when sbf transmission is executed. remark the interval between fields is controlled by software.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 542 jun 20, 2011 figure 14-83. flowchart for lin transmission starting lin communication writing 1 to ss12 transmitting wakeup signal frame transmitting sync break field writing 1 to st12 end of lin communication sync break field identification field data field checksum field sync field transfer end interrupt g enerated? transfer end interrupt g enerated? writing 1 to ss12 transmitting 55h wakeup signal frame setting baud rate setting transfer data 00h setting transfer data 00h setting baud rate receiving data
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 543 jun 20, 2011 14.6.4 lin reception of uart reception, uart3 supports lin communication. for lin reception, channel 3 of unit 1 (sau1) is used. uart uart0 uart1 uart2 uart3 support of lin communication not supported not supported not supported supported target channel ? ? ? channel 3 of sau1 pins used ? ? ? rxd3 ? ? ? intsr3 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error interrupt ? ? ? intsre3 error detection flag ? framing error detection flag (fef13) ? parity error detection flag (pef13) ? overrun error detection flag (ovf13) transfer data length 8 bits transfer rate max. f mck /6 [bps] (sdrmn [15:9] = 2 or more), min. f clk /(2 2 11 128) [bps] note data phase forward output (default: high level) reverse output (default: low level) parity bit the following selectable ? no parity bit ? appending 0 parity ? appending even parity ? appending odd parity stop bit the following selectable ? appending 1 bit ? appending 2 bits data direction msb or lsb first note use this operation within a range that satisfies the conditions above and the ac characteristics in the electrical specifications (see chapter 31 electrical specifications ). remarks 1. f mck : operation clock (mck) frequency of target channel f clk : system clock frequency 2. for 78k0r/lf3, uart0 is not mounted. figure 14-84 outlines a rec eption operation of lin.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 544 jun 20, 2011 figure 14-84. reception operation of lin lin bus 13-bit sbf reception sf reception id reception data reception data reception data reception wakeup signal frame sync break field sync field identification field data filed data filed checksum field r x d3 (input) reception interrupt (intsr3) edge detection (intp0) capture timer disable enable disable enable <1> <2> <3> <4> <5> here is the flow of signal processing. <1> the wakeup signal is detected by detecting an interr upt edge (intp0) on a pin. when the wakeup signal is detected, enable reception of uart3 (r xe13 = 1) and wait for sbf reception. <2> when the start bit of sbf is detected, reception is started and serial data is sequentially stored in the rxd3 register (= bits 7 to 0 of the serial data register 13 (s dr13)) at the set baud rate. when the stop bit is detected, the reception end interrupt request (intsr3) is generated. when data of low levels of 11 bits or more is detected as sbf, it is judged that sbf reception has been correctly co mpleted. if data of low le vels of less than 11 bits is detected as sbf, it is judged that an sbf recepti on error has occurred, and the system returns to the sbf reception wait status. <3> when sbf reception has been correctly completed, star t channel 7 of the timer array unit and measure the bit interval (pulse width) of the sync field (see 6.7.5 operation as input signal high-/low-level width measurement ). <4> calculate a baud rate error from the bit interval of sync field (sf). stop uart3 once and adjust (re-set) the baud rate. <5> the checksum field should be distinguished by software. in addition, processing to initialize uart3 after the checksum field is received and to wait for reception of sbf should also be performed by software.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 545 jun 20, 2011 figure 14-85 shows the configuration of a port that manipulates reception of lin. the wakeup signal transmitted from the mast er of lin is received by detecting an ed ge of an external interrupt (intp0). the length of the sync field transmitted fr om the master can be measured by using t he external event capture operation of the timer array unit (tau) to calculate a baud-rate error. by controlling switch of port input (isc0 /isc1), the input source of port input (r xd3) for reception can be input to the external interrupt pin (intp0) and timer array unit (tau). figure 14-85. port configuration for manipulating reception of lin rxd3 input intp0 input channel 7 input of tau p50/rxd3 p120/intp0 p33/ti07 port input switch control (isc0) 0: selects intp0 (p120) 1: selects rxd3 (p50) port mode (pm50) output latch (p50) port mode (pm120) output latch (p120) port input switch control (isc1) 0: selects ti07 (p33) 1: selects rxd3 (p50) selector selector selector selector selector port mode (pm33) output latch (p33) remark isc0, isc1: bits 0 and 1 of the input switch control register (isc) (see figure 14-17 .)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 546 jun 20, 2011 the peripheral functions used for the lin communication operation are as follows. ? external interrupt (intp0); wakeup signal detection usage: to detect an edge of the wakeup si gnal and the start of communication ? channel 7 of timer array unit (tau); baud rate error detection usage: to detect the length of the sync fiel d (sf) and divide it by the number of bits in order to detect an error (the interval of the edge input to rxd3 is measured in the capture mode.) ? channels 2 and 3 (uart3) of serial array unit 1 (sau1)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 547 jun 20, 2011 figure 14-86. flowchart of lin reception starting lin communication detecting low-level width detecting low-level width stopping operation detecting high-level width end of lin communication sync break field identification field data field checksum field sync field sbf detected? writing 1 to st13 writing 1 to ss13 wakeup signal frame setting tau in capture mode (to measure low-level width) detecting low-level width receiving data wakeup detected? setting tau in capture mode (to measure low-/high-level width) detecting low-level width setting uart reception mode calculating baud rate detecting high-level width intp0, tau sau for details, see figure 14-81
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 548 jun 20, 2011 14.6.5 calculating baud rate (1) baud rate calculation expression the baud rate for uart (uart0, uart1, uart2, uart3) communication can be calculated by the following expressions. (baud rate) = {operation clock (mck) frequency of ta rget channel} (sdrmn[15:9] + 1) 2 [bps] caution setting sdrmn [15:9] = (0000000b, 0000001b) is prohibited. remarks 1. when uart is used, the value of sdrmn[15:9] is the value of bits 15 to 9 of the sdrmn register (0000010b to 1111111b) and therefore is 2 to 127. 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 3) the operation clock (mck) is determined by serial cloc k select register m (spsm) and bit 15 (cksmn) of serial mode register mn (smrmn).
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 549 jun 20, 2011 table 14-3. selection of operation clock smrmn register spsm register operation clock (mck) note1 cksmn prs m13 prs m12 prs m11 prs m10 prs m03 prs m02 prs m01 prs m00 f clk = 20 mhz x x x x 0 0 0 0 f clk 20 mhz x x x x 0 0 0 1 f clk /2 10 mhz x x x x 0 0 1 0 f clk /2 2 5 mhz x x x x 0 0 1 1 f clk /2 3 2.5 mhz x x x x 0 1 0 0 f clk /2 4 1.25 mhz x x x x 0 1 0 1 f clk /2 5 625 khz x x x x 0 1 1 0 f clk /2 6 313 khz x x x x 0 1 1 1 f clk /2 7 156 khz x x x x 1 0 0 0 f clk /2 8 78.1 khz x x x x 1 0 0 1 f clk /2 9 39.1 khz x x x x 1 0 1 0 f clk /2 10 19.5 khz x x x x 1 0 1 1 f clk /2 11 9.77 khz 0 x x x x 1 1 1 1 inttm02 if m = 0, inttm03 if m = 1 note2 0 0 0 0 x x x x f clk 20 mhz 0 0 0 1 x x x x f clk /2 10 mhz 0 0 1 0 x x x x f clk /2 2 5 mhz 0 0 1 1 x x x x f clk /2 3 2.5 mhz 0 1 0 0 x x x x f clk /2 4 1.25 mhz 0 1 0 1 x x x x f clk /2 5 625 khz 0 1 1 0 x x x x f clk /2 6 313 khz 0 1 1 1 x x x x f clk /2 7 156 khz 1 0 0 0 x x x x f clk /2 8 78.1 khz 1 0 0 1 x x x x f clk /2 9 39.1 khz 1 0 1 0 x x x x f clk /2 10 19.5 khz 1 0 1 1 x x x x f clk /2 11 9.77 khz 1 1 1 1 1 x x x x inttm02 if m = 0, inttm03 if m = 1 note2 other than above setting prohibited notes 1. when changing the clock selected for f clk (by changing the system clock control register (ckc) value), do so after having stopped (stm = 000fh) the opera tion of the serial array unit (saum). when selecting inttm02 and inttm03 for the operation clock, also stop the timer array unit (tau0) (tt0 = 00ffh). 2. saum can be operated at a fixed division rati o of the subsystem clock, regardless of the f clk frequency (main system clock, subsystem clock), by operating the interval timer for which f sub /4 has been selected as the count clock (setting tis02 (if m = 0) or tis03 (if m = 1) of the tis0 register to 1) and selecting inttm02 and inttm03 by using the spsm r egister in channels 2 and 3 of tau0. when changing f clk , however, saum and tau0 must be stopped as described in note 1 above. remarks 1. x: don?t care 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 3)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 550 jun 20, 2011 (2) baud rate error during transmission the baud rate error of uart (uart0, uart1, uart2, uart3) communication during transmission can be calculated by the following expression. make sure t hat the baud rate at the transmission side is within the permissible baud rate range at the reception side. (baud rate error) = (calculated baud rate value) (target baud rate) 100 ? 100 [%] here is an example of setting a uart baud rate at f clk = 20 mhz. f clk = 20 mhz uart baud rate (target baud rate) operation clock (mck) sdrmn[15:9] calculat ed baud rate error from target baud rate 300 bps f clk /2 9 64 300.48 bps +0.16 % 600 bps f clk /2 8 64 600.96 bps +0.16 % 1200 bps f clk /2 7 64 1201.92 bps +0.16 % 2400 bps f clk /2 6 64 2403.85 bps +0.16 % 4800 bps f clk /2 5 64 4807.69 bps +0.16 % 9600 bps f clk /2 4 64 9615.38 bps +0.16 % 19200 bps f clk /2 3 64 19230.8 bps +0.16 % 31250 bps f clk /2 3 39 31250.0 bps 0.0 % 38400 bps f clk /2 2 64 38461.5 bps +0.16 % 76800 bps f clk /2 64 76923.1 bps +0.16 % 153600 bps f clk 64 153846 bps +0.16 % 312500 bps f clk 31 312500 bps 0.0 %
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 551 jun 20, 2011 (3) permissible baud rate range for reception the permissible baud rate range for reception during uart (uart0, uart1, uart2, uart3) communication can be calculated by the following expression. make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side. 2 k nfr (maximum receivable baud rate) = 2 k nfr ? k + 2 brate 2 k (nfr ? 1) (minimum receivable baud rate) = 2 k nfr ? k ? 2 brate brate: calculated baud rate value at the reception side (see 14.6.5 (1) baud rate calculation expression .) k: sdrmn[15:9] + 1 nfr: 1 data frame length [bits] = (start bit) + (data length) + (parity bit) + (stop bit) figure 14-87. permissible baud rate range fo r reception (1 data frame length = 11 bits) fl 1 data frame (11 fl) (11 fl) min. (11 fl) max. data frame length of sau start bit bit 0 bit 1 bit 7 parity bit permissible minimum data frame length permissible maximum data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 14-87, the timing of latching receive data is determined by the division ratio set by bits 15 to 9 of the serial data register mn (sdrmn) after the start bit is detected. if the last data (stop bit) is received before this latch timing, the data can be correctly received. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 552 jun 20, 2011 14.7 operation of simplified i 2 c (iic10, iic20) communication this is a clocked communication function to communicate with two or more devices by using two lines: serial clock (scl) and serial data (sda). this communication function is designed to execute single communication with devices such as eeprom, flash memory, and a/d converter, and therefore, can be used only by the mast er and does not have a wait detection function. make sure by using software, as well as operating the control registers, t hat the ac specifications of the start and stop conditions are observed. [data transmission/reception] ? master transmission, master reception (onl y master function with a single master) ? ack output function note and ack detection function ? data length of 8 bits (when an address is transmitted, the addr ess is specified by the higher 7 bi ts, and the least significant bit is used for r/w control.) ? manual generation of start condition and stop condition [interrupt function] ? transfer end interrupt [error detection flag] ? parity error (ack error) * [functions not supported by simplified i 2 c] ? slave transmission, slave reception ? arbitration loss detection function ? wait detection function note an ack is not output when the last data is being received by writing 0 to the soemn (soem register) bit and stopping the output of serial communication data. see 14.7.3 (2) processing flow for details. remarks 1. to use the full-function i 2 c bus, see chapter 15 serial interface iica . 2. m: unit number (m = 0, 1), n: channel number (n = 0, 2) the channels supporting simplified i 2 c (iic10, iic20) are channel 2 of sau0 and channel 0 of sau1. unit channel used as csi used as uart used as simplified i 2 c 0 csi00 ? 1 csi01 uart0 ? 2 csi10 uart1 iic10 0 3 ? ? 0 csi20 uart2 iic20 1 ? ? 2 ? ? 1 3 ? uart3 (supporting lin-bus) ?
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 553 jun 20, 2011 simplified i 2 c (iic10, iic20) performs the following four types of communication operations. ? address field transmission (see 14.7.1 .) ? data transmission (see 14.7.2 .) ? data reception (see 14.7.3 .) ? stop condition generation (see 14.7.4 .) 14.7.1 address field transmission address field transmission is a transmission operation that first executes in i 2 c communication to identify the target for transfer (slave). after a start condition is generated, an addre ss (7 bits) and a transfer direction (1 bit) are transmitted i n one frame. simplified i 2 c iic10 iic20 target channel channel 2 of sau0 channel 0 of sau1 pins used scl10, sda10 note scl20, sda20 note intiic10 intiic20 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag parity error detection flag (pefmn) transfer data length 8 bits (transmitted with specifying the higher 7 bits as address and the least significant bit as r/w control) transfer rate max. f clk /4 [mhz] (sdrmn [15:9] = 1 or more) f clk : system clock frequency however, the following condition must be satisfied in each mode of i 2 c. ? max. 400 khz (first mode) ? max. 100 khz (standard mode) data level forward output (default: high level) parity bit no parity bit stop bit appending 1 bit (for ack reception timing) data direction msb first note to perform communication via simplified i 2 c, set the data i/o pins (sda10, sda 20) in the n-ch open-drain output (v dd tolerance) mode (pom14 = 1, pom11 = 1) by us ing the port output mode re gister 1 (pom1) (see 4.3 registers controlling port function for details). when communicating with an external device with a different potential, set the n-ch open-drain output (v dd tolerance) mode (pom15 = 1, pom10 = 1) also for the clock input/output pins (scl10, scl20) (see 4.4.4 connecting to external device wit h different potential (2.5 v, 3 v) for details). remark m: unit number (m = 0, 1), n: channel number (n = 0, 2)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 554 jun 20, 2011 (1) register setting figure 14-88. example of contents of register s for address field transmission of simplified i 2 c (iic10, iic20) (a) serial output register m (som) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 som 0 0 0 0 1 ckom2 0/1 ckom1 ckom0 0/1 0 0 0 0 1 som2 0/1 som1 som0 0/1 start condition is generated by manipulating the somn bit. (b) serial output enable register m (soem) ? sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soem 0 0 0 0 0 0 0 0 0 0 0 0 0 soem2 0/1 soem1 soem0 0/1 soemn = 0 until the start condition is generated, and soemn = 1 after generation. (c) serial channel start register m (ssm) ? sets only the bits of the target channel is 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssm 0 0 0 0 0 0 0 0 0 0 0 0 ssm3 ssm2 0/1 ssm1 ssm0 0/1 (d) serial mode register mn (smrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cksmn 0/1 ccsmn 0 0 0 0 0 0 stsmn 0 0 sismn0 0 1 0 0 mdmn2 1 mdmn1 0 mdmn0 0 operation mode of channel n 0: transfer end interrupt (e) serial communication operati on setting register mn (scrmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txemn 1 rxemn 0 dapmn 0 ckpmn 0 0 eocmn 0 ptcmn1 0 ptcmn0 0 dirmn 0 0 slcmn1 0 slcmn0 1 0 dlsmn2 1 dlsmn1 1 dlsmn0 1 setting of parity bit 00b: no parity setting of stop bit 01b: appending 1 bit (ack) (f) serial data register mn (sdrmn) (lower 8 bits: sior) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn baud rate setting 0 transmit data setting (address + r/w) remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), r: iic number (r = 10, 20) : setting is fixed in the iic mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user sior
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 555 jun 20, 2011 (2) operation procedure figure 14-89. initial setting proce dure for address field transmission caution after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. starting initial setting setting per0 register setting spsm register setting smrmn register setting scrmn register setting sdrmn register setting som register setting port setting som register starting communication release the serial array unit from the reset status and start clock supply. set the prescaler. set an operation mode, etc. set a communication format. set a transfer baud rate. manipulate the somn and ckomn bits and set an initial output level. enable data output, clock output, and the n-ch open-drain output (v dd tolerance) mode of the target channel by setting a port register, a port mode register, and a port output mode register. clear the somn bit to 0 to generate the start condition. set address and r/w to the sior register (bits 7 to 0 of the sdrmn register) and start communication. writing to ssm register set the ssmn bit of the target channel to 1 to set semn = 1. setting som register clear the ckomn bit to 0 to lower the clock output level. changing setting of soem register set the soemn bit to 1 and enable data output of the target channel. secure a wait time so that the specifications of i 2 c on the slave side are satisfied. wait
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 556 jun 20, 2011 (3) processing flow figure 14-90. timing chart of address field transmission d7 d6 d5 d4 d3 d2 d1 d0 r/w d7 d6 ssmn semn soemn sdrmn sclr output sdar output sdar input shift register mn intiicr tsfmn d5 d4 d3 d2 d1 d0 ack address shift operation address field transmission somn bit manipulation ckomn bit manipulation remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), r: iic number (r = 10, 20)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 557 jun 20, 2011 figure 14-91. flowchart of address field transmission starting iic communication writing 0 to somn bit address field transmission completed perform initial setting when semn = 0. smrmn, scrmn: se tting communication spsm, sdrmn[15:9]: setting transfer rate transfer end interrupt g enerated? no yes writing address and r/w data to sior (sdrmn[7:0]) writing 1 to ssmn bit parity error (ack error) flag pefmn = 1 ? no yes ack reception error to data transmission flow and data reception flow writing 1 to soemn bit writing 0 to ckomn bit
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 558 jun 20, 2011 14.7.2 data transmission data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field. after all data are transmitted to the slave, a stop condition is generated and the bus is released. simplified i 2 c iic10 iic20 target channel channel 2 of sau0 channel 0 of sau1 pins used scl10, sda10 note scl20, sda20 note intiic10 intiic20 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag parity error detection flag (pefmn) transfer data length 8 bits transfer rate max. f clk /4 [mhz] (sdrmn [15:9] = 1 or more) f clk : system clock frequency however, the following condition must be satisfied in each mode of i 2 c. ? max. 400 khz (first mode) ? max. 100 khz (standard mode) data level forward output (default: high level) parity bit no parity bit stop bit appending 1 bit (for ack reception timing) data direction msb first note to perform communication via simplified i 2 c, set the data i/o pins (sda10, sda 20) in the n-ch open-drain output (v dd tolerance) mode (pom14 = 1, pom11 = 1) by us ing the port output mode re gister 1 (pom1) (see 4.3 registers controlling port function for details). when communicating with an external device with a different potential, set the n-ch open-drain output (v dd tolerance) mode (pom15 = 1, pom10 = 1) also for the clock input/output pins (scl10, scl20) (see 4.4.4 connecting to external device wit h different potential (2.5 v, 3 v) for details). remark m: unit number (m = 0, 1), n: channel number (n = 0, 2)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 559 jun 20, 2011 (1) register setting figure 14-92. example of contents of regist ers for data transmission of simplified i 2 c (iic10, iic20) (a) serial output register m (som) ? do not manipulate this regi ster during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 som 0 0 0 0 1 ckom2 0/1 note ckom1 ckom0 0/1 note 0 0 0 0 1 som2 0/1 note som1 som0 0/1 note (b) serial output enable register m (soem) ? do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soem 0 0 0 0 0 0 0 0 0 0 0 0 0 soem2 0/1 soem1 soem0 0/1 (c) serial channel start register m (ssm) ? do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssm 0 0 0 0 0 0 0 0 0 0 0 0 ssm3 ssm2 0/1 ssm1 ssm0 0/1 (d) serial mode register mn (smrmn) ? do not manipulate this re gister during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cksmn 0/1 ccsmn 0 0 0 0 0 0 stsmn 0 0 sismn0 0 1 0 0 mdmn2 1 mdmn1 0 mdmn0 0 (e) serial communication operation setting register mn (scrmn) ? do not manipulate the bits of this register, except the txemn and rxemn bits, during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txemn 1 rxemn 0 dapmn 0 ckpmn 0 0 eocmn 0 ptcmn1 0 ptcmn0 0 dirmn 0 0 slcmn1 0 slcmn0 1 0 dlsmn2 1 dlsmn1 1 dlsmn0 1 (f) serial data register mn (sdrmn) (lower 8 bits: sior) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn baud rate setting 0 transmit data setting note the value varies depending on the communication data during communication operation. remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), r: iic number (r = 10, 20) : setting is fixed in the iic mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user sior
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 560 jun 20, 2011 (2) processing flow figure 14-93. timing chart of data transmission d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 ssmn semn soemn sdrmn sclr output sdar output sdar input shift register mn intiicr tsfmn d5 d4 d3 d2 d1 d0 ack shift operation ?l? ?h? ?h? transmit data 1 remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), r: iic number (r = 10, 20) figure 14-94. flowchart of data transmission starting data transmission data transmission completed transfer end interrupt g enerated? no yes writing data to sior (sdrmn[7:0]) no yes ack reception error s top con di t i on generat i on data transfer completed? yes no address field transmission completed parity error (ack error) flag pefmn = 1 ?
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 561 jun 20, 2011 14.7.3 data reception data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field. after all data are received to the slave, a stop condition is generated and the bus is released. simplified i 2 c iic10 iic20 target channel channel 2 of sau0 channel 0 of sau1 pins used scl10, sda10 note scl20, sda20 note intiic10 intiic20 interrupt transfer end interrupt only (setting the buffer empty interrupt is prohibited.) error detection flag none transfer data length 8 bits transfer rate max. f clk /4 [mhz] (sdrmn [15:9] = 1 or more) f clk : system clock frequency however, the following condition must be satisfied in each mode of i 2 c. ? max. 400 khz (first mode) ? max. 100 khz (standard mode) data level forward output (default: high level) parity bit no parity bit stop bit appending 1 bit (ack transmission) data direction msb first note to perform communication via simplified i 2 c, set the data i/o pins (sda10, sda 20) in the n-ch open-drain output (v dd tolerance) mode (pom14 = 1, pom11 = 1) by us ing the port output mode re gister 1 (pom1) (see 4.3 registers controlling port function for details). when communicating with an external device with a different potential, set the n-ch open-drain output (v dd tolerance) mode (pom15 = 1, pom10 = 1) also for the clock input/output pins (scl10, scl20) (see 4.4.4 connecting to external device wit h different potential (2.5 v, 3 v) for details). remark m: unit number (m = 0, 1), n: channel number (n = 0, 2)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 562 jun 20, 2011 (1) register setting figure 14-95. example of contents of regi sters for data reception of simplified i 2 c (iic10, iic20) (a) serial output register m (som) ? do not manipulate this regi ster during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 som 0 0 0 0 1 ckom2 0/1 note ckom1 ckom0 0/1 note 0 0 0 0 1 som2 0/1 note som1 som0 0/1 note (b) serial output enable register m (soem) ? do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soem 0 0 0 0 0 0 0 0 0 0 0 0 0 soem2 0/1 soem1 soem0 0/1 (c) serial channel start register m (ssm) ? do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ssm 0 0 0 0 0 0 0 0 0 0 0 0 ssm3 ssm2 0/1 ssm1 ssm0 0/1 (d) serial mode register mn (smrmn) ? do not manipulate this re gister during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smrmn cksmn 0/1 ccsmn 0 0 0 0 0 0 stsmn 0 0 sismn0 0 1 0 0 mdmn2 1 mdmn1 0 mdmn0 0 (e) serial communication operation setting register mn (scrmn) ? do not manipulate the bits of this register, except the txemn and rxemn bits, during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scrmn txemn 0 rxemn 1 dapmn 0 ckpmn 0 0 eocmn 0 ptcmn1 0 ptcmn0 0 dirmn 0 0 slcmn1 0 slcmn0 1 0 dlsmn2 1 dlsmn1 1 dlsmn0 1 (f) serial data register mn (sdrmn) (lower 8 bits: sior) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdrmn baud rate setting 0 dummy transmit data setting (ffh) note the value varies depending on the communication data during communication operation. remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), r: iic number (r = 10, 20) : setting is fixed in the iic mode, : setting disabled (set to the initial value) : bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: set to 0 or 1 depending on the usage of the user sior
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 563 jun 20, 2011 (2) processing flow figure 14-96. timing chart of data reception (a) when starting data reception d7 d6 d5 d4 d3 d2 d1 d0 ssmn semn soemn sdrmn sclr output sdar output sdar input shift register mn intiicr tsfmn ack stmn txemn = 0 / rxemn = 1 txemn, rxemn txemn = 1 / rxemn = 0 shift operation ?h? dummy data (ffh) receive data (b) when receiving last data d7 d6 d5 d4 d3 d2 d1 d0 d2 d1 d0 stmn semn soemn sdrmn sclr output sdar output sdar input shift register mn intiicr tsfmn receive data receive data output is enabled by serial communication operation output is stopped by serial communication operation nack ack txemn = 0 / rxemn = 1 txemn, rxemn stop condition reception of last byte iic operation stop somn bit manipulation ckomn bit manipulation somn bit manipulation shift operation dummy data (ffh) shift operation dummy data (ffh) remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), r: iic number (r = 10, 20)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 564 jun 20, 2011 figure 14-97. flowchart of data reception caution ack is also output when the last data is received. communication is then completed by setting ?1? to the stmn bit to stop operation and generating a stop condition. starting data reception data reception completed transfer end interrupt g enerated? no yes writing dummy data (ffh) to sior (sdrmn[7:0]) s top con di t i on generat i on yes no reading sior (sdrmn[7:0]) address field tran smission completed writing 1 to stmn bit writing 0 to txemn bit, and 1 to rxemn bit writing 1 to ssmn bit last byte received? yes writing 0 to soemn bit (stopping output by serial communication operation) no data transfer completed?
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 565 jun 20, 2011 14.7.4 stop condition generation after all data are transmitted to or received from the target sl ave, a stop condition is generated and the bus is released. (1) processing flow figure 14-98. timing chart of stop condition generation note during the receive operation, the soemn bit is set to 0 before receiving the last data. remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), r: iic number (r = 10, 20)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 566 jun 20, 2011 figure 14-99. flowchart of stop condition generation 14.7.5 calculating transfer rate the transfer rate for simplified i 2 c (iic10, iic20) communication can be calculated by the following expressions. (transfer rate) = {operation clock (mck) frequency of target channel} (sdrmn[15:9] + 1) 2 caution setting sdrmn [15:9] = 0000000b is prohibi ted. set sdrmn[15:9] to 0000001b or greater. remarks 1. the value of sdrmn[15:9] is t he value of bits 15 to 9 of t he sdrmn register (0000000b to 1111111b) and therefore is 0 to 127. 2. m: unit number (m = 0, 1), n: channel number (n = 0, 2) the operation clock (mck) is determined by serial clock se lect register m (spsm) and bit 15 (cksmn) of serial mode register mn (smrmn). starting generation of stop condition. end of iic communication writing 1 to stmn bit to clear semn to 0. writing 0 to soemn bit writing 1 to somn bit writing 1 to ckomn bit writing 0 to somn bit completion of data transmission/data reception wait secure a wait time so that the specifications of i 2 c on the slave side are satisfied.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 567 jun 20, 2011 table 14-4. selection of operation clock smrmn register spsm register operation clock (mck) note1 cksmn prs m13 prs m12 prs m11 prs m10 prs m03 prs m02 prs m01 prs m00 f clk = 20 mhz x x x x 0 0 0 0 f clk 20 mhz x x x x 0 0 0 1 f clk /2 10 mhz x x x x 0 0 1 0 f clk /2 2 5 mhz x x x x 0 0 1 1 f clk /2 3 2.5 mhz x x x x 0 1 0 0 f clk /2 4 1.25 mhz x x x x 0 1 0 1 f clk /2 5 625 khz x x x x 0 1 1 0 f clk /2 6 313 khz x x x x 0 1 1 1 f clk /2 7 156 khz x x x x 1 0 0 0 f clk /2 8 78.1 khz x x x x 1 0 0 1 f clk /2 9 39.1 khz x x x x 1 0 1 0 f clk /2 10 19.5 khz x x x x 1 0 1 1 f clk /2 11 9.77 khz 0 x x x x 1 1 1 1 inttm02 if m = 0, inttm03 if m = 1 note2 0 0 0 0 x x x x f clk 20 mhz 0 0 0 1 x x x x f clk /2 10 mhz 0 0 1 0 x x x x f clk /2 2 5 mhz 0 0 1 1 x x x x f clk /2 3 2.5 mhz 0 1 0 0 x x x x f clk /2 4 1.25 mhz 0 1 0 1 x x x x f clk /2 5 625 khz 0 1 1 0 x x x x f clk /2 6 313 khz 0 1 1 1 x x x x f clk /2 7 156 khz 1 0 0 0 x x x x f clk /2 8 78.1 khz 1 0 0 1 x x x x f clk /2 9 39.1 khz 1 0 1 0 x x x x f clk /2 10 19.5 khz 1 0 1 1 x x x x f clk /2 11 9.77 khz 1 1 1 1 1 x x x x inttm02 if m = 0, inttm03 if m = 1 note2 other than above setting prohibited notes 1. when changing the clock selected for f clk (by changing the system clock control register (ckc) value), do so after having stopped (stm = 000fh) the opera tion of the serial array unit (saum). when selecting inttm02 and inttm03 for the operation clock, also stop the timer array unit (tau0) (tt0 = 00ffh). 2. saum can be operated at a fixed division rati o of the subsystem clock, regardless of the f clk frequency (main system clock, subsystem clock), by operating the interval timer for which f sub /4 has been selected as the count clock (setting tis02 (if m = 0) or tis03 (if m = 1) of the tis0 register to 1) and selecting inttm02 and inttm03 by using the spsm r egister in channels 2 and 3 of tau0. when changing f clk , however, saum and tau0 must be stopped as described in note 1 above. remarks 1. x: don?t care 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 2)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 568 jun 20, 2011 here is an example of setting an iic transfer rate where mck = f clk = 20 mhz. f clk = 20 mhz iic transfer mode (desired transfer rate) operation clock (mck) sdrmn[15:9] calculated transfer rate error from desired transfer rate 100 khz f clk 99 100 khz 0.0% 400 khz f clk 24 400 khz 0.0%
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 569 jun 20, 2011 14.8 processing procedure in case of error the processing procedure to be followed if an error of eac h type occurs is described in figures 14-100 to 14-102. figure 14-100. processing procedure in case of parity error or overrun error software manipulation hardware status remark reads sdrmn register. bff = 0, and channel n is enabled to receive data. this is to prevent an overrun error if the next reception is completed during error processing. reads ssrmn register. error type is identified and the read value is used to clear error flag. writes sirmn register. error flag is cl eared. error can be cleared only during reading, by writing the value read from the ssrmn register to the sirmn register without modification. figure 14-101. processing procedure in case of framing error software manipulation hardware status remark reads sdrmn register. bff = 0, and channel n is enabled to receive data. this is to prevent an overrun error if the next reception is completed during error processing. reads ssrmn register. error type is identified and the read value is used to clear error flag. writes sirmn register. error flag is cl eared. error can be cleared only during reading, by writing the value read from the ssrmn register to the sirmn register without modification. sets stmn bit to 1. semn = 0, and channel n stops operation. synchronization with other party of communication synchronization with the other party of communication is re-established and communication is resumed because it is considered that a framing error has occurred because the start bit has been shifted. sets ssmn bit to 1. semn = 1, and channel n is enabled to operate. remark m: unit number (m = 0, 1), n: channel number (n = 0 to 3)
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 570 jun 20, 2011 figure 14-102. processing procedure in case of parity error (ack error) in simplified i 2 c mode software manipulation hardware status remark reads sdrmn register. bff = 0, and channel n is enabled to receive data. this is to prevent an overrun error if the next reception is completed during error processing. reads ssrmn register. error type is identified and the read value is used to clear error flag. writes sirmn register. error flag is cl eared. error can be cleared only during reading, by writing the value read from the ssrmn register to the sirmn register without modification. sets stmn bit to 1. semn = 0, and channel n stops operation. creates stop condition. creates start condition. slave is not ready for reception because ack is not returned. therefore, a stop condition is created, the bus is released, and communication is started again from the start condition. or, a restart condition is generated and transmission can be redone from address transmission. sets ssmn bit to 1. semn = 1, and channel n is enabled to operate. remark m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 02, 10
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 571 jun 20, 2011 14.9 relationship between re gister settings and pins tables 14-5 to 14-12 show the relationship between register settings and pins for each channel of serial array units 0 and 1. table 14-5. relationship between register settings and pi ns (channel 0 of unit 0: csi00, uart0 transmission) pin function se 00 note1 md 002 md 001 soe 00 so 00 cko 00 txe 00 rxe 00 pm 80 p80 pm 81 note2 p81 note2 pm 82 p82 operation mode sck00/ intp11 /p80 si00/rxd0/ intp9/ p81 note2 so00/ txd0/p82 0 0 intp9/p81 0 0 1 0 1 1 0 0 note3 note3 note3 note3 note3 note3 operation stop mode intp11/ p80 rxd0/ intp9/p81 p82 0 1 1 0 1 1 1 note3 note3 slave csi00 reception sck00 (input) si00 p82 1 0/1 note4 1 1 0 1 note3 note3 0 1 slave csi00 transmission sck00 (input) intp9/p81 so00 1 0/1 note4 1 1 1 1 1 0 1 slave csi00 transmission/ reception sck00 (input) si00 so00 0 1 0/1 note4 0 1 0 1 1 note3 note3 master csi00 reception sck00 (output) si00 p82 1 0/1 note4 0/1 note4 1 0 0 1 note3 note3 0 1 master csi00 transmission sck00 (output) intp9/p81 so00 0 0 1 0/1 note4 0/1 note4 1 1 0 1 1 0 1 master csi00 transmission/ reception sck00 (output) si00 so00 1 0 1 1 0/1 note4 1 1 0 note3 note3 note3 note3 0 1 uart0 transmission note5 intp11/ p80 rxd0/ intp9/p81 txd0 notes 1. the se0 register is a read-only status register which is set using the ss0 and st0 registers. 2. when channel 1 of unit 0 is set to uart0 reception, this pin becomes an rxd0 function pin (refer to table 14-6 ). in this case, operation stop mode or uart0 trans mission must be selected for channel 0 of unit 0. 3. this pin can be set as a port function pin. 4. this is 0 or 1, depending on the communication operation. for details, refer to 14.3 (12) serial output register m (som) . 5. when using uart0 transmission and reception in a pair, set channel 1 of unit 0 to uart0 reception (refer to table 14-6 ). remarks 1. x: don?t care 2. for 78k0r/lf3, the channel 0 of unit 0 is not mounted.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 572 jun 20, 2011 table 14-6. relationship between register settings and pins (channel 1 of unit 0: csi01, uart0 reception) pin function se 01 note1 md 012 md 011 soe 01 so01 cko 01 txe 01 rxe 01 pm 75 p75 pm 76 p76 pm 77 p77 pm 81 note2 p81 note2 operation mode sck01/ kr5/ p75 si01/ kr6/ p76 so01/ kr7/ p77 rxd0/si00/ intp9/ p81 note2 0 0 0 0 1 0 1 1 0 0 note3 note3 note3 note3 note3 note3 note3 note3 operation stop mode kr5/ p75 kr6/p76 kr7/ p77 si00/ intp9/p80 0 1 1 0 1 1 1 note3 note3 note3 note3 slave csi01 reception sck01 (input) si01 kr7/ p77 si00/ intp9/p80 1 0/1 note4 1 1 0 1 note3 note3 0 1 note3 note3 slave csi01 transmission sck01 (input) kr6/p76 so01 si00/ intp9/p80 1 0/1 note4 1 1 1 1 1 0 1 note3 note3 slave csi01 transmission /reception sck01 (input) si01 so01 si00/ intp9/p80 0 1 0/1 note4 0 1 0 1 1 note3 note3 note3 note3 master csi01 reception sck01 (output) si01 kr7/ p77 si00/ intp9/p80 1 0/1 note4 0/1 note4 1 0 0 1 note3 note3 0 1 note3 note3 master csi01 transmission sck01 (output) kr6/p76 so01 si00/ intp9/p80 0 0 1 0/1 note4 0/1 note4 1 1 0 1 1 0 1 note3 note3 master csi01 transmission /reception sck01 (output) si01 so01 si00/ intp9/p80 1 0 1 0 1 1 0 1 note3 note3 note3 note3 note3 note3 1 uart0 reception note5, 6 kr5/ p75 kr6/p76 kr7/ p77 rxd0 notes 1. the se0 register is a read-only status register which is set using the ss0 and st0 registers. 2. when channel 1 of unit 0 is set to uart0 reception, this pin becomes an rxd0 function pin. in this case, set channel 0 of unit 0 to operation stop mode or uart0 transmission (refer to table 14-5 ). when channel 0 of unit 0 is set to csi00, this pin cannot be used as an rxd0 function pin. in this case, set channel 1 of unit 0 to operation stop mode or csi01. 3. this pin can be set as a port function pin. 4. this is 0 or 1, depending on the communication operation. for details, refer to 14.3 (12) serial output register m (som) . 5. when using uart0 transmission and reception in a pair, set channel 0 of unit 0 to uart0 transmission (refer to table 14-5 ). 6. the smr00 register of channel 0 of unit 0 must also be set during uart0 reception. for details, refer to 14.5.2 (1) register setting . remarks 1. x: don?t care 2. for 78k0r/lf3, the channel 1 of unit 0 is not mounted. 3. for 78k0r/lg3, csi01 is not mounted.
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 573 jun 20, 2011 table 14-7. relationship between register settings and pins (channel 2 of unit 0: csi10, uart1 transmission, iic10) pin function se 02 note1 md 022 md 021 soe 02 so 02 cko 02 txe 02 rxe 02 pm 15 p15 pm14 note2 p14 note2 pm13 p13 operation mode sck10/ scl10/ intp7/p15 si10/sda10/ rxd1/intp4 /p14 note2 so10/ txd1/ to04/p13 0 0 intp4/p14 0 1 rxd1/intp4/ p14 0 1 0 0 1 1 0 0 note3 note3 note3 note3 note3 note3 operation stop mode intp7/p15 intp4/p14 to04/p13 0 1 1 0 1 1 1 note3 note3 slave csi10 reception sck10 (input) si10 to04/p13 1 0/1 note4 1 1 0 1 note3 note3 0 1 slave csi10 transmission sck10 (input) intp4/p14 so10 1 0/1 note4 1 1 1 1 1 0 1 slave csi10 transmission /reception sck10 (input) si10 so10 0 1 0/1 note4 0 1 0 1 1 note3 note3 master csi10 reception sck10 (output) si10 to04/p13 1 0/1 note4 0/1 note4 1 0 0 1 note3 note3 0 1 master csi10 transmission sck10 (output) intp4/p14 so10 0 0 1 0/1 note4 0/1 note4 1 1 0 1 1 0 1 master csi10 transmission /reception sck10 (output) si10 so10 1 0 1 1 0/1 note4 1 1 0 note3 note3 note3 note3 0 1 uart1 transmission note5 intp7/p15 rxd1/intp4/ p14 txd1 0 0 1 0 0 0 0/1 note6 0/1 note6 0 1 0 1 0 1 note3 note3 iic10 start condition scl10 sda10 to04/p13 1 0/1 note4 0/1 note4 1 0 0 1 0 1 note3 note3 iic10 address field transmission scl10 sda10 to04/p13 1 0/1 note4 0/1 note4 1 0 0 1 0 1 note3 note3 iic10 data transmission scl10 sda10 to04/p13 1 1 0/1 note4 0/1 note4 0 1 0 1 0 1 note3 note3 iic10 data reception scl10 sda10 to04/p13 0 0 1 0 0 1 0 0 0/1 note7 0/1 note7 0 1 0 1 0 1 note3 note3 iic10 stop condition scl10 sda10 to04/p13 notes 1. the se0 register is a read-only status register which is set using the ss0 and st0 registers. 2. when channel 3 of unit 0 is set to uart1 reception, this pin becomes an rxd1 function pin (refer to table 14-8 ). in this case, operation stop mode or uart1 trans mission must be selected for channel 2 of unit 0. 3. this pin can be set as a port function pin. 4. this is 0 or 1, depending on the communication operation. for details, refer to 14.3 (12) serial output register m (som) . 5. when using uart1 transmission and reception in a pair, set channel 3 of unit 0 to uart1 reception (refer to table 14-8 ). 6. set the cko02 bit to 1 before a start condition is genera ted. clear the so02 bit from 1 to 0 when the start condition is generated. 7. set the cko02 bit to 1 before a stop condition is genera ted. clear the so02 bit from 0 to 1 when the stop condition is generated. remark x: don?t care
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 574 jun 20, 2011 table 14-8. relationship between register settings and pins (channel 3 of un it 0: uart1 reception) pin function se03 note1 md032 md031 txe03 rxe03 pm14 note2 p14 note2 operation mode rxd1/si10/sda10/intp4/ p14 note2 0 0 1 0 0 note3 note3 operation stop mode si10/sda10/intp4/p14 note2 1 0 1 0 1 1 uart1 reception note4, 5 rxd1 notes 1. the se0 register is a read-only status register which is set using the ss0 and st0 registers. 2. when channel 3 of unit 0 is set to uart1 reception, this pin becomes an rxd1 function pin. in this case, set channel 2 of unit 0 to operation stop mode or uart1 transmission (refer to table 14-7 ). when channel 2 of unit 0 is set to csi10 or iic10, this pi n cannot be used as an rxd1 function pin. in this case, set channel 3 of unit 0 to operation stop mode. 3. this pin can be set as a port function pin. 4. when using uart1 transmission and reception in a pair, set channel 2 of unit 0 to uart1 transmission (refer to table 14-7 ). 5. the smr02 register of channel 2 of unit 0 must also be set during uart1 reception. for details, refer to 14.5.2 (1) register setting . remark x: don?t care
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 575 jun 20, 2011 table 14-9. relationship between register settings and pins (channel 0 of unit 1: csi20, uart2 transmission, iic20) pin function se 10 note1 md 102 md 101 soe 10 so 10 cko 10 txe 10 rxe 10 pm 10 p10 pm 11 note2 p11 note2 pm 12 p12 operation mode sck20/ scl20/p10 si20/sda20/ rxd2/intp6/ p11 note2 so20/ txd2/ to02/p12 0 0 intp6/p11 0 1 rxd2/intp6/ p11 0 1 0 0 1 1 0 0 note3 note3 note3 note3 note3 note3 operation stop mode p10 intp6/p11 to02/p12 0 1 1 0 1 1 1 note3 note3 slave csi20 reception sck20 (input) si20 to02/p12 1 0/1 note4 1 1 0 1 note3 note3 0 1 slave csi20 transmission sck20 (input) intp6/p11 so20 1 0/1 note4 1 1 1 1 1 0 1 slave csi20 transmission/reception sck20 (input) si20 so20 0 1 0/1 note4 0 1 0 1 1 note3 note3 master csi20 reception sck20 (output) si20 to02/p12 1 0/1 note4 0/1 note4 1 0 0 1 note3 note3 0 1 master csi20 transmission sck20 (output) intp6/p11 so20 0 0 1 0/1 note4 0/1 note4 1 1 0 1 1 0 1 master csi20 transmission/reception sck20 (output) si20 so20 1 0 1 1 0/1 note4 1 1 0 note3 note3 note3 note3 0 1 uart2 transmission note5 p10 rxd2/intp6/ p11 txd2 0 0 1 0 0 0 0/1 note6 0/1 note6 0 1 0 1 0 1 note3 note3 iic20 start condition scl20 sda20 to02/p12 1 0/1 note4 0/1 note4 1 0 0 1 0 1 note3 note3 iic20 address field transmission scl20 sda20 to02/p12 1 0/1 note4 0/1 note4 1 0 0 1 0 1 note3 note3 iic20 data transmission scl20 sda20 to02/p12 1 1 0/1 note4 0/1 note4 0 1 0 1 0 1 note3 note3 iic20 data reception scl20 sda20 to02/p12 0 0 1 0 0 1 0 0 0/1 note7 0/1 note7 0 1 0 1 0 1 note3 note3 iic20 stop condition scl20 sda20 to02/p12 notes 1. the se1 register is a read-only status register which is set using the ss1 and st1 registers. 2. when channel 1 of unit 1 is set to uart2 reception, this pin becomes an rxd2 function pin (refer to table 14- 10 ). in this case, operation stop mode or uart2 transmission must be selected for channel 0 of unit 1. 3. this pin can be set as a port function pin. 4. this is 0 or 1, depending on the communication operation. for details, refer to 14.3 (12) serial output register m (som) . 5. when using uart2 transmission and reception in a pair, set channel 1 of unit 1 to uart2 reception (refer to table 14-10 ). 6. set the cko10 bit to 1 before a start condition is genera ted. clear the so10 bit from 1 to 0 when the start condition is generated. 7. set the cko10 bit to 1 before a stop condition is genera ted. clear the so10 bit from 0 to 1 when the stop condition is generated. remark x: don?t care
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 576 jun 20, 2011 table 14-10. relationship between register settings and pins (channel 1 of unit 1: uart2 reception) pin function se11 note1 md112 md111 txe11 rxe11 pm11 note2 p11 note2 operation mode si20/sda20/rxd2/ intp6/p11 note2 0 0 1 0 0 note3 note3 operation stop mode si20/sda20/intp6/p11 1 0 1 0 1 1 uart2 reception note4, 5 rxd2 notes 1. the se1 register is a read-only status register which is set using the ss1 and st1 registers. 2. when channel 1 of unit 1 is set to uart2 reception, this pin becomes an rxd2 function pin. in this case, set channel 0 of unit 1 to operation stop mode or uart2 transmission (refer to table 14-9 ). when channel 0 of unit 1 is set to csi20 or iic20, this pi n cannot be used as an rxd2 function pin. in this case, set channel 1 of unit 1 to operation stop mode. 3. this pin can be set as a port function pin. 4. when using uart2 transmission and reception in a pair, set channel 0 of unit 1 to uart2 transmission (refer to table 14-9 ). 5. the smr10 register of channel 0 of unit 1 must also be set during uart2 reception. for details, refer to 14.5.2 (1) register setting . remark x: don?t care
78k0r/lx3 chapter 14 serial array unit r01uh0004ej0501 rev.5.01 577 jun 20, 2011 table 14-11. relationship between register settings a nd pins (channel 2 of unit 1: uart3 transmission) pin function se12 note1 md122 md121 soe12 so12 txe12 rxe12 pm51 p51 operation mode txd3/seg52/p51 0 0 1 0 1 0 0 note2 note2 operation stop mode seg52/p51 1 0 1 1 0/1 note3 1 0 0 1 uart3 transmission note4 txd3 notes 1. the se1 register is a read-only status register which is set using the ss1 and st1 registers. 2. this pin can be set as a port function pin. 3. this is 0 or 1, depending on the communication operation. for details, refer to 14.3 (12) serial output register m (som) . 4. when using uart3 transmission and reception in a pair, set channel 3 of unit 1 to uart3 reception (refer to table 14-12 ). remark x: don?t care table 14-12. relationship between register settings and pins (channel 3 of unit 1: uart3 reception) pin function se13 note1 md132 md131 txe13 rxe13 pm50 p50 operation mode rxd3/seg53/p50 0 0 1 0 0 note2 note2 operation stop mode seg53/p50 1 0 1 0 1 1 uart3 reception note3, 4 rxd3 notes 1. the se1 register is a read-only status register which is set using the ss1 and st1 registers. 2. this pin can be set as a port function pin. 3. when using uart3 transmission and reception in a pair, set channel 2 of unit 1 to uart3 transmission (refer to table 14-11 ). 4. the smr12 register of channel 2 of unit 1 must also be set during uart3 reception. for details, refer to 14.5.2 (1) register setting . remark x: don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 578 jun 20, 2011 chapter 15 serial interface iica 78k0r/lf3 78k0r/lg3 78k0r/lh3 item 80 pins 100 pins 128 pins serial interface iica ? 1 ch 15.1 functions of serial interface iica serial interface iica has the following three modes. (1) operation stop mode this mode is used when serial transfers are not performed. it can therefore be used to reduce power consumption. (2) i 2 c bus mode (multimaster supported) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock (scl0) line and a serial data bus (sda0) line. this mode complies with the i 2 c bus format and the master device can generated ?start condition?, ?address?, ?transfer direction specificatio n?, ?data?, and ?stop condition? data to the slave device, via the serial data bus. the slave device automatically detects thes e received status and data by hardware. this function can simplify the part of application program that controls the i 2 c bus. since the scl0 and sda0 pins are used for open drain outputs, iica requires pull-up resistors for the serial clock line and the serial data bus line. (3) wakeup mode the stop mode can be released by generating an interrupt request signal (intiica) when an extension code from the master device or a local address has been received while in stop mode. this can be set by using the wup bit of iica control register 1 (iicctl1). figure 15-1 shows a block diagram of serial interface iica.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 579 jun 20, 2011 figure 15-1. block diagram of serial interface iica iice dq dfc sda0/ p61 scl0/ p60 intiica iicctl0.stt, spt iics.msts, exc, coi iics.msts, exc, coi f clk lrel wrel spie wtim acke stt spt msts ald exc coi trc ackd std spd stcf iicbsy stcen iicrsv wup cld dad dfc smc pm60 internal bus iica status register (iics) iica control register 0 (iicctl0) slave address register (sva) noise eliminator match signal match signal iica shift register (iica) so latch set clear iicwl trc dfc data hold time correction circuit start condition generator stop condition generator ack generator wakeup controller n-ch open- drain output pm61 noise eliminator bus status detector ack detector stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller start condition detector internal bus iica flag register (iicf) iica control register 1 (iicctl1) n-ch open- drain output output latch (p60) output latch (p61) wup sub-circuit for standby filter filter output control iica shift register (iica) counter iica low-level width setting register (iicwl) iica high-level width setting register (iicwh)
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 580 jun 20, 2011 figure 15-2 shows a serial bus configuration example. figure 15-2. serial bus c onfiguration example using i 2 c bus master cpu1 slave cpu1 address 0 sda0 scl0 serial data bus serial clock + v dd + v dd sda0 scl0 sda0 scl0 sda0 scl0 sda0 scl0 master cpu2 slave cpu2 address 1 slave cpu3 address 2 slave ic address 3 slave ic address n
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 581 jun 20, 2011 15.2 configuration of serial interface iica serial interface iica includes the following hardware. table 15-1. configuration of serial interface iica item configuration registers iica shift register (iica) slave address register (sva) control registers peripheral enable register 0 (per0) iica control register 0 (iicctl0) iica status register (iics) iica flag register (iicf) iica control register 1 (iicctl1) iica low-level width setting register (iicwl) iica high-level width setting register (iicwh) port mode register 6 (pm6) port register 6 (p6) (1) iica shift register (iica) iica is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock. iica can be used for both transmission and reception. the actual transmit and receive operations can be contro lled by writing and reading operations to iica. cancel the wait state and start data transfer by writing data to iica during the wait period. iica can be set by an 8-bit memory manipulation instruction. reset signal generation clears iica to 00h. figure 15-3. format of iica shift register (iica) symbol iica address: fff50h after reset: 00h r/w 76543210 cautions 1. do not write data to iica during data transfer. 2. write or read iica only during the wait pe riod. accessing iica in a communication state other than during the wait period is prohibited. when the device serves as the master, however, iica can be written only once after the comm unication trigger bit (stt) is set to 1. 3. when communication is reserved, write data to iica after the interrupt triggered by a stop condition is detected. (2) slave address register (sva) this register stores seven bits of local addresse s {a6, a5, a4, a3, a2, a1, a0} when in slave mode. sva can be set by an 8-bit memory manipulation instruction. however, rewriting to this register is prohibited wh ile std = 1 (while the start condition is detected). reset signal generation clears sva to 00h.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 582 jun 20, 2011 figure 15-4. format of slave address register (sva) symbol sva address: f0234h after reset: 00h r/w 76543210 0 note a0 a1 a2 a3 a4 a5 a6 note bit 0 is fixed to 0. (3) so latch the so latch is used to retain the sda0 pin?s output level. (4) wakeup controller this circuit generates an interrupt request (intiica) when the address received by this register matches the address value set to the slave address register (sva) or when an extension code is received. (5) serial clock counter this counter counts the serial clocks that are output or in put during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. (6) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiica). an i 2 c interrupt request is generated by the following two triggers. ? falling edge of eighth or ninth clock of the serial clock (set by wtim bit) ? interrupt request generated when a stop co ndition is detected (set by spie bit) remark wtim bit: bit 3 of iica control register 0 (iicctl0) spie bit: bit 4 of iica control register 0 (iicctl0) (7) serial clock controller in master mode, this circuit generates the clock output via the scl0 pin from a sampling clock. (8) serial clock wait controller this circuit controls the wait timing. (9) ack generator, stop condition detector, start condition detector, and ack detector these circuits generate and detect each status. (10) data hold time correction circuit this circuit generates the hold time for data corre sponding to the falling edge of the serial clock. (11) start condition generator this circuit generates a start condition when the stt bit is set to 1. however, in the communication reservat ion disabled status (iicrsv bit = 1) , when the bus is not released (iicbsy bit = 1), start condition requests are ignor ed and the stcf bit is set to 1. (12) stop condition generator this circuit generates a stop condition when the spt bit is set to 1.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 583 jun 20, 2011 (13) bus status detector this circuit detects whether or not the bus is releas ed by detecting start conditions and stop conditions. however, as the bus status cannot be detected immediately following operation, the initial status is set by the stcen bit. remark stt bit: bit 1 of iica control register 0 (iicctl0) spt bit: bit 0 of iica control register 0 (iicctl0) iicrsv bit: bit 0 of iica flag register (iicf) iicbsy bit: bit 6 of iica flag register (iicf) stcf bit: bit 7 of iica flag register (iicf) stcen bit: bit 1 of iica flag register (iicf)
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 584 jun 20, 2011 15.3 registers controlling serial interface iica serial interface iica is controlled by the following eight registers. ? peripheral enable register 0 (per0) ? iica control register 0 (iicctl0) ? iica flag register (iicf) ? iica status register (iics) ? iica control register 1 (iicctl1) ? iica low-level width setting register (iicwl) ? iica high-level width se tting register (iicwh) ? port mode register 6 (pm6) ? port register 6 (p6) (1) peripheral enable register 0 (per0) this register is used to enable or disable supplying t he clock to the peripheral hardware. clock supply to a hardware macro that is not used is stopped in or der to reduce the power consumption and noise. when serial interface iica is used, be sure to set bit 4 (iicaen) of this register to 1. per0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 15-5. format of peripheral enable register 0 (per0) address: f00f0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> per0 rtcen dacen adcen iicaen note sau1en sau0en tau1en tau0en iicaen control of serial interface iica input clock 0 stops supply of input clock. ? sfr used by serial interface iica cannot be written. ? serial interface iica is in the reset status. 1 supplies input clock. ? sfr used by serial interface iica can be read/written. note 78k0r/lg3, 78k0r/lh3 only caution when setting serial interface iica, be sure to set iicaen to 1 firs t. if iicaen = 0, writing to a control register of serial interface iica is ignor ed, and, even if the register is read, only the default value is read. (2) iica control register 0 (iicctl0) this register is used to enable/stop i 2 c operations, set wait timing, and set other i 2 c operations. iicctl0 can be set by a 1-bit or 8-bit memory manipulat ion instruction. however, set the spie, wtim, and acke bits while iice bit = 0 or during the wait period. these bi ts can be set at the same ti me when the iice bit is set from ?0? to ?1?. reset signal generation clea rs this register to 00h.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 585 jun 20, 2011 figure 15-6. format of iica cont rol register 0 (iicctl0) (1/4) address: f0230h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> iicctl0 iice lrel wrel spie wtim acke stt spt iice i 2 c operation enable 0 stop operation. reset the iica status register (iics) note 1 . stop internal operation. 1 enable operation. be sure to set this bit (1) while the scl0 and sda0 lines are at high level. condition for clearing (iice = 0) condition for setting (iice = 1) ? cleared by instruction ? reset ? set by instruction lrel notes 2,3 exit from communications 0 normal operation 1 this exits from the current communications and sets standby mode. this setting is automatically cleared to 0 after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl0 and sda0 lines are set to high impedance. the following flags of iica control register 0 (iicctl0) and iica status register (iics) are cleared to 0. ? stt ? spt ? msts ? exc ? coi ? trc ? ackd ? std the standby mode following exit from communications rema ins in effect until the following communications entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code rece ption occurs after the start condition. condition for clearing (lrel = 0) condition for setting (lrel = 1) ? automatically cleared after execution ? reset ? set by instruction wrel notes 2,3 wait cancellation 0 do not cancel wait 1 cancel wait. this setting is automatic ally cleared after wait is canceled. when wrel is set (wait canceled) during the wait period at the ninth clock pulse in t he transmission status (trc = 1), the sda0 line goes into the high impedance state (trc = 0). condition for clearing (wrel = 0) condition for setting (wrel = 1) ? automatically cleared after execution ? reset ? set by instruction notes 1. the iics register, the stcf and iicbsy bits of the iicf register, and the cld and dad bits of the iicctl1 register are reset. 2. the signal of this bit is invalid while iice is 0. 3. when the lrel and wrel bits are read, 0 is always read. caution if the operation of i 2 c is enabled (iice = 1) when the scl0 line is at high level, the sda0 line is at low level, and dfc of the iicctl1 register is 1, a start condition will be inadvertently detected immediately. immediately after enabling i 2 c to operate (iice = 1), set lrel (1) by using a 1-bit memory manipulation instruction.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 586 jun 20, 2011 figure 15-6. format of iica cont rol register 0 (iicctl0) (2/4) spie note 1 enable/disable generation of interrupt request when stop condition is detected 0 disable 1 enable if wup of the iicctl1 register is 1, no stop condition interrupt will be generated even if spie = 1. condition for clearing (spie = 0) condition for setting (spie = 1) ? cleared by instruction ? reset ? set by instruction wtim note 1 control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, cloc k output is set to low level and wait is set. slave mode: after input of eight clo cks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clo cks, the clock is set to low level and wait is set for master device. an interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit. the setting of this bit is valid when the address tr ansfer is completed. when in master mode, a wait is inserted at the falling edge of the ninth clock during address tr ansfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ack) is issued. however, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtim = 0) condition for setting (wtim = 1) ? cleared by instruction ? reset ? set by instruction acke notes 1, 2 acknowledgment control 0 disable acknowledgment. 1 enable acknowledgment. during t he ninth clock period, the sda0 line is set to low level. condition for clearing (acke = 0) condition for setting (acke = 1) ? cleared by instruction ? reset ? set by instruction notes 1. the signal of this bit is invalid while iice is 0. set this bit during that period. 2. the set value is invalid during address transfer and if the code is not an extension code. when the device serves as a slave and the addresses match, an acknowledgment is generated regardless of the set value.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 587 jun 20, 2011 figure 15-6. format of iica cont rol register 0 (iicctl0) (3/4) stt note start condition trigger 0 do not generate a start condition. 1 when bus is released (in standby state, when iicbsy = 0): if this bit is set (1), a start conditi on is generated (startup as the master). when a third party is communicating: ? when communication reservation function is enabled (iicrsv = 0) functions as the start condition reservation flag. when set to 1, automatically generates a start condition after the bus is released. ? when communication reservation function is disabled (iicrsv = 1) even if this bit is set (1), the stt bit is cleared and the stt clear flag (stcf) is set (1). no start condition is generated. in the wait state (when master device): generates a restart condition after releasing the wait. cautions concerning set timing ? for master reception: cannot be set to 1 during transfer. can be set to 1 only in the waiting period when acke has been cleared to 0 and slave ha s been notified of final reception. ? for master transmission: a start condition cannot be generated normally during the acknowledge period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as spt. ? setting stt to 1 and then setting it again before it is cleared to 0 is prohibited. condition for clearing (stt = 0) condition for setting (stt = 1) ? cleared by setting stt to 1 while communication reservation is prohibited. ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? cleared by lrel = 1 (exit from communications) ? when iice = 0 (operation stop) ? reset ? set by instruction note the signal of this bit is invalid while iice0 is 0. remarks 1. bit 1 (stt) becomes 0 when it is read after data setting. 2. iicrsv: bit 0 of iic flag register (iicf) stcf: bit 7 of iic flag register (iicf)
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 588 jun 20, 2011 figure 15-6. format of iica cont rol register 0 (iicctl0) (4/4) spt stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (terminati on of master device?s transfer). cautions concerning set timing ? for master reception: cannot be set to 1 during transfer. can be set to 1 only in the waiting period when acke has been cleared to 0 and slave has been notified of final reception. ? for master transmission: a st op condition cannot be generated normally during the acknowledge period. therefore, set it during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as stt. ? spt can be set to 1 only when in master mode. ? when wtim has been cleared to 0, if spt is set to 1 duri ng the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level peri od of the ninth clock. wtim should be changed from 0 to 1 during the wait period following the output of eight clocks, and spt should be set to 1 during the wait period that follows the output of the ninth clock. ? setting spt to 1 and then setting it again before it is cleared to 0 is prohibited. condition for clearing (spt = 0) condition for setting (spt = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? cleared by lrel = 1 (exit from communications) ? when iice = 0 (operation stop) ? reset ? set by instruction caution when bit 3 (trc) of the iica status register (iics) is set to 1, wrel is set to 1 during the ninth clock and wait is canceled, after which trc is cleared and the sda0 line is set to high impedance. release the wait performed while the trc bit is 1 (transmission status) by writing to the iica shift register. remark bit 0 (spt) becomes 0 when it is read after data setting.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 589 jun 20, 2011 (3) iica status register (iics) this register indicates the status of i 2 c. iics is read by a 1-bit or 8-bit memory manipulation in struction only when stt = 1 and during the wait period. reset signal generation clea rs this register to 00h. caution reading the iics register while the address ma tch wakeup function is enabled (wup = 1) in stop mode is prohibited. when the wup bit is chan ged from 1 to 0 (wakeup operation is stopped), regardless of the intiica interrupt request, the ch ange in status is not reflected until the next start condition or stop condition is detected. to use the wakeup function, therefore, enable (spie = 1) the interrupt generated by detecting a stop condition and read the iics register after the interrupt has been detected. remark stt: bit 1 of iica control register 0 (iicctl0) wup: bit 7 of iica control register 1 (iicctl1) figure 15-7. format of iica status register (iics) (1/3) address: fff51h after reset: 00h r symbol <7> <6> <5> <4> <3> <2> <1> <0> iics msts ald exc coi trc ackd std spd msts master status check flag 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts = 0) condition for setting (msts = 1) ? when a stop condition is detected ? when ald = 1 (arbitration loss) ? cleared by lrel = 1 (exit from communications) ? when iice changes from 1 to 0 (operation stop) ? reset ? when a start condition is generated ald detection of arbitration loss 0 this status means either that there was no arbitr ation or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. msts is cleared. condition for clearing (ald = 0) condition for setting (ald = 1) ? automatically cleared after iics is read note ? when iice changes from 1 to 0 (operation stop) ? reset ? when the arbitration result is a ?loss?. exc detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc = 0) condition for setting (exc = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel = 1 (exit from communications) ? when iice changes from 1 to 0 (operation stop) ? reset ? when the higher four bits of the received address data is either ?0000? or ?1111? (set at the rising edge of the eighth clock). note this register is also cleared when a 1-bit memory manipulation instruction is ex ecuted for bits other than iics. therefore, when using the ald bit, read the da ta of this bit before the data of the other bits. remark lrel: bit 6 of iica control register 0 (iicctl0) iice: bit 7 of iica control register 0 (iicctl0)
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 590 jun 20, 2011 figure 15-7. format of iica status register (iics) (2/3) coi detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coi = 0) condition for setting (coi = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lrel = 1 (exit from communications) ? when iice changes from 1 to 0 (operation stop) ? reset ? when the received address matches the local address (slave address register (sva)) (set at the rising edge of the eighth clock). trc detection of transmit/receive status 0 receive status (other than transmit status). the sda0 line is set for high impedance. 1 transmit status. the value in the so0 latch is enabled for output to the sda0 line (valid starting at the falling edge of the first byte?s ninth clock). condition for clearing (trc = 0) condition for setting (trc = 1) ? when a stop condition is detected ? cleared by lrel = 1 (exit from communications) ? when the iice bit changes from 1 to 0 (operation stop) ? cleared by wrel = 1 note (wait cancel) ? when the ald bit changes from 0 to 1 (arbitration loss) ? reset ? when not used for communication (msts, exc, coi = 0) ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) ? when a start condition is detected ? when ?0? is input to the first byte?s lsb (transfer direction specification bit) ? when a start condition is generated ? when 0 (master transmission) is output to the lsb (transfer direction specification bit) of the first byte (during address transfer) ? when 1 (slave transmission) is input to the lsb (transfer direction specification bit) of the first byte from the master (during address transfer) note when bit 3 (trc) of the iica status register (iics) is set to 1 (trans mission status), bit 5 (wrel) of iica control register 0 (iicctl0) is set to 1 duri ng the ninth clock and wait is canceled, after which the trc bit is cleared (reception status) and the sd a0 line is set to high impedance. release the wait performed while the trc bit is 1 (transmission status) by writing to the iica shift register. remark lrel: bit 6 of iica control register 0 (iicctl0) iice: bit 7 of iica control register 0 (iicctl0)
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 591 jun 20, 2011 figure 15-7. format of iica status register (iics) (3/3) ackd detection of acknowledge (ack) 0 acknowledge was not detected. 1 acknowledge was detected. condition for clearing (ackd = 0) condition for setting (ackd = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by lrel = 1 (exit from communications) ? when iice changes from 1 to 0 (operation stop) ? reset ? after the sda0 line is set to low level at the rising edge of scl0?s ninth clock std detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect. condition for clearing (std = 0) condition for setting (std = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by lrel = 1 (exit from communications) ? when iice changes from 1 to 0 (operation stop) ? reset ? when a start condition is detected spd detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device ?s communication is terminated and the bus is released. condition for clearing (spd = 0) condition for setting (spd = 1) ? at the rising edge of the address transfer byte?s first clock following setting of th is bit and detection of a start condition ? when iice changes from 1 to 0 (operation stop) ? reset ? when a stop condition is detected remark lrel: bit 6 of iica control register 0 (iicctl0) iice: bit 7 of iica control register 0 (iicctl0) (4) iica flag register (iicf) this register sets the operation mode of i 2 c and indicates the status of the i 2 c bus. iicf can be set by a 1-bit or 8-bit memory manipulation instruction. however, the stcf and iicbsy bits are read- only. the iicrsv bit can be used to enable/disabl e the communication reservation function. stcen can be used to set the initial value of the iicbsy bit. iicrsv and stcen can be written only when the operation of i 2 c is disabled (bit 7 (iice) of iica control register 0 (iicctl0) = 0). when operation is en abled, the iicf register can be read. reset signal generation clea rs this register to 00h.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 592 jun 20, 2011 figure 15-8. format of iica flag register (iicf) <7> stcf condition for clearing (stcf = 0) ? cleared by stt = 1 ? when iice = 0 (operation stop) ? reset condition for setting (stcf = 1) ? generating start condition unsuccessful and stt cleared to 0 when communication reservation is disabled (iicrsv = 1). stcf 0 1 generate start condition start condition generation unsuccessful: clear stt flag stt clear flag iicf symbol <6> iicbsy 5 0 4 0 3 0 2 0 <1> stcen <0> iicrsv address: fff52h after reset: 00h r/w note condition for clearing (iicbsy = 0) ? detection of stop condition ? when iice = 0 (operation stop) ? reset condition for setting (iicbsy = 1) ? detection of start condition ? setting of iice when stcen = 0 iicbsy 0 1 bus release status (communication initial status when stcen = 1) bus communication status (communication initial status when stcen = 0) i 2 c bus status flag condition for clearing (stcen = 0) ? cleared by instruction ? detection of start condition ? reset condition for setting (stcen = 1) ? set by instruction stcen 0 1 after operation is enabled (iice = 1), enable generation of a start condition upon detection of a stop condition. after operation is enabled (iice = 1), enable generation of a start condition without detecting a stop condition. initial start enable trigger condition for clearing (iicrsv = 0) ? cleared by instruction ? reset condition for setting (iicrsv = 1) ? set by instruction iicrsv 0 1 enable communication reservation disable communication reservation communication reservation function disable bit note bits 6 and 7 are read-only. cautions 1. write to stcen only when the operation is stopped (iice = 0). 2. as the bus release status (iicbsy = 0) is recognized regardless of the actual bus status when stcen = 1, when generating the first start condition (stt = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. 3. write to iicrsv only when the operation is stopped (iice = 0). remark stt: bit 1 of iica cont rol register 0 (iicctl0) iice: bit 7 of iica control register 0 (iicctl0)
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 593 jun 20, 2011 (5) iica control register 1 (iicctl1) this register is used to set the operation mode of i 2 c and detect the statuses of the scl0 and sda0 pins. iicctl1 can be set by a 1-bit or 8-bit memory manipulatio n instruction. however, the cld and dad bits are read- only. set the iicctl1 register, except t he wup bit, while operation of i 2 c is disabled (bit 7 (iice) of iica control register 0 (iicctl0) is 0). reset signal generation clea rs this register to 00h. figure 15-9. format of iica cont rol register 1 (iicctl1) (1/2) address: f0231h after reset: 00h r/w note 1 symbol 7 6 <5> <4> <3> <2> 1 0 iicctl1 wup 0 cld dad smc dfc 0 0 wup control of address match wakeup 0 stops operation of address match wakeup function in stop mode. 1 enables operation of address match wakeup function in stop mode. to shift to stop mode when wup = 1, execute the stop instruction at least three clocks after setting (1) the wup bit (see figure 15-22 flow when setting wup = 1 ). clear (0) the wup bit after the address has matched or an extension code has been received. the subsequent communication can be entered by the cl earing (0) wup bit. (the wait must be released and transmit data must be written after the wup bit has been cleared (0).) the interrupt timing when the address has matched or when an extension code has been received, while wup = 1, is identical to the interrupt timing when wup = 0. (a delay of the difference of sampling by the clock will occur.) furthermore, when wup = 1, a stop condition interr upt is not generated even if the spie bit is set to 1. when wup = 0 is set by a source other than an interrupt from serial interface iica, operation as the master device cannot be performed until the subsequent start co ndition or stop condition is detected. do not output a start condition by setting (1) the stt bit, without waiti ng for the detection of the subsequent start condition or stop condition. condition for clearing (w up = 0) condition for setting (wup = 1) ? cleared by instruction (after address match or extension code reception) ? set by instruction (when the msts, exc, and coi bits are ?0?, and the std bit also ?0? (communication not entered)) note 2 notes 1. bits 4 and 5 are read-only. 2. the status of the iica status register (iics) must be che cked and the wup bit must be set during the period shown below. scl0 <1> <2> sda0 a6 a5 a4 a3 a2 a1 a0 the maximum time from reading iics to setting wup is the period from <1> to <2>. check the iics operation status and set wup during this period. r/w
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 594 jun 20, 2011 figure 15-9. format of iica cont rol register 1 (iicctl1) (2/2) cld detection of scl0 pin level (valid only when iice = 1) 0 the scl0 pin was detected at low level. 1 the scl0 pin was detected at high level. condition for clearing (cld = 0) condition for setting (cld = 1) ? when the scl0 pin is at low level ? when iice = 0 (operation stop) ? reset ? when the scl0 pin is at high level dad detection of sda0 pin level (valid only when iice = 1) 0 the sda0 pin was detected at low level. 1 the sda0 pin was detected at high level. condition for clearing (dad = 0) condition for setting (dad = 1) ? when the sda0 pin is at low level ? when iice = 0 (operation stop) ? reset ? when the sda0 pin is at high level smc operation mode switching 0 operates in standard mode. 1 operates in fast mode. dfc digital filter operation control 0 digital filter off. 1 digital filter on. digital filter can be used only in fast mode. in fast mode, the transfer clock does not vary, rega rdless of the dfc bit being set (1) or cleared (0). the digital filter is used for noise elimination in fast mode. remark iice: bit 7 of iica control register 0 (iicctl0)
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 595 jun 20, 2011 (6) iica low-level width setting register (iicwl) this register is used to set the low-level width of the scl0 pin signal that is output by serial interface iica. the iicwl register can be set by an 8- bit memory manipulation instruction. set the iicwl register while operation of i 2 c is disabled (bit 7 (iice) of iica control register 0 (iicctl0) is 0). reset signal generation sets this register to ffh. figure 15-10. format of iica low-level width setting register (iicwl) address: f0232h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 iicwl (7) iica high-level width setting register (iicwh) this register is used to set the high-level width of the scl0 pin signal that is output by serial interface iica. the iicwh register can be set by an 8- bit memory manipulation instruction. set the iicwh register while operation of i 2 c is disabled (bit 7 (iice) of iica control register 0 (iicctl0) is 0). reset signal generation sets this register to ffh. figure 15-11. format of iica high-level width setting register (iicwh) address: f0233h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 iicwh remark for how to set the transfer clock by using the iicwl and iicwh registers, see 15.4.2 setting transfer clock by using iicwl and iicwh registers . (8) port mode register 6 (pm6) this register sets the input/output of port 6 in 1-bit units. when using the p60/scl0 pin as cloc k i/o and the p61/sda0 pin as serial data i/o, clear pm60 and pm61, and the output latches of p60 and p61 to 0. set iice (bit 7 of iica control register 0 (iicctl0)) to 1 before setting the output mode because the p60/scl0 and p61/sda0 pins output a low level (fixed) when iice is 0. pm6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation se ts this register to ffh. figure 15-12. format of port mode register 6 (pm6) pm60 pm61 1 1 1 1 1 1 p6n pin i/o mode selection (n = 0, 1) output mode (output buffer on) input mode (output buffer off) pm6n 0 1 0 1 2 3 4 5 6 7 pm6 address: fff26h after reset: ffh r/w symbol
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 596 jun 20, 2011 15.4 i 2 c bus mode functions 15.4.1 pin configuration the serial clock pin (scl0) and serial data bus pin (sda0) are configured as follows. (1) scl0....... this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. (2) sda0 ...... this pin is used fo r serial data input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial da ta bus line are n-ch open-drain outputs, an external pull-up resistor is required. figure 15-13. pin configuration diagram master device clock output (clock input) data output data input v ss v ss scl0 sda0 v dd v dd (clock output) clock input data output data input v ss v ss slave device scl0 sda0
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 597 jun 20, 2011 15.4.2 setting transfer clock by using iicwl and iicwh registers (1) setting transfer clock on master side transfer clock = f clk iicwl + iicwh + f clk (t r + t f ) at this time, the optimal setting values of iicwl and iicwh are as follows. (the fractional parts of all setting values are rounded up.) ? when the fast mode iicwl = 0.52 transfer clock f clk iicwh = ( 0.48 transfer clock ? t r ? t f ) f clk ? when the standard mode iicwl = 0.47 transfer clock f clk iicwh = ( 0.53 transfer clock ? t r ? t f ) f clk (2) setting iicwl and iicwh on slave side (the fractional parts of all setting values are truncated.) ? when the fast mode iicwl = 1.3 s f clk iicwh = (1.2 s ? t r ? t f ) f clk ? when the standard mode iicwl = 4.7 s f clk iicwh = (5.3 s ? t r ? t f ) f clk caution note the minimum f clk operation frequency when setting the transfer clock. the minimum f clk operation frequency for serial interface ii ca is determined according to the mode. fast mode: f clk = 3.5 mhz (min.) standard mode: f clk = 1 mhz (min.) remarks 1. calculate the rise time (t r ) and fall time (t f ) of the sda0 and scl0 signals separately, because they differ depending on the pull-up resistance and wire load. 2. iicwl: iica low-level width setting register iicwh: iica high-level width setting register t f : sda0 and scl0 signal falling times t r : sda0 and scl0 signal rising times f clk : cpu/peripheral hardware clock frequency
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 598 jun 20, 2011 15.5 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. figure 15-14 shows the transfer timing for the ?start conditi on?, ?address?, ?data?, and ?stop condition? output via the i 2 c bus?s serial data bus. figure 15-14. i 2 c bus serial data transfer timing scl0 sda0 start condition address r/w ack data 1-7 8 9 1-8 ack data ack stop condition 9 1-8 9 the master device generates the start c ondition, slave address, and stop condition. the acknowledge (ack) can be generated by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scl0) is continuously output by the master device. howeve r, in the slave device, the scl0?s low level period can be extended and a wait can be inserted. 15.5.1 start conditions a start condition is met when the scl0 pin is at high level and the sda0 pin changes from high level to low level. the start conditions for the scl0 pin and sda0 pin are signals that the master device generates to the slave device when starting a serial transfer. when the device is us ed as a slave, start conditions can be detected. figure 15-15. start conditions scl0 sda0 h a start condition is output when bit 1 (stt) of iica control re gister 0 (iicctl0) is set (1) after a stop condition has been detected (spd: bit 0 of the iica status register (iics) = 1). when a start condition is detected, bit 1 (std) of iics is set (1).
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 599 jun 20, 2011 15.5.2 addresses the address is defined by the 7 bits of data that follow the start condition. an address is a 7-bit data segment that is output in order to select one of t he slave devices that are connected to the master device via the bus lines. theref ore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware t hat detects the start condition and che cks whether or not the 7-bit address data matches the data values stored in the slave address regist er (sva). if the address data matches the sva values, the slave device is selected and communicates with the master device unt il the master device generat es a start condition or stop condition. figure 15-16. address scl0 sda0 intiica 123456789 a6 a5 a4 a3 a2 a1 a0 r/w address note note intiica is not issued if data other than a local address or extension code is received during slave device operation. addresses are output when a total of 8 bi ts consisting of the slave address and the transfer direction described in 15.5.3 transfer di rection specification are written to the iica shift register (iica). the received addresses are written to iica. the slave address is assigned to the higher 7 bits of iica. 15.5.3 transfer di rection specification in addition to the 7-bit address data, the master device s ends 1 bit that specifies t he transfer direction. when this transfer direction spec ification bit has a value of ?0?, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of ?1?, it indicate s that the master device is receiving data from a slave device. figure 15-17. transfer direction specification scl0 sda0 intiica 123456789 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification note note intiica is not issued if data other than a local address or extension code is received during slave device operation.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 600 jun 20, 2011 15.5.4 acknowledge (ack) ack is used to check the status of serial data at the transmission and reception sides. the reception side returns ack each time it has received 8-bit data. the transmission side usually receives ack after transmitting 8- bit data. when ack is returned from the reception side, it is assumed that reception has been correctly performed a nd processing is continued. whether ack has been detected can be checked by using bit 2 (ackd) of the iica status register (iics). when the master receives the last data item, it does not return ack and instead ge nerates a stop condition. if a slave does not return ack after receiving data, the master outputs a stop condition or restart condit ion and stops transmission. if ack is not returned, the possible causes are as follows. <1> reception was not performed normally. <2> the final data item was received. <3> the reception side specified by the address does not exist. to generate ack, the reception side makes the sda0 line low at the ninth clock (indicating normal reception). automatic generation of ack is enabled by setting bit 2 (acke) of iica control register 0 (ii cctl0) to 1. bit 3 (trc) of the iics register is set by the data of the eighth bit that follows 7-bit address information. usually, set acke to 1 for reception (trc = 0). if a slave can receive no more data during reception (trc = 0) or does not require the next data item, then the slave must inform the master, by clearing acke to 0, that it will not receive any more data. when the master does not require the next data item during reception (trc = 0), it must clear acke to 0 so that ack is not generated. in this way, the master informs a slave at the transmission side that it does not require any more data (transmission will be stopped). figure 15-18. ack scl0 sda0 123456789 a6 a5 a4 a3 a2 a1 a0 r/w ack when the local address is received, ac k is automatically generated, regardle ss of the value of acke. when an address other than that of t he local address is received, ack is not generated (nack). when an extension code is received, ack is generated if acke is set to 1 in advance. how ack is generated when data is received differs as follows depending on the setting of the wait timing. ? when 8-clock wait state is selected (b it 3 (wtim) of iicctl0 register = 0): by setting acke to 1 before releasing the wait state, ack is generated at the falling edge of the eighth clock of the scl0 pin. ? when 9-clock wait state is selected (b it 3 (wtim) of iicctl0 register = 1): ack is generated by setting acke to 1 in advance.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 601 jun 20, 2011 15.5.5 stop condition when the scl0 pin is at high level, changing the sda0 pin from low level to high level generates a stop condition. a stop condition is a signal that t he master device generates to the slave device when serial transfer has been completed. when the device is used as a slave, stop conditions can be detected. figure 15-19. stop condition scl0 sda0 h a stop condition is generated when bit 0 (spt ) of iica control register 0 (iicctl0) is set to 1. when the stop condition is detected, bit 0 (spd) of t he iica status register (iics) is set to 1 and intiica is generated when bit 4 (spie) of iicctl0 is set to 1.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 602 jun 20, 2011 15.5.6 wait the wait is used to notify the communicati on partner that a device (mast er or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0 pin to low level notifie s the communication partner of the wait state. when wait state has been canceled for both the master and slave devices, the next data transfer can begin. figure 15-20. wait (1/2) (1) when master device has a nine-clock wait and slave device has an eight-clock wait (master transmits, slave receives, and acke = 1) master iica scl0 slave iica scl0 acke transfer lines scl0 sda0 6789 123 master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock iica data write (cancel wait) wait after output of eighth clock wait from slave wait from master ffh is written to iica or wrel is set to 1 678 9 123 d2 d1 d0 d7 d6 d5 ack h
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 603 jun 20, 2011 figure 15-20. wait (2/2) (2) when master and slave devices both have a nine-clock wait (master transmits, slave receives, and acke = 1) master iica scl0 slave iica scl0 acke transfer lines scl0 sda0 h 6789 1 23 master and slave both wait after output of ninth clock wait from master and slave wait from slave iica data write (cancel wait) ffh is written to iica or wrel is set to 1 6789 123 d2 d1 d0 ack d7 d6 d5 generate according to previously set acke value remark acke: bit 2 of iica control register 0 (iicctl0) wrel: bit 5 of iica control register 0 (iicctl0) a wait may be automatically generated depending on the setti ng of bit 3 (wtim) of iica control register 0 (iicctl0). normally, the receiving side cancels the wait state when bit 5 (wrel) of the iicctl0 register is set to 1 or when ffh is written to the iica shift register (iica), and the transmitting side cancels the wait state w hen data is written to the iica register. ? by setting bit 1 (stt) of iicctl0 to 1 ? by setting bit 0 (spt) of iicctl0 to 1
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 604 jun 20, 2011 15.5.7 canceling wait the i 2 c usually cancels a wait stat e by the following processing. ? writing data to iica shift register (iica) ? setting bit 5 (wrel) of iica control register 0 (iicctl0) (canceling wait) ? setting bit 1 (stt) of iicctl0 regi ster (generating start condition) note ? setting bit 0 (spt) of iicctl0 regi ster (generating stop condition) note note master only when the above wait canceling processing is executed, the i 2 c cancels the wait state and communication is resumed. to cancel a wait state and transmit data (incl uding addresses), write the data to iica. to receive data after canceling a wait state, or to comple te data transmission, set bit 5 (wrel) of iica control register 0 (iicctl0) to 1. to generate a restart condition after canceling a wait state, set bit 1 (stt) of iicctl0 to 1. to generate a stop condition after canceling a wa it state, set bit 0 ( spt) of iicctl0 to 1. execute the canceling processing only once for one wait state. if, for example, data is written to iica after canceling a wait state by setting wrel to 1, an incorrect value may be output to sda0 because the timing for changing the sd a0 line conflicts with the timing for writing iica. in addition to the above, communication is stopped if iice is cleared to 0 when communication has been aborted, so that the wait stat e can be canceled. if the i 2 c bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (lrel) of iicctl0, so that the wait st ate can be canceled. caution if a processing to cancel a wait state executed when wup (bit 7 of iica control register 1 (iicctl1)) = 1, the wait state will not be canceled.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 605 jun 20, 2011 15.5.8 interrupt request (intiica) generation timing and wait control the setting of bit 3 (wtim) of iica control register 0 (iic ctl0) determines the timing by which intiica is generated and the corresponding wait control, as shown in table 15-2. table 15-2. intiica generation timing and wait control during slave device operation during master device operation wtim address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiica signal and wait period o ccurs at the falling edge of the ninth clock only when there is a match with the address set to the slave address register (sva). at this point, ack is generated regardless of the value set to iicctl0?s bit 2 (acke). for a slave device that has received an extension code, intiica occu rs at the falling edge of the eighth clock. however, if the address does not match after rest art, intiica is generated at the falling edge of the 9th clock, but wait does not occur. 2. if the received address does not match the contents of the slave address register (sva) and extension code is not received, neither intiica nor a wait occurs. remark the numbers in the table indicate t he number of the serial clock?s clock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) during address transmission/reception ? slave device operation: interrupt and wait timi ng are determined depending on the conditions described in notes 1 and 2 above, regardless of the wtim bit. ? master device operation: interrupt and wait timing oc cur at the falling edge of the ninth clock regardless of the wtim bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtim bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtim bit. (4) wait cancellation method the four wait cancellation methods are as follows. ? writing data to iica shift register (iica) ? setting bit 5 (wrel) of iica control register 0 (iicctl0) (canceling wait) ? setting bit 1 (stt) of iicctl0 regi ster (generating start condition) note ? setting bit 0 (spt) of iicctl0 regi ster (generating stop condition) note note master only. when an 8-clock wait has been selected (wtim = 0) , the presence/absence of ack generation must be determined prior to wait cancellation. (5) stop condition detection intiica is generated when a stop condit ion is detected (only when spie = 1).
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 606 jun 20, 2011 15.5.9 address match detection method in i 2 c bus mode, the master device can se lect a particular slave device by trans mitting the corresponding slave address. address match can be detected automatically by hardware. an interrupt request (intiica) occurs when the address set to the slave address register (sva) matches the slave address sent by the master device, or when an extension code has been received. 15.5.10 error detection in i 2 c bus mode, the status of t he serial data bus (sda0) during data transmissi on is captured by the iica shift register (iica) of the transmitting device, so the iica data prior to transmission can be compared with the transmitted iica data to enable detection of transmission errors. a transmission erro r is judged as having occurred when the compared data values do not match. 15.5.11 extension code (1) when the higher 4 bits of the receive address are eit her ?0000? or ?1111?, the extension code reception flag (exc) is set to 1 for extension code reception and an interrupt request (intiica) is issued at the falling edge of the eighth clock. the local address stored in the slav e address register (sva) is not affected. (2) the settings below are specified if 11110xx0 is transferre d from the master by using a 10-bit address transfer when the sva register is set to 11110xx0. note that intiica occurs at the falling edge of the eighth clock. ? higher four bits of data match: exc = 1 ? seven bits of data match: coi = 1 remark exc: bit 5 of iica status register (iics) coi: bit 4 of iica status register (iics) (3) since the processing after the interrupt request occurs di ffers according to the data that follows the extension code, such processing is performed by software. if the extension code is received while a slave device is operating, then the slave device is participating in communication even if its address does not match. for example, after the extension code is received, if you do not wish to operate the target device as a slave device, set bit 6 (lrel) of the iica control re gister 0 (iicctl0) to 1 to set the standby mode for the next communication operation. table 15-3. bit definitions of main extension code slave address r/w bit description 0 0 0 0 0 0 0 0 general call address 1 1 1 1 0 x x 0 10-bit slave address sp ecification (for address authentication) 1 1 1 1 0 x x 1 10-bit slave address specification (for read command issuance after address match) remark for extension codes other than the above, refer to the i 2 c-bus specification published by nxp.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 607 jun 20, 2011 15.5.12 arbitration when several master devices simultaneous ly generate a start condition (when stt is set to 1 before std is set to 1), communication among the master devices is performed as the num ber of clocks are adjusted until the data differs. this kind of operation is called arbitration. when one of the master devices loses in arbitration, an arbitration loss flag (ald) in the iica status register (iics) is set (1) via the timing by which the arbitration loss occurred, and the scl0 and sda0 lines are both set to high impedance, which releases the bus. the arbitration loss is detected based on th e timing of the next interrupt request (t he eighth or ninth clock, when a stop condition is detected, etc.) and the ald = 1 setting that has been made by software. for details of interrupt request timing, see 15.5.8 interrupt request (intiica) generation timing and wait control . remark std: bit 1 of iica status register (iics) stt: bit 1 of iica control register 0 (iicctl0) figure 15-21. arbitration timing example scl0 sda0 scl0 sda0 scl0 sda0 hi-z hi-z master 1 loses arbitration master 1 master 2 transfer lines
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 608 jun 20, 2011 table 15-4. status during arbitration and interrupt request generation timing status during arbitration interrupt request generation timing during address transmission read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack transfer period after data transmission when restart condition is detected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected during data transf er when stop condition is generated (when spie = 1) note 2 when data is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to generate a restart condition when stop condition is generated (when spie = 1) note 2 when data is at low level while attempting to generate a stop condition when scl0 is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when wtim (bit 3 of iica control r egister 0 (iicctl0)) = 1, an interrupt request occurs at the falling edge of the ninth clock. when wtim = 0 and the extension code ?s slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. when there is a chance that ar bitration will occur, set spie = 1 for master device operation. remark spie: bit 4 of iica control register 0 (iicctl0)
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 609 jun 20, 2011 15.5.13 wakeup function the i 2 c bus slave function is a function t hat generates an interrupt request signa l (intiica) when a local address and extension code have been received. this function makes processing more efficient by prev enting unnecessary intiica signal from occurring when addresses do not match. when a start condition is detected, wa keup standby mode is set. this wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbi tration loss may change the master device (which has generated a start condition) to a slave device. however, when a stop condition is detected, bit 4 (spie) of iica control register 0 (iicctl0) is set regardless of the wakeup function, and this determines whether interrupt requests are enabled or disabled. to use the wakeup function in the stop mode, set wup to 1. addresses can be received regardless of the operation clock. an interrupt request signal (intiica) is also generated when a local addres s and extension code have been received. operation returns to normal operation by using an in struction to clear (0) the wup bit after this interrupt has been generated. figure 15-22 shows the flow for setting wup = 1 and figure 15-23 shows the flow for setting wup = 0 upon an address match. figure 15-22. flow when setting wup = 1 waits for 3 clocks. yes no start wup = 1 wait stop instruction execution msts = std = exc = coi =0?
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 610 jun 20, 2011 figure 15-23. flow when setting wup = 0 upon addr ess match (including extension code reception) waits for 5 clocks. executes processing corresponding to the operation to be executed after checking the operation state of serial interface iica. stop mode state no yes wup = 0 wait reading iics intiica = 1?
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 611 jun 20, 2011 use the following flows to perform the processing to re lease the stop mode other t han by an interrupt request (intiica) generated from serial interface iica. ? master device operation: flow shown in figure 15-24 ? slave device operation: same as the flow in figure 15-23 figure 15-24. when operating as master device after releasing stop mode other than by intiica executes processing corresponding to the operation to be executed after checking the operation state of serial interface iica. no yes releases stop mode by an interrupt other than intiica. generates a stop condition or selects as a slave device. start wup = 1 spie = 1 releasing stop mode stop instruction wup = 0 reading iics intiica = 1? stop mode state waits for 5 clocks. wait
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 612 jun 20, 2011 15.5.14 communication reservation (1) when communication reservation func tion is enabled (bit 0 (iicrsv) of iica flag register (iicf) = 0) to start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. there are two modes under which the bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released by setting bit 6 (lrel) of iica control r egister 0 (iicctl0) to 1 and saving communication). if bit 1 (stt) of iicctl0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition is automatically generated and wait state is set. if an address is written to the iica shift register (iica) after bit 4 (spie) of iicctl0 was set to 1, and it was detected by generation of an interrupt request signal (intiica) that the bus was released (detection of the stop condition), then the device automatically starts communicat ion as the master. data written to iica before the stop condition is detected is invalid. when stt has been set to 1, the operation mode (as start condition or as communication reservation) is determined according to the bus status. ? if the bus has been released ........................................ a start c ondition is generated ? if the bus has not been released (stand by mode)......... communication reservation check whether the communication reservation operates or not by using msts (bit 7 of the iica status register (iics)) after stt is set to 1 and the wait time elapses. use software to secure the wait time calculated by the following expression. wait time from setting stt = 1 to checking the msts flag: (iicwl setting value + iicwh setting value + 4 clocks) / f clk + t f 2 remark iicwl: iica low-level width setting register iicwh: iica high-level width setting register t f : sda0 and scl0 signal falling times f clk : cpu/peripheral hardware clock frequency
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 613 jun 20, 2011 figure 15-25 shows the communication reservation timing. figure 15-25. communication reservation timing 2 1 3456 2 1 3456 789 scl0 sda0 program processing hardware processing write to iica set spd and intiica stt = 1 communi- cation reservation set std generate by master device with bus mastership remark iica: iica shift register stt: bit 1 of iica control register 0 (iicctl0) std: bit 1 of iica status register (iics) spd: bit 0 of iica status register (iics) communication reservations are accepted via the timing sh own in figure 15-26. after bit 1 (std) of the iica status register (iics) is set to 1, a communication rese rvation can be made by setting bit 1 (stt) of iica control register 0 (iicctl0) to 1 befor e a stop condition is detected. figure 15-26. timing for accep ting communication reservations scl0 sda0 std spd standby mode (communication can be reserved by setting stt to 1 during this period.) figure 15-27 shows the communication reservation protocol.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 614 jun 20, 2011 figure 15-27. communication reservation protocol di set1 stt define communication reservation wait msts = 0? (communication reservation) note 2 yes no (generate start condition) cancel communication reservation mov iica, # h ei sets stt flag (communication reservation) defines that communication reservation is in effect (defines and sets user flag to any part of ram) secures wait time note 1 by software. confirmation of communication reservation clear user flag iica write operation notes 1. the wait time is calculated as follows. (iicwl setting value + iicwh setting value + 4 clocks) / f clk + t f 2 2. the communication reservation operation executes a write to the iica shift register (iica) when a stop condition interrupt request occurs. remark stt: bit 1 of iica control register 0 (iicctl0) msts: bit 7 of iica status register (iics) iica: iica shift register iicwl: iica low-level width setting register iicwh: iica high-level width setting register t f : sda0 and scl0 signal falling times f clk : cpu/peripheral hardware clock frequency
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 615 jun 20, 2011 (2) when communication reservation function is disabled (bit 0 (iicrsv) of iica flag register (iicf) = 1) when bit 1 (stt) of iica control regi ster 0 (iicctl0) is set to 1 when t he bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. the following two statuses are included in the st atus where bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released by setting bit 6 (lrel) of iicctl0 to 1 and saving communication) to confirm whether the start condition was generated or re quest was rejected, check stcf (bit 7 of iicf). it takes up to 5 clocks until stcf is set to 1 after setting stt = 1. therefore, secure the time by software.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 616 jun 20, 2011 15.5.15 cautions (1) when stcen = 0 immediately after i 2 c operation is enabled (iice = 1), the bus comm unication status (iicbsy = 1) is recognized regardless of the actual bus status. when changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. when using multiple masters, it is not possible to per form master device communication when the bus has not been released (when a stop condition has not been detected). use the following sequence for generating a stop condition. <1> set iica control register 1 (iicctl1). <2> set bit 7 (iice) of iica cont rol register 0 (iicctl0) to 1. <3> set bit 0 (spt) of iicctl0 to 1. (2) when stcen = 1 immediately after i 2 c operation is enabled (iice = 1), the bus re leased status (iicbsy = 0) is recognized regardless of the actual bus status. to generate the first start condition (stt = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) if other i 2 c communications are already in progress if i 2 c operation is enabled and the device part icipates in communication already in progress when the sda0 pin is low and the scl0 pin is high, the macro of i 2 c recognizes that the sda0 pin has gone low (detects a start condition). if the value on the bus at this time can be re cognized as an extension code, ack is returned, but this interferes with other i 2 c communications. to avoid this, start i 2 c in the following sequence. <1> clear bit 4 (spie) of iicctl0 to 0 to disable generati on of an interrupt request signal (intiica) when the stop condition is detected. <2> set bit 7 (iice) of iicctl0 to 1 to enable the operation of i 2 c. <3> wait for detection of the start condition. <4> set bit 6 (lrel) of iicctl0 to 1 before ack is retu rned (4 to 80 clocks after setting iice to 1), to forcibly disable detection. (4) setting stt and spt (bits 1 and 0 of iicctl0) again afte r they are set and before they are cleared to 0 is prohibited. (5) when transmission is reserved, set spie (bit 4 of iictl0) to 1 so that an interrupt request is generated when the stop condition is detected. transfer is started when communication data is wr itten to iica after the interrupt request is generated. unless the interrupt is generated when the st op condition is detected, the device stops in the wait state because the interrupt request is not generated when communication is start ed. however, it is not necessary to set spie to 1 when msts (bit 7 of iics) is detected by software.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 617 jun 20, 2011 15.5.16 communication operations the following shows three operatio n procedures with the flowchart. (1) master operation in single master system the flowchart when using the 78k0r/lx3 microcontrollers as the master in a single master system is shown below. this flowchart is broadly divided into the initial settings and communication processing. execute the initial settings at startup. if communication wit h the slave is required, prepare the communication and then execute communication processing. (2) master operation in multimaster system in the i 2 c bus multimaster system, whether the bus is released or used cannot be judged by the i 2 c bus specifications when the bus takes part in a communicati on. here, when data and clock are at a high level for a certain period (1 frame), the 78k0r/lx3 microcontrollers take part in a communication with bus released state. this flowchart is broadly divided into the initial settings , communication waiting, and communication processing. the processing when the 78k0r/lx3 microcontrollers loose in arbitration and are specifi ed as the slave is omitted here, and only the processing as the ma ster is shown. execute the initial settings at startup to take part in a communication. then, wait for the communication request as t he master or wait for the s pecification as the slave. the actual communication is performed in the communication processing, and it supports the transmission/reception with the slave and the arbitration with other masters. (3) slave operation an example of when the 78k0r/lx3 microcontrollers are used as the i 2 c bus slave is shown below. when used as the slave, operation is star ted by an interrupt. execute the initial settings at startup, then wait for the intiica interrupt occurrence (communication waiting). when an intiica interrupt occurs, the communication status is judged and its result is passed as a flag over to the main processing. by checking the flags, necessary communication processing is performed.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 618 jun 20, 2011 (1) master operation in single-master system figure 15-28. master operation in single-master system spt = 1 spt = 1 wrel = 1 start end acke = 0 wtim = wrel = 1 no no yes no no no yes yes yes yes stcen = 1? acke = 1 wtim = 0 trc = 1? ackd = 1? ackd = 1? no yes no yes yes no yes no yes no yes no yes no stt = 1 iicwl, iicwh xxh iicf 0xh setting stcen, iicrsv = 0 iicctl0 1xx111xxb iice = 1 iicctl0 0xx111xxb acke = wtim = spie = 1 setting port initializing i 2 c bus note sva xxh writing iica writing iica reading iica intiica interrupt occurs? end of transfer? end of transfer? restart? setting of the port used alternatively as the pin to be used. first, set the port to input mode and the output latch to 0 (see 15.3 (8) port mode register 6 (pm6) ). setting port set the port from input mode to output mode and enable the output of the i 2 c bus (see 15.3 (8) port mode register 6 (pm6) ). sets a transfer clock. sets a local address. sets a start condition. prepares for starting communication (generates a start condition). starts communication (specifies an address and transfer direction). waits for detection of acknowledge. waits for data transmission. starts transmission. communication processing initial setting starts reception. waits for data reception. intiica interrupt occurs? waits for detection of acknowledge. prepares for starting communication (generates a stop condition). waits for detection of the stop condition. intiica interrupt occurs? intiica interrupt occurs? intiica interrupt occurs? note release (scl0 and sda0 pins = high level) the i 2 c bus in conformance with the specifications of the product that is communicating. if eeprom is outputting a low le vel to the sda0 pin, for example, set the scl0 pin in the output port mode, and output a clock pu lse from the output port until the sda0 pin is constantly at high level. remark conform to the specifications of the product that is communicating, with respect to the transmission and reception formats.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 619 jun 20, 2011 (2) master operation in multi-master system figure 15-29. master operation in multi-master system (1/3) iicwl, iicwh xxh iicf 0xh setting stcen and iicrsv setting port spt = 1 sva xxh spie = 1 start slave operation slave operation releases the bus for a specific period. bus status is being checked. yes checking bus status note master operation starts? enables reserving communication. disables reserving communication. spd = 1? stcen = 1? iicrsv = 0? a selects a transfer clock. sets a local address. sets a start condition. (communication start request) (no communication start request) ? waiting to be specified as a slave by other master ? waiting for a communication start request (depends on user program) prepares for starting communication (generates a stop condition). waits for detection of the stop condition. no yes yes no intiica interrupt occurs? intiica interrupt occurs? yes no yes no spd = 1? yes no slave operation no intiica interrupt occurs? yes no 1 b spie = 0 yes no waits for a communication request. waits for a communication initial setting iicctl0 1xx111xxb iice = 1 iicctl0 0xx111xxb acke = wtim = spie = 1 setting of the port used alternatively as the pin to be used. first, set the port to input mode and the output latch to 0 (see 15.3 (8) port mode register 6 (pm6) ). setting port set the port from input mode to output mode and enable the output of the i 2 c bus (see 15.3 (8) port mode register 6 (pm6) ). note confirm that the bus is released (cld bit = 1, dad bit = 1) for a specific period (for example, for a period of one frame). if the sda0 pin is constantly at low level, decide whether to release the i 2 c bus (scl0 and sda0 pins = high level) in conformance with the specificat ions of the product that is communicating.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 620 jun 20, 2011 figure 15-29. master operation in multi-master system (2/3) stt = 1 wait slave operation yes msts = 1? exc = 1 or coi =1? prepares for starting communication (generates a start condition). secure wait time note by software. waits for bus release (communication being reserved). wait state after stop condition was detected and start condition was generated by the communication reservation function. no intiica interrupt occurs? yes yes no no a c stt = 1 wait note slave operation yes iicbsy = 0? exc = 1 or coi =1? prepares for starting communication (generates a start condition). disables reserving communication. enables reserving communication. waits for bus release detects a stop condition. no no intiica interrupt occurs? yes yes no yes stcf = 0? no b d c d communication processing communication processing note the wait time is calculated as follows. (iicwl setting value + iicwh setting value + 4 clocks) / f clk + t f 2 remark iicwl: iica low-level width setting register iicwh: iica high-level wid th setting register t f : sda0 and scl0 signal falling times f clk : cpu/peripheral hardware clock frequency
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 621 jun 20, 2011 figure 15-29. master operation in multi-master system (3/3) writing iica wtim = 1 wrel = 1 reading iica acke = 1 wtim = 0 wtim = wrel = 1 acke = 0 writing iica yes trc = 1? restart? msts = 1? starts communication (specifies an address and transfer direction). starts transmission. no yes waits for data reception. starts reception. yes no intiica i nterrupt occurs? yes no transfer end? waits for detection of ack. yes no intiica i nterrupt occurs? waits for data transmission. does not participate in communication. yes no intiica i nterrupt occurs? no yes ackd = 1? no yes no c 2 yes msts = 1? no yes transfer end? no yes ackd = 1? no 2 yes msts = 1? no 2 waits for detection of ack. yes no intiica i nterrupt occurs? yes msts = 1? no c 2 yes exc = 1 or coi = 1? no 1 2 spt = 1 stt = 1 slave operation end communication processing communication processing remarks 1. conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. 2. to use the device as a master in a multi-master system, read the ms ts bit each time interrupt intiica has occurred to check the arbitration result. 3. to use the device as a slave in a multi-master system, check the status by using the iics and iicf registers each time inte rrupt intiica has occurred, and determine the processing to be performed next.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 622 jun 20, 2011 (3) slave operation the processing procedure of the slave operation is as follows. basically, the slave operation is event-driven. therefore, processing by the intiica interrupt (processing that must substantially change the operation st atus such as detection of a stop c ondition during communication) is necessary. in the following explanation, it is a ssumed that the extension c ode is not supported for data communication. it is also assumed that the intiica interrupt servicing only per forms status transition proces sing, and that actual data communication is performed by the main processing. iica interrupt servicing main processing intiica flag setting data setting therefore, data communication processing is performed by preparing the following three flags and passing them to the main processing instead of intiica. <1> communication mode flag this flag indicates the following two communication statuses. ? clear mode: status in which data communication is not performed ? communication mode: status in which data commun ication is performed (from valid address detection to stop condition detection, no detection of ack from master, address mismatch) <2> ready flag this flag indicates that data communication is enabled. its function is the same as the intiica interrupt for ordinary data communication. this flag is set by interrupt servicing and cleared by the main processing. clear this flag by interrupt servicing when communicati on is started. however, the ready flag is not set by interrupt servicing when the first data is transmitted. therefore, the first data is transmitted without the flag being cleared (an address match is interpreted as a request for the next data). <3> communication direction flag this flag indicates the direction of communication. its value is the same as trc.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 623 jun 20, 2011 the main processing of the slave operation is explained next. start serial interface iica and wait until communication is enabled. when communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt. he re, check the status by using the flags). the transmission operation is repeated unt il the master no longer returns ack. if ack is not returned from the master, communication is completed. for reception, the necessary amount of data is received. when communication is completed, ack is not returned as the next data. after that, the master generates a stop condition or restart condition. exit from the communication status occurs in this way. figure 15-30. slave operation flowchart (1) yes yes yes yes yes yes yes no no no no no no wrel = 1 ackd = 1? no yes no yes no start communication mode flag = 1? communication mode flag = 1? communication direction flag = 1? ready flag = 1? communication direction flag = 0? reading iica clearing ready flag clearing ready flag communication direction flag = 1? clearing communication mode flag wrel = 1 writing iica sva xxh sets a local address. iicwl, iicwh xxh selects a transfer clock. iicf 0xh setting iicrsv sets a start condition. starts transmission. starts reception. communication mode flag = 1? ready flag = 1? setting port setting port communication processing initial setting setting of the port used alternatively as the pin to be used. first, set the port to input mode and the output latch to 0 (see 15.3 (8) port mode register 6 (pm6) ). set the port from input mode to output mode and enable the output of the i 2 c bus (see 15.3 (8) port mode register 6 (pm6) ). iicctl0 0xx011xxb acke = wtim = 1, spie = 0 iicctl0 1xx011xxb iice = 1 remark conform to the specifications of the product t hat is in communication, regarding the transmission and reception formats.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 624 jun 20, 2011 an example of the processing procedure of the slave wit h the intiica interrupt is explained below (processing is performed assuming that no extension code is used). th e intiica interrupt checks the status, and the following operations are performed. <1> communication is stopped if the stop condition is issued. <2> if the start condition is issued, the address is che cked and communication is completed if the address does not match. if the address matches, the communication mo de is set, wait is cancelled, and processing returns from the interrupt (the ready flag is cleared). <3> for data transmit/receive, only the ready flag is set. processing returns from the interrupt with the i 2 c bus remaining in the wait state. remark <1> to <3> above correspond to <1> to <3> in figure 15-31 slave operation flowchart (2). figure 15-31. slave operation flowchart (2) yes yes yes no no no intiica generated set ready flag interrupt servicing completed spd = 1? std = 1? coi = 1? communication direction flag trc set communication mode flag clear ready flag clear c ommunication direction flag, ready flag, and communication mode flag <1> <2> <3>
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 625 jun 20, 2011 15.5.17 timing of i 2 c interrupt request (intiica) occurrence the timing of transmitting or receiving data and generation of interrupt request signal int iica, and the value of the iics register when the intiica signal is generated are shown below. remark st: start condition ad6 to ad0: address r/w: transfer direction specification ack: acknowledge d7 to d0: data sp: stop condition
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 626 jun 20, 2011 (1) master device operation (a) start ~ address ~ data ~ data ~ stop (transmission/reception) (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt = 1 3 4 5 2 1 1: iics = 1000110b 2: iics = 1000000b 3: iics = 1000000b (sets wtim to 1) note 4: iics = 100000b (sets spt to 1) note 5: iics = 00000001b note to generate a stop condition, set wtim to 1 and ch ange the timing for generating the intiica interrupt request signal. remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt = 1 3 4 2 1 1: iics = 1000110b 2: iics = 1000100b 3: iics = 100000b (sets spt to 1) 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 627 jun 20, 2011 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack stt = 1 spt = 1 3 4 7 2 1 5 6 1: iics = 1000110b 2: iics = 1000000b (sets wtim to 1) note 1 3: iics = 100000b (clears wtim to 0 note 2 , sets stt to 1) 4: iics = 1000110b 5: iics = 1000000b (sets wtim to 1) note 3 6: iics = 100000b (sets spt to 1) 7: iics = 00000001b notes 1. to generate a start condition, set wtim to 1 and change the timing for generating the intiica interrupt request signal. 2. clear wtim to 0 to restore the original setting. 3. to generate a stop condition, set wtim to 1 and change the timing for generating the intiica interrupt request signal. remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack stt = 1 spt = 1 3 4 5 2 1 1: iics = 1000110b 2: iics = 100000b (sets stt to 1) 3: iics = 1000110b 4: iics = 100000b (sets spt to 1) 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 628 jun 20, 2011 (c) start ~ code ~ data ~ data ~ stop (extension code transmission) (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt = 1 3 4 5 2 1 1: iics = 1010110b 2: iics = 1010000b 3: iics = 1010000b (sets wtim to 1) note 4: iics = 101000b (sets spt to 1) 5: iics = 00000001b note to generate a stop condition, set wtim to 1 and ch ange the timing for generating the intiica interrupt request signal. remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp spt = 1 3 4 2 1 1: iics = 1010110b 2: iics = 1010100b 3: iics = 101000b (sets spt to 1) 4: iics = 00001001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 629 jun 20, 2011 (2) slave device operation (slave address data reception) (a) start ~ address ~ data ~ data ~ stop (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics = 0001110b 2: iics = 0001000b 3: iics = 0001000b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics = 0001110b 2: iics = 0001100b 3: iics = 000100b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 630 jun 20, 2011 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim = 0 (after restart, matches with sva) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics = 0001110b 2: iics = 0001000b 3: iics = 0001110b 4: iics = 0001000b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 (after restart, matches with sva) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics = 0001110b 2: iics = 000100b 3: iics = 0001110b 4: iics = 000100b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 631 jun 20, 2011 (c) start ~ address ~ data ~ start ~ code ~ data ~ stop (i) when wtim = 0 (after restart, do es not match address (= extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics = 0001110b 2: iics = 0001000b 3: iics = 0010010b 4: iics = 0010000b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 (after restart, do es not match address (= extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 5 6 2 1 4 1: iics = 0001110b 2: iics = 000100b 3: iics = 0010010b 4: iics = 0010110b 5: iics = 001000b 6: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 632 jun 20, 2011 (d) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim = 0 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics = 0001110b 2: iics = 0001000b 3: iics = 00000110b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics = 0001110b 2: iics = 000100b 3: iics = 00000110b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 633 jun 20, 2011 (3) slave device operation (w hen receiving extension code) the device is always participating in communication when it receives an extension code. (a) start ~ code ~ data ~ data ~ stop (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics = 0010010b 2: iics = 0010000b 3: iics = 0010000b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 5 2 1 1: iics = 0010010b 2: iics = 0010110b 3: iics = 0010100b 4: iics = 001000b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 634 jun 20, 2011 (b) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim = 0 (after restart, matches sva) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics = 0010010b 2: iics = 0010000b 3: iics = 0001110b 4: iics = 0001000b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 (after restart, matches sva) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 6 2 1 5 1: iics = 0010010b 2: iics = 0010110b 3: iics = 001000b 4: iics = 0001110b 5: iics = 000100b 6: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 635 jun 20, 2011 (c) start ~ code ~ data ~ start ~ code ~ data ~ stop (i) when wtim = 0 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics = 0010010b 2: iics = 0010000b 3: iics = 0010010b 4: iics = 0010000b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 7 2 1 5 6 1: iics = 0010010b 2: iics = 0010110b 3: iics = 001000b 4: iics = 0010010b 5: iics = 0010110b 6: iics = 001000b 7: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 636 jun 20, 2011 (d) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim = 0 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 2 1 1: iics = 00100010b 2: iics = 00100000b 3: iics = 00000110b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 (after restart, does not match address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ad6 to ad0 ack ack sp st r/w d7 to d0 ack 3 4 5 2 1 1: iics = 00100010b 2: iics = 00100110b 3: iics = 0010000b 4: iics = 00000110b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 637 jun 20, 2011 (4) operation without communication (a) start ~ code ~ data ~ data ~ stop st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 1 1: iics = 00000001b remark : generated only when spie = 1 (5) arbitration loss operation (opera tion as slave after arbitration loss) when the device is used as a master in a multi-master system, read the msts bit each time interrupt request signal intiica has occurred to check the arbitration result. (a) when arbitration loss occurs durin g transmission of slave address data (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics = 0101110b 2: iics = 0001000b 3: iics = 0001000b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 638 jun 20, 2011 (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics = 0101110b 2: iics = 0001100b 3: iics = 000100b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (b) when arbitration loss occurs dur ing transmission of extension code (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 2 1 1: iics = 0110010b 2: iics = 0010000b 3: iics = 0010000b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 639 jun 20, 2011 (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 4 5 2 1 1: iics = 0110010b 2: iics = 0010110b 3: iics = 0010100b 4: iics = 001000b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (6) operation when arbitration loss occurs (no communication after arbitration loss) when the device is used as a master in a multi-master system, read the msts bit each time interrupt request signal intiica has occurred to check the arbitration result. (a) when arbitration loss occu rs during transmission of slave address data (when wtim = 1) st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 2 1 1: iics = 01000110b 2: iics = 00000001b remark : always generated : generated only when spie = 1
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 640 jun 20, 2011 (b) when arbitration loss occurs dur ing transmission of extension code st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 2 1 1: iics = 0110010b sets lrel = 1 by software 2: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (c) when arbitration loss occu rs during transmission of data (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 2 1 1: iics = 10001110b 2: iics = 01000000b 3: iics = 00000001b remark : always generated : generated only when spie = 1
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 641 jun 20, 2011 (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack ack sp 3 2 1 1: iics = 10001110b 2: iics = 01000100b 3: iics = 00000001b remark : always generated : generated only when spie = 1 (d) when loss occurs due to rest art condition during data transfer (i) not extension code (example: unmatches with sva) st ad6 to ad0 r/w ack d7 to dn ad6 to ad0 ack sp st r/w d7 to d0 ack 3 2 1 1: iics = 1000110b 2: iics = 01000110b 3: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care n = 6 to 0
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 642 jun 20, 2011 (ii) extension code st ad6 to ad0 r/w ack d7 to dn ad6 to ad0 ack sp st r/w d7 to d0 ack 3 2 1 1: iics = 1000110b 2: iics = 01100010b sets lrel = 1 by software 3: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care n = 6 to 0 (e) when loss occurs due to st op condition during data transfer st ad6 to ad0 r/w ack d7 to dn sp 2 1 1: iics = 10000110b 2: iics = 01000001b remark : always generated : generated only when spie = 1 : don?t care n = 6 to 0
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 643 jun 20, 2011 (f) when arbitration loss occurs due to low-level da ta when attempting to generate a restart condition (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack stt = 1 3 4 5 2 1 1: iics = 1000110b 2: iics = 1000000b (sets wtim to 1) 3: iics = 1000100b (clears wtim to 0) 4: iics = 01000000b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack stt = 1 3 4 2 1 1: iics = 1000110b 2: iics = 1000100b (sets stt to 1) 3: iics = 01000100b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 644 jun 20, 2011 (g) when arbitration loss occurs due to a stop cond ition when attempting to generate a restart condition (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 ack sp stt = 1 3 4 2 1 1: iics = 1000110b 2: iics = 1000000b (sets wtim to 1) 3: iics = 100000b (sets stt to 1) 4: iics = 01000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp stt = 1 2 3 1 1: iics = 1000110b 2: iics = 100000b (sets stt to 1) 3: iics = 01000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 645 jun 20, 2011 (h) when arbitration loss occurs due to low-level data when attemp ting to generate a stop condition (i) when wtim = 0 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack spt = 1 3 4 5 2 1 1: iics = 1000110b 2: iics = 1000000b (sets wtim to 1) 3: iics = 1000100b (clears wtim to 0) 4: iics = 01000100b 5: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care (ii) when wtim = 1 st ad6 to ad0 r/w ack d7 to d0 d7 to d0 ack sp ack d7 to d0 ack spt = 1 3 4 2 1 1: iics = 1000110b 2: iics = 1000100b (sets spt to 1) 3: iics = 01000100b 4: iics = 00000001b remark : always generated : generated only when spie = 1 : don?t care
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 646 jun 20, 2011 15.6 timing charts when using the i 2 c bus mode, the master device out puts an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the ma ster device transmits the trc bit (bit 3 of the iica status register (iics)), which specifies the data transfer di rection, and then starts serial communication with the slave device. figures 15-32 and 15-33 show timing charts of the data communication. the iica shift register (iica)?s shift operation is synchronized with the falling ed ge of the serial clock (scl0). the transmit data is transferred to the so latch an d is output (msb first) via the sda0 pin. data input via the sda0 pin is captured into iica at the rising edge of scl0.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 647 jun 20, 2011 figure 15-32. example of master to slave communication (when 9-clock wait is selected for master, 9-clock wait is selected for slave) (1/4) (1) start condition ~ address ~ data iica stt (st trigger) spt (sp trigger) ackd (ack detection) wtim (8 or 9 clock wait) acke (ack control) msts (communication status) trc (transmit/receive) scl0 (bus) (clock line) wrel (wait cancellation) intiica (interrupt) sda0 (bus) (data line) w ack <2> iica std (st detection) spd (sp detection) ackd (ack detection) acke (ack control) msts (communication status) trc (transmit/receive) wrel (wait cancellation) intiica (interrupt) master side bus line slave side slave address l l h l h h h l ad5 ad4 ad3 ad2 ad1 ad0 wtim (8 or 9 clock wait) note 1 start condition d 1 7 ad6 note 2 note 3 <5> <1> <4> <3> <6> : wait state by slave device : wait state by master and slave devices notes 1. write data to iica, not setting the wrel bit, in or der to cancel a wait stat e during master transmission. 2. make sure that the time between the fall of the sda0 pin signal and the fall of the scl0 pin signal is at least 4.0 s when specifying standard mode and at least 0.6 s when specifying fast mode. 3. to cancel slave wait, write ?ffh? to iica or set the wrel bit.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 648 jun 20, 2011 the meanings of <1> to <6> in (1) start condition ~ address ~ data in figure 15-32 are explained below. <1> the start condition trigger is set by the master device (stt = 1) and a start condition (sda0 = 0 and scl0 = 1) is generated once the bus data line goes low (s da0 = 0). when the start condition is subsequently detected, the master devi ce enters the master device communicat ion status (msts = 1). the master device is ready to communicate once the bus clock line goes low (scl0 = 0) after the hold time has elapsed. <2> the master device writes the address + w (transmissio n) to the iica shift register (iica) and transmits the slave address. <3> if the address received matches the address of a slave device note , that slave device sends an ack by hardware to the master device. the ack is detected by the master device (ackd = 1) at the rising edge of the 9th clock. <4> the master device issues an interrupt (intiica: end of address transmission) at the falling edge of the 9th clock, and the slave device whose address matched t he transmitted slave address also issues an interrupt (intiica: address match). the master device and sl ave device also set a wait status (scl0 = 0) note when the addresses match. <5> the master device writes the data to transmit to the iic a register and releases the wa it status that it set by the master device. <6> if the slave device releases the wait status (wrel = 1), the master device starts transferring data to the slave device. note if the transmitted address does not match the address of the slave device, the slave device does not return an ack to the master device (nack: sda0 = 1). the sl ave device also does not issue the intiica interrupt (address match) and does not set a wait status. the ma ster device, however, issues the intiica interrupt (end of address transmission) regardless of whether it receives an ack or nack. remark <1> to <15> in figure 15-32 represent the enti re procedure for communicating data using the i 2 c bus. figure 15-32 (1) start condition ~ address ~ data shows the processing from <1> to <6>, figure 15-32 (2) address ~ data ~ data shows the processing from <3> to <10>, and figure 15-32 (3) data ~ data ~ stop condition shows the processing from <7> to <15>.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 649 jun 20, 2011 figure 15-32. example of master to slave communication (when 9-clock wait is selected for master, 9-clock wait is selected for slave) (2/4) (2) address ~ data ~ data iica stt (st trigger) spt (sp trigger) ackd (ack detection) wtim (8 or 9 clock wait) acke (ack control) msts (communication status) trc (transmit/receive) scl0 (bus) (clock line) wrel (wait cancellation) intiica (interrupt) sda0 (bus) (data line) iica std (st detection) spd (sp detection) ackd (ack detection) wtim (8 or 9 clock wait) acke (ack control) msts (communication status) trc (transmit/receive) wrel (wait cancellation) intiica (interrupt) w ack master side bus line slave side h h l h l l l h h l l d 1 6 d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 1 7 d 2 7 ack h note 2 <10> <6> <7> <8> <3> <4> note 1 note 1 <9> <5> note 2 : wait state by slave device : wait state by master and slave devices notes 1. write data to iica, not setting the wrel bit, in orde r to cancel a wait state during master transmission. 2. to cancel slave wait, write ?ffh? to iica or set the wrel bit.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 650 jun 20, 2011 the meanings of <3> to <10> in (2) address ~ data ~ data in figure 15-32 are explained below. <3> if the address received matches the address of a slave device note , that slave device sends an ack by hardware to the master device. the ack is detected by the master device (ackd = 1) at the rising edge of the 9th clock. <4> the master device issues an interrupt (intiica: end of address transmission) at the falling edge of the 9th clock, and the slave device whose address matched t he transmitted slave address also issues an interrupt (intiica: address match). the master device and sl ave device also set a wait status (scl0 = 0) note when the addresses match. <5> the master device writes the data to transmit to the iica shift register (iica) and releases the wait status that it set by the master device. <6> if the slave device releases the wait status (wrel = 1), the master device starts transferring data to the slave device. <7> when data transfer is complete, the slave device sends an ack by hardware to the master device. the ack is detected by the master device (ackd = 1) at the rising edge of the 9th clock. <8> the master device and slave device set a wait stat us (scl0 = 0) at the falling edge of the 9th clock, and both the master device and slave device i ssue an interrupt (intiica: end of transfer). <9> the master device writes the data to transmit to the iic a register and releases the wa it status that it set by the master device. <10> the slave device reads the received data and releases the wait status (wrel = 1). the master device then starts transferring data to the slave device. note if the transmitted address does not match the address of the slave device, the slave device does not return an ack to the master device (nack: sda0 = 1). the sl ave device also does not issue the intiica interrupt (address match) and does not set a wait status. the ma ster device, however, issues the intiica interrupt (end of address transmission) regardless of whether it receives an ack or nack. remark <1> to <15> in figure 15-32 represent the enti re procedure for communicating data using the i 2 c bus. figure 15-32 (1) start condition ~ address ~ data shows the processing from <1> to <6>, figure 15-32 (2) address ~ data ~ data shows the processing from <3> to <10>, and figure 15-32 (3) data ~ data ~ stop condition shows the processing from <7> to <15>.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 651 jun 20, 2011 figure 15-32. example of master to slave communication (when 9-clock wait is selected for master, 9-clock wait is selected for slave) (3/4) (3) data ~ data ~ stop condition master side d 16 1 iica stt (st trigger) spt (sp trigger) ackd (ack detection) wtim (8 or 9 clock wait) acke (ack control) msts (communication status) trc (transmit/receive) scl0 (bus) (clock line) wrel (wait cancellation) intiica (interrupt) sda0 (bus) (data line) d 16 2 d 16 3 d 16 4 d 16 5 d 16 0 d 16 6 iica std (st detection) spd (sp detection) ackd (ack detection) wtim (8 or 9 clock wait) acke (ack control) msts (communication status) trc (transmit/receive) wrel (wait cancellation) intiica (interrupt) d 15 0 d 16 7 bus line slave side l l h h l l h h l ack ack note 1 stop condition <14> <9> note 2 <8> <12> <7> <11> <15> <10> <13> note 3 note 3 : wait state by master device : wait state by slave device : wait state by master and slave devices notes 1. write data to iica, not setting the wrel bit, in or der to cancel a wait stat e during master transmission. 2. make sure that the time between the rise of the scl0 pin signal and the generation of the stop condition after a stop condition has been issued is at least 4.0 s when specifying standard mode and at least 0.6 s when specifying fast mode. 3. to cancel slave wait, write ?ffh? to iica or set the wrel bit.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 652 jun 20, 2011 the meanings of <7> to <15> in (3) data ~ data ~ stop condition in figure 15-32 are explained below. <7> when data transfer is complete, the slave device sends an ack by hardware to the master device. the ack is detected by the master device (ackd = 1) at the rising edge of the 9th clock. <8> the master device and slave device set a wait stat us (scl0 = 0) at the falling edge of the 9th clock, and both the master device and slave device i ssue an interrupt (intiica: end of transfer). <9> the master device writes the data to transmit to the iica shift register (iica) and releases the wait status that it set by the master device. <10> the slave device reads the received data and releases the wait status (wrel = 1). the master device then starts transferring data to the slave device. <11> when data transfer is complete, the slave device sends an ack by hardware to the master device. the ack is detected by the master device (ackd = 1) at the rising edge of the 9th clock. <12> the master device and slave device set a wait stat us (scl0 = 0) at the falling edge of the 9th clock, and both the master device and slave device i ssue an interrupt (intiica: end of transfer). <13> the slave device reads the received dat a and releases the wait status (wrel = 1). <14> after a stop condition trigger is set, the bus data line is cleared (sda0 = 0) and the bus clock line is set (scl0 = 1). the stop condition is then generated by setting the bus data line (sda0 = 1) after the stop condition setup time has elapsed. <15> when a stop condition is generat ed, the slave device detects the st op condition and issues an interrupt (intiica: stop condition). remark <1> to <15> in figure 15-32 represent the enti re procedure for communicating data using the i 2 c bus. figure 15-32 (1) start condition ~ address ~ data shows the processing from <1> to <6>, figure 15-32 (2) address ~ data ~ data shows the processing from <3> to <10>, and figure 15-32 (3) data ~ data ~ stop condition shows the processing from <7> to <15>.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 653 jun 20, 2011 figure 15-32. example of master to slave communication (when 9-clock wait is selected for master, 9-clock wait is selected for slave) (4/4) (4) data ~ restart condition ~ address l h l h l h iica stt (st trigger) spt (sp trigger) ackd (ack detection) wtim (8 or 9 clock wait) acke (ack control) msts (communication status) trc (transmit/receive) scl0 (bus) (clock line) wrel (wait cancellation) intiica (interrupt) sda0 (bus) (data line) ad6 iica std (st detection) spd (sp detection) ackd (ack detection) wtim (8 or 9 clock wait) acke (ack control) msts (communication status) trc (transmit/receive) wrel (wait cancellation) intiica (interrupt) master side bus line slave side slave address d 1 3 ack l h h l h restart condition d 1 2 d 1 1 d 1 0 ad5 ad4 ad3 ad2 ad1 <7> <8> note 2 note 1 : wait state by master device : wait state by slave device : wait state by master and slave devices notes 1. make sure that the time between the rise of the scl0 pin signal and the generation of the start condition after a restart condition has been issued is at least 4.7 s when specifying standard mode and at least 0.6 s when specifying fast mode. 2. to cancel slave wait, write ?ffh? to iica or set the wrel bit.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 654 jun 20, 2011 the following describes the operations in figure 15-32 (4) data ~ restart condition ~ address. after the operations in steps <7> and <8>, the operations in steps <1> to <3> are performed. these steps re turn the processing to step <3>, the data transmission step. <7> when data transfer is complete, the slave device sends an ack by hardware to the master device. the ack is detected by the master device (ackd = 1) at the rising edge of the 9th clock. <8> the master device and slave device set a wait stat us (scl0 = 0) at the falling edge of the 9th clock, and both the master device and slave device i ssue an interrupt (intiica: end of transfer). the slave device reads the received data and releases the wait status (wrel = 1). the start condition trigger is set again by the mast er device (stt = 1) and a start condition (sda0 = 0 and scl0 = 1) is generated once the bus clock line goes high (scl0 = 1) and the bus data line goes low (sda0 = 0) after the restart condition setup time has elaps ed. when the start condition is subsequently detected, the master device is ready to communicate once the bus clock line goes low (scl0 = 0) after the hold time has elapsed. the master device writes the address + r/w (transmission) to the iica shift register (iica) and transmits the slave address.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 655 jun 20, 2011 figure 15-33. example of slave to master communication (when 8-clock wait is selected for master, 9-clock wait is selected for slave) (1/3) (1) start condition ~ address ~ data iica stt (st trigger) spt (sp trigger) ackd (ack detection) wtim (8 or 9 clock wait) acke (ack control) msts (communication status) trc (transmit/receive) scl0 (bus) (clock line) wrel (wait cancellation) intiica (interrupt) sda0 (bus) (data line) ad6 d 1 7 r ack iica std (st detection) spd (sp detection) ackd (ack detection) wtim (8 or 9 clock wait) acke (ack control) msts (communication status) trc (transmit/receive) wrel (wait cancellation) intiica (interrupt) master side bus line slave side slave address l l h h h l ad5 ad4 ad3 ad2 ad1 ad0 start condition note 2 note 1 note 3 <2> <5> <1> <7> <3> <4> <6> : wait state by master device : wait state by slave device : wait state by master and slave devices notes 1. to cancel master wait, write ?ffh? to iica or set the wrel bit. 2. make sure that the time between the fall of the sda0 pin signal and the fall of the scl0 pin signal is at least 4.0 s when specifying standard mode and at least 0.6 s when specifying fast mode. 3. write data to iica, not setting the wrel bit, in or der to cancel a wait state during slave transmission.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 656 jun 20, 2011 the meanings of <1> to <7> in (1) start condition ~ address ~ data in figure 15-33 are explained below. <1> the start condition trigger is set by the master device (stt = 1) and a start condition (sda0 = 0 and scl0 = 1) is generated once the bus data line goes low (s da0 = 0). when the start condition is subsequently detected, the master devi ce enters the master device communicat ion status (msts = 1). the master device is ready to communicate once the bus clock line goes low (scl0 = 0) after the hold time has elapsed. <2> the master device writes the address + w (transmissio n) to the iica shift register (iica) and transmits the slave address. <3> if the address received matches the address of a slave device note , that slave device sends an ack by hardware to the master device. the ack is detected by the master device (ackd = 1) at the rising edge of the 9th clock. <4> the master device issues an interrupt (intiica: end of address transmission) at the falling edge of the 9th clock, and the slave device whose address matched t he transmitted slave address also issues an interrupt (intiica: address match). the master device and sl ave device also set a wait status (scl0 = 0) note when the addresses match. <5> the timing at which the master device sets the wait status changes to the 8th clock (wtim = 0). <6> the slave device writes the data to transmit to the iic a register and releases the wa it status that it set by the slave device. <7> if the master device releases the wait status (wrel = 1), the slave device starts transferring data to the master device. note if the transmitted address does not match the address of the slave device, the slave device does not return an ack to the master device (nack: sda0 = 1). the sl ave device also does not issue the intiica interrupt (address match) and does not set a wait status. the ma ster device, however, issues the intiica interrupt (end of address transmission) regardless of whether it receives an ack or nack. remark <1> to <19> in figure 15-33 represent the enti re procedure for communicating data using the i 2 c bus. figure 15-33 (1) start condition ~ address ~ data shows the processing from <1> to <7>, figure 15-33 (2) address ~ data ~ data shows the processing from <3> to <12>, and figure 15-33 (3) data ~ data ~ stop condition shows the processing from <8> to <19>.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 657 jun 20, 2011 figure 15-33. example of slave to master communication (when 8-clock wait is selected for master, 9-clock wait is selected for slave) (2/3) (2) address ~ data ~ data iica stt (st trigger) spt (sp trigger) ackd (ack detection) wtim (8 or 9 clock wait) acke (ack control) msts (communication status) trc (transmit/receive) scl0 (bus) (clock line) wrel (wait cancellation) intiica (interrupt) sda0 (bus) (data line) iica std (st detection) spd (sp detection) ackd (ack detection) wtim (8 or 9 clock wait) acke (ack control) msts (communication status) trc (transmit/receive) wrel (wait cancellation) intiica (interrupt) r ack ack master side bus line slave side h h l h l l h l h l l d 1 7 d 1 6d 1 5d 1 4d 1 3d 1 2d 1 1d 1 0 d 2 7 note 1 note 1 <5> <7> <9> note 2 note 2 <4> <8> <11> <10> <12> <6> <3> : wait state by master device : wait state by slave device : wait state by master and slave devices notes 1. to cancel master wait, write ?ffh? to iica or set the wrel bit. 2. write data to iica, not setting the wrel bit, in or der to cancel a wait state during slave transmission.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 658 jun 20, 2011 the meanings of <3> to <12> in (2) address ~ data ~ data in figure 15-33 are explained below. <3> if the address received matches the address of a slave device note , that slave device sends an ack by hardware to the master device. the ack is detected by the master device (ackd = 1) at the rising edge of the 9th clock. <4> the master device issues an interrupt (intiica: end of address transmission) at the falling edge of the 9th clock, and the slave device whose address matched t he transmitted slave address also issues an interrupt (intiica: address match). the master device and sl ave device also set a wait status (scl0 = 0) note when the addresses match. <5> the timing at which the master device sets the wait status changes to the 8th clock (wtim = 0). <6> the slave device writes the data to transmit to the iic a shift register (iica) and rel eases the wait status that it set by the slave device. <7> if the master device releases the wait status (wrel = 1), the slave device starts transferring data to the master device. <8> the master device sets a wait status (scl0 = 0) at the falling edge of the 8th cl ock, and issues an interrupt (intiica: end of transfer). the master device then sends an ack by hardware to the slave device. <9> the master device reads the received data and releases the wait status (wrel = 1). <10> the ack is detected by the slave device (a ckd = 1) at the rising edge of the 9th clock. <11> the slave device set a wait status (scl0 = 0) at t he falling edge of the 9th clock, and the slave device issue an interrupt (intiica: end of transfer). <12> the slave device writes the data to transmit to the iica register and releases the wa it status that it set by the slave device. the slave device then starts transferring data to the master device. note if the transmitted address does not match the address of the slave device, the slave device does not return an ack to the master device (nack: sda0 = 1). the sl ave device also does not issue the intiica interrupt (address match) and does not set a wait status. the ma ster device, however, issues the intiica interrupt (end of address transmission) regardless of whether it receives an ack or nack. remark <1> to <19> in figure 15-33 represent the enti re procedure for communicating data using the i 2 c bus. figure 15-33 (1) start condition ~ address ~ data shows the processing from <1> to <7>, figure 15-33 (2) address ~ data ~ data shows the processing from <3> to <12>, and figure 15-33 (3) data ~ data ~ stop condition shows the processing from <8> to <19>.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 659 jun 20, 2011 figure 15-33. example of slave to master communication (when 8-clock and 9-clock wait is selected for m aster, 9-clock wait is selected for slave) (3/3) (3) data ~ data ~ stop condition iica stt (st trigger) spt (sp trigger) ackd (ack detection) wtim (8 or 9 clock wait) acke (ack control) msts (communication status) trc (transmit/receive) scl0 (bus) (clock line) wrel (wait cancellation) intiica (interrupt) sda0 (bus) (data line) iica std (st detection) spd (sp detection) ackd (ack detection) wtim (8 or 9 clock wait) acke (ack control) msts (communication status ) trc (transmit/receive) wrel (wait cancellation) intiica (interrupt) d 15 0 master side bus line slave side h l h l l l ack nack d 16 7 d 16 6 d 16 5 d 16 4 d 16 3 d 16 2 d 16 1 d 16 0 stop conditon note 1 note 1 note 3 note 2 notes 1, 4 note 4 <14> <9> <8> <11> <10> <12> <13> <16> <19> <15> <17> <18> : wait state by master device : wait state by slave device : wait state by master and slave devices notes 1. to cancel a wait state, write ?ffh? to iica or set the wrel bit. 2. make sure that the time between the rise of the scl0 pin signal and the generation of the stop condition after a stop condition has been issued is at least 4.0 s when specifying standard mode and at least 0.6 s when specifying fast mode. 3. write data to iica, not setting the wrel bit, in or der to cancel a wait state during slave transmission. 4. if a wait state during slave transmission is canceled by setting the wrel bit, the trc bit will be cleared.
78k0r/lx3 chapter 15 serial interface iica r01uh0004ej0501 rev.5.01 660 jun 20, 2011 the meanings of <8> to <19> in (3) data ~ data ~ stop condition in figure 15-33 are explained below. <8> the master device sets a wait status (scl0 = 0) at the falling edge of the 8th cl ock, and issues an interrupt (intiica: end of transfer). the master device then sends an ack by hardware to the slave device. <9> the master device reads the received data and releases the wait status (wrel = 1). <10> the ack is detected by the slave device (a ckd = 1) at the rising edge of the 9th clock. <11> the slave device set a wait status (scl0 = 0) at t he falling edge of the 9th clock, and the slave device issue an interrupt (intiica: end of transfer). <12> the slave device writes the data to transmit to the iic a shift register (iica) and rel eases the wait status that it set by the slave device. the slave device t hen starts transferring data to the master device. <13> the master device issues an inte rrupt (intiica: end of transfer) at th e falling edge of the 8th clock, and sets a wait status (scl0 = 0). because ack control (acke = 1) is performed, the bus data line is at the low level (sda0 = 0) at this stage. <14> the master device sets nack as the response (ac ke = 0) and changes the timing at which it sets the wait status to the 9th clock. <15> if the master device releases t he wait status (wrel = 1), the slave de vice detects the nack (ack = 0) at the rising edge of the 9th clock. <16> the master device and slave device set a wait stat us (scl0 = 0) at the falling edge of the 9th clock, and both the master device and slave device i ssue an interrupt (intiica: end of transfer). <17> when the master device issues a stop condition (s pt = 1), the bus data line is cleared (sda0 = 0) and the master device releases the wait st atus. the master device then waits until the bus clock line is set (scl0 = 1). <18> the slave device acknowledges the nack, halts trans mission, and releases the wait status (wrel = 1) to end communication. once the slave device releases t he wait status, the bus clock line is set (scl0 = 1). <19> once the master device recognizes that the bu s clock line is set (scl0 = 1) and after the stop condition setup time has elapsed, the master device sets the bus data line (sda0 = 1) and issues a stop condition. the slave device detects the generated stop condition and both the master device and slave device issue an interrupt (intiica: stop condition). remark <1> to <19> in figure 15-33 represent the enti re procedure for communicating data using the i 2 c bus. figure 15-33 (1) start condition ~ address ~ data shows the processing from <1> to <7>, figure 15-33 (2) address ~ data ~ data shows the processing from <3> to <12>, and figure 15-33 (3) data ~ data ~ stop condition shows the processing from <8> to <19>.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 661 jun 20, 2011 chapter 16 lcd controller/driver 78k0r/lf3 78k0r/lg3 78k0r/lh3 item 80 pins 100 pins 128 pins lcd controller/driver segment signal outputs: 31 common signal outputs: 8 segment signal outputs: 40 common signal outputs: 8 segment signal outputs: 54 common signal outputs: 8 16.1 functions of lcd controller/driver the functions of the lcd contro ller/driver in the 78k0r/lx3 microcontrollers are as follows. (1) the lcd driver voltage generator can switch internal voltage boosting method, capacitor split method, and external resistance division method. (2) automatic output of segment and common signal s based on automatic display data memory read (3) six different display modes: ? static ? 1/2 duty (1/2 bias) ? 1/3 duty (1/2 bias) ? 1/3 duty (1/3 bias) ? 1/4 duty (1/3 bias) ? 1/8 duty (1/4 bias) (4) six different frame frequencies, selectable in each display mode (5) the reference voltage to be generat ed when operating the voltage boost circ uit can be selected from 20 stages (contrast adjustment). (6) the data display of the lcd display dat a memory can be selected from three types. ? displaying an a-pattern area (lower four bits) ? displaying a b-pattern area (higher four bits) ? alternately displaying a-pattern and b-pattern areas (blinking display corresponding to the constant-period interrupt (intrtc) timing of the real-time counter (rtc)) (7) 78k0r/lf3: segment signal outputs: 31 note (seg0 to seg30), common signal outputs: 8 note (com0 to com7) 78k0r/lg3: segment signal outputs: 40 note (seg0 to seg39), common signal outputs: 8 note (com0 to com7) 78k0r/lh3: segment signal outputs: 54 note (seg0 to seg53), common signal outputs: 8 note (com0 to com7) note the four segment signal outputs (seg0 to seg3) and four comm on signal outputs (com4 to com7) are alternate-function pins. com4 to com7 can be used only when eight-time-s lice mode is selected by the setting of the lcd display mode register (lcdm).
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 662 jun 20, 2011 table 16-1 lists the maximum number of pixels that can be displayed in each display mode. table 16-1. maximum nu mber of pixels (1/3) (a) 78k0r/lf3 lcd driver voltage generator bias mode number of time slices common signals used number of segments maximum number of pixels ? static com0 (com1 to com3) 31 (31 segment signals, 1 common signal) note 1 2 com0, com1 62 (31 segment signals, 2 common signals) note 2 1/2 3 com0 to com2 3 com0 to com2 93 (31 segment signals, 3 common signals) note 3 1/3 4 com0 to com3 31 124 (31 segment signals, 4 common signals) note 4 external resistance division 1/4 8 com0 to com7 27 216 (27 segment signals, 8 common signals) note 5 3 com0 to com2 93 (31 segment signals, 3 common signals) note 1/3 4 com0 to com3 31 124 (31 segment signals, 4 common signals) note 4 internal voltage boosting 1/4 8 com0 to com7 27 216 (27 segment signals, 8 common signals) note 5 3 com0 to com2 93 (31 segment signals, 3 common signals) note3 capacitor split 1/3 4 com0 to com3 31 124 (31 segment signals, 4 common signals) note 4 notes 1. 3-digit lcd panel, each digit having an 8-segment configuration. 2. 7-digit lcd panel, each digit having a 4-segment configuration. 3. 11-digit lcd panel, each digit having a 3-segment configuration. 4. 15-digit lcd panel, each digit having a 2-segment configuration. 5. 27-digit lcd panel, each digit having a 1-segment configuration.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 663 jun 20, 2011 table 16-1. maximum nu mber of pixels (2/3) (b) 78k0r/lg3 lcd driver voltage generator bias mode number of time slices common signals used number of segments maximum number of pixels ? static com0 (com1 to com3) 40 (40 segment signals, 1 common signal) note 1 2 com0, com1 80 (40 segment signals, 2 common signals) note 2 1/2 3 com0 to com2 3 com0 to com2 120 (40 segment signals, 3 common signals) note 3 1/3 4 com0 to com3 40 160 (40 segment signals, 4 common signals) note 4 external resistance division 1/4 8 com0 to com7 36 288 (36 segment signals, 8 common signals) note 5 3 com0 to com2 120 (40 segment signals, 3 common signals) note3 1/3 4 com0 to com3 40 160 (40 segment signals, 4 common signals) note 4 internal voltage boosting 1/4 8 com0 to com7 36 288 (36 segment signals, 8 common signals) note 5 3 com0 to com2 120 (40 segment signals, 3 common signals) note capacitor split 1/3 4 com0 to com3 40 160 (40 segment signals, 4 common signals) note 4 notes 1. 5-digit lcd panel, each digit having an 8-segment configuration. 2. 10-digit lcd panel, each digit having a 4-segment configuration. 3. 15-digit lcd panel, each digit having a 3-segment configuration. 4. 20-digit lcd panel, each digit having a 2-segment configuration. 5. 36-digit lcd panel, each digit having a 1-segment configuration.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 664 jun 20, 2011 table 16-1. maximum nu mber of pixels (3/3) (b) 78k0r/lg3 lcd driver voltage generator bias mode number of time slices common signals used number of segments maximum number of pixels ? static com0 (com1 to com3) 54 (54 segment signals, 1 common signal) note 1 2 com0, com1 108 (54 segment signals, 2 common signals) note 2 1/2 3 com0 to com2 3 com0 to com2 162 (54 segment signals, 3 common signals) note 3 1/3 4 com0 to com3 54 216 (54 segment signals, 4 common signals) note 4 external resistance division 1/4 8 com0 to com7 50 400 (50 segment signals, 8 common signals) note 5 3 com0 to com2 162 (54 segment signals, 3 common signals) note3 1/3 4 com0 to com3 54 216 (54 segment signals, 4 common signals) note 4 internal voltage boosting 1/4 8 com0 to com7 50 400 (50 segment signals, 8 common signals) note 5 3 com0 to com2 162 (54 segment signals, 3 common signals) note capacitor split 1/3 4 com0 to com3 54 216 (54 segment signals, 4 common signals) note 4 notes 1. 6-digit lcd panel, each digit having an 8-segment configuration. 2. 13-digit lcd panel, each digit having a 4-segment configuration. 3. 20-digit lcd panel, each digit having a 3-segment configuration. 4. 27-digit lcd panel, each digit having a 2-segment configuration. 5. 50-digit lcd panel, each digit having a 1-segment configuration.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 665 jun 20, 2011 16.2 configuration of lcd controller/driver the lcd controller/driver consis ts of the following hardware. table 16-2. configuration of lcd controller/driver item configuration display outputs 78k0r/lf3: 31 segment signals note (seg0 to seg30), 8 common signals note (com0 to com7) 78k0r/lg3: 40 segment signals note (seg0 to seg39), 8 common signals note (com0 to com7) 78k0r/lh3: 54 segment signals note (seg0 to seg53), 8 common signals note (com0 to com7) control registers lcd mode register (lcdmd) lcd display mode register (lcdm) lcd clock control register 0 (lcdc0) lcd boost level control register (vlcd) port function register (pfall) segment enable register (segen) input switch control register (isc) note the four segment signal outputs (seg0 to seg3) and four comm on signal outputs (com4 to com7) are alternate-function pins. com4 to com7 can be used only when eight-time-s lice mode is selected by the setting of the lcd display mode register (lcdm).
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 666 jun 20, 2011 figure 16-1. block diagram of lcd controller/driver remark 78k0r/lf3: 31 segment signals (seg0 to seg30), 8 common signals (com0 to com7) 78k0r/lg3: 40 segment signals (seg0 to seg39), 8 common signals (com0 to com7) 78k0r/lh3: 54 segment signals (seg0 to seg53), 8 common signals (com0 to com7) lcdc4 lcdc2 lcdc1 lcdc0 3 2 f lcd 2 6 f lcd 2 7 f lcd 2 8 f lcd 2 9 vlcon lcdm2 v lc0 com0 com3 3210 65 74 35h seg53 f sub f clk /2 6 f clk /2 7 f lcd lcdon lcdcl lcdm1 v lc2 caph capl v lc1 vlcon lcdm0 vlcd4 lcdon scoc mdset1 mdset0 2 3 lcdc5 f clk /2 8 f lcd 2 5 f lcd 2 4 blon lcdsel 2 vlcd3 vlcd2 vlcd1 vlcd0 5 com4/ seg0 com7/ seg3 3210 65 74 04h lcdon seg4 3210 65 74 3210 65 74 03h lcdon 3210 65 74 3210 65 74 00h lcdon 3210 65 74 3210 65 74 lcd mode register (lcdmd) lcd clock control register 0 (lcdc0) lcd display mode register (lcdm) selector prescaler lcd clock selector internal bus lcd boost level control register (vlcd) timing controller display data memory selector segment driver selector selector selector segment driver segment driver segment driver common driver segment voltage controller common voltage controller lcd drive voltage controller voltage boost circuit capacitor split circuit clock genarator for capacitor split clock genarator for voltage boost intrtc
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 667 jun 20, 2011 16.3 registers controlling lcd controller/driver the following seven registers are used to control the lcd controller/driver. ? lcd mode register (lcdmd) ? lcd display mode register (lcdm) ? lcd clock control register 0 (lcdc0) ? lcd boost level control register (vlcd) ? port function register (pfall) ? segment enable register (segen) ? input switch control register (isc) (1) lcd mode register (lcdmd) lcdmd sets the lcd drive voltage generator. lcdmd is set using a 1-bit or 8-bi t memory manipulation instruction. reset signal generation sets lcdmd to 00h. figure 16-2. format of lcd mode register (lcdmd) address: fff40h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 lcdmd 0 0 mdset1 mdset0 0 0 0 0 mdset1 mdset0 lcd drive voltage generator selection 0 0 external resistance division method 0 1 internal voltage boosting method 1 0 capacitor split method 1 1 setting prohibited caution bits 0 to 3, 6 and 7 must be set to 0. (2) lcd display mode register (lcdm) lcdm is a register that enables/dis ables display operation, enables/disables voltage boost circuit or capacitor split circuit operation, and sets the di splay data area and the display mode. lcdm is set using a 1-bit or 8-bi t memory manipulation instruction. reset signal generation sets lcdm to 00h.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 668 jun 20, 2011 figure 16-3. format of lcd di splay mode register (lcdm) address: fff41h after reset : 00h r/w symbol <7> <6> <5> <4> <3> 2 1 0 lcdm lcdon scoc vlcon blon lcdsel lcdm2 lcdm1 lcdm0 lcdon scoc lcd display enable/disable 0 0 output ground level to segment/common pin 0 1 display off (all segment outputs are deselected.) 1 0 output ground level to segment/common pin 1 1 display on vlcon voltage boost circuit or capacitor split circ uit operation enable/disable 0 stops voltage boost circuit or capacitor split circuit operation 1 enables voltage boost circuit or capacitor split circuit operation blon lcdsel display data area control 0 0 displaying an a-pattern area data (lower four bits of lcd display data memory) 0 1 displaying a b-pattern area data (higher four bits of lcd display data memory) 1 0 1 1 alternately displaying a-pattern and b-pattern area data (blinking display corresponding to the constant-period interrupt (intrtc) timing of the real-time counter (rtc)) lcd controller/driver display mode selection external resistance division method internal voltage boosting method capacitor split method lcdm2 lcdm1 lcdm0 number of time slices bias mode number of time slices bias mode number of time slices bias mode 0 0 0 4 1/3 4 1/3 4 1/3 0 0 1 3 1/3 3 1/3 3 1/3 0 1 0 2 1/2 4 1/3 4 1/3 0 1 1 3 1/2 4 1/3 4 1/3 1 0 0 static setting prohibited 1 1 1 8 1/4 8 1/4 4 1/3 other than above setting prohibited cautions 1. when lcd display is not performed or n ecessary, set scoc and vlcon to 0, in order to reduce power consumption. 2. when the external resistan ce division method has been set (mdset1 = mdset0 = 0), do not set vlcon to 1. 3. set blon and lcdsel to 0 when 8 has b een selected as the number of time slices for the display mode. 4. to use the internal voltage boosting method, specify the reference vo ltage by using the vlcd register (or perform a reset to use the default value of the re ference voltage), wait for the reference voltage setup time (2 ms (min.)), and then set vlcon to 1.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 669 jun 20, 2011 caution 5. to manipulate vlcon when using the in ternal voltage boosting method or capacitor split method, follow the procedure below. a. to stop the operation of the voltage boosting/cap acitor split circuit a fter switching display status from on to off: 1) set to display off stat us by setting lcdon = 0. 2) disable outputs of all the segment buffers and common buffers by setting scoc = 0. 3) stop the operation of the voltage boosting/cap acitor split circuit by setting vlcon = 0. b. to stop the operation of the voltage boosting/cap acitor split circuit during display on status: setting prohibited. be sure to stop the ope ration of the voltage boosting/capacitor split circuit after setting display off. c. to set display on from stop status of the voltage boosting/cap acitor split circuit: 1) start the operation of the voltage boosting/ capacitor split circuit by setting vlcon = 1, then wait for the voltage boosting/cap acitor split wait time (see chapter 31 electrical specifications). 2) set all the segment buffers and common bu ffers to non-display output status by setting scoc = 1. 3) set display on by setting lcdon = 1. (3) lcd clock control register (lcdc0) lcdc0 specifies the lcd source clock and lcd clock. the frame frequency is determined according to t he lcd clock and the number of time slices. lcdc0 is set using an 8-bit memory manipulation instruction. reset signal generation sets lcdc0 to 00h. figure 16-4. format of lcd cl ock control register (lcdc0) address: fff42h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 lcdc0 0 0 l cdc5 lcdc4 0 lcdc2 lcdc1 lcdc0 lcdc5 lcdc4 lcd source clock (f lcd ) selection 0 0 f sub 0 1 f clk /2 6 1 0 f clk /2 7 1 1 f clk /2 8 lcdc2 lcdc1 lcdc0 lcd clock (lcdcl) selection 0 0 0 f lcd /2 4 0 0 1 f lcd /2 5 0 1 0 f lcd /2 6 0 1 1 f lcd /2 7 1 0 0 f lcd /2 8 1 0 1 f lcd /2 9 other than above setting prohibited
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 670 jun 20, 2011 cautions 1. bits 3, 6, and 7 must be set to 0. 2. set the lcd clock (lcdcl) to no more than 512 hz when the internal voltage boost method has been set. remark f clk : cpu/peripheral hardware clock frequency f sub : subsystem clock frequency (4) lcd boost level control register (vlcd) this register is used to select the reference vo ltage that is to be generated when operating the voltage boost circuit (contrast adjustment). the refe rence voltage can be se lected from 20 stages. vlcd is set using an 8-bit memory manipulation instruction. reset signal generation sets vlcd to 0fh. figure 16-5. format of lcd boost level control register (vlcd) address: fff43h after reset : 0fh r/w symbol 7 6 5 4 3 2 1 0 vlcd 0 0 0 vlcd4 vlcd3 vlcd2 vlcd1 vlcd0 v lc0 voltage vlcd4 vlcd3 vlcd2 vlcd1 vlcd0 reference voltage selection (contrast adjustment) 1/3 bias 1/4 bias 0 0 0 0 0 1.75 v 5.25 v 0 0 0 0 1 1.70 v 5.10 v 0 0 0 1 0 1.65 v 4.95 v 0 0 0 1 1 1.60 v 4.80 v 0 0 1 0 0 1.55 v 4.65 v 0 0 1 0 1 1.50 v 4.50 v 0 0 1 1 0 1.45 v 4.35 v 0 0 1 1 1 1.40 v 4.20 v 0 1 0 0 0 1.35 v 4.05 v setting prohibited note 0 1 0 0 1 1.30 v 3.90 v 5.20 v 0 1 0 1 0 1.25 v 3.75 v 5.00 v 0 1 0 1 1 1.20 v 3.60 v 4.80 v 0 1 1 0 0 1.15 v 3.45 v 4.60 v 0 1 1 0 1 1.10 v 3.30 v 4.40 v 0 1 1 1 0 1.05 v 3.15 v 4.20 v 0 1 1 1 1 1.00 v (default) 3.00 v 4.00 v 1 0 0 0 0 0.95 v 2.85 v 3.80 v 1 0 0 0 1 0.90 v 2.70 v 3.60 v 1 0 0 1 0 0.85 v 2.55 v 3.40 v 1 0 0 1 1 0.80 v 2.40 v 3.20 v other than above setting prohibited note these settings are prohibited because v lc0 > 5.5 v.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 671 jun 20, 2011 cautions 1. the vlcd setting is valid only wh en the voltage boost circuit is operating. 2. bits 5 to 7 must be set to 0. 3. be sure to change the vl cd value after having stopped the opera tion of the voltage boost circuit (vlcon = 0). 4. these values abo ve may change after device evaluation. 5. to use the internal voltage boosting method, sp ecify the reference volt age by using the vlcd register (or perform a reset to u se the default value of the referen ce voltage), wait for the reference voltage setup time (2 ms (min. )), and then set vlcon to 1. (5) port function register (pfall) this register sets whether to use pins p50 to p57, p90 to p97, p100 to p102, and p140 to p147 as port pins (other than segment output pi ns) or segment output pins. pfall is set using a 1-bit or 8-bi t memory manipulation instruction. reset signal generation sets pfall to 00h. remark the port pins to be used alternatively with t he segment output pins vary, depending on the product. ? 78k0r/lf3: p50 to p57, p90 to p92, p100, p140 to p147 ? 78k0r/lg3: p50 to p57, p90 to p97, p100, p140 to p147 ? 78k0r/lh3: p50 to p57, p90 to p97, p100 to p102, p140 to p147 figure 16-6. format of port function register (pfall) (1/2) address: f0080h after reset : 00h r/w symbol 7 6 5 4 3 2 1 0 pfall 0 pf14h pf14l pf10 pf9h note pf9l pf5h pf5l pf14h port/segment outputs specific ation of the p144 to p147 pins 0 used the p144 to p147 pins as port (other than segment output) 1 used the p144 to p147 pins as segment output pf14l port/segment outputs specific ation of the p140 to p143 pins 0 used the p140 to p143 pins as port (other than segment output) 1 used the p140 to p143 pins as segment output pf10 port/segment outputs specific ation of the p100 to p102 pins 0 used the p100 to p102 pins as port (other than segment output) 1 used the p100 to p102 pins as segment output pf9h port/segment outputs specific ation of the p94 to p97 pins 0 used the p94 to p97 pins as port (other than segment output) 1 used the p94 to p97 pins as segment output pf9l port/segment outputs specif ication of p90 to p93 pins 0 used the p90 to p93 pins as port (other than segment output) 1 used the p90 to p93 pins as segment output note 78k0r/lg3, 78k0r/lh3 only
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 672 jun 20, 2011 figure 16-6. format of port func tion register (pfall) (2/2) pf5h port/segment outputs specific ation of the p54 to p57 pins 0 used the p54 to p57 pins as port (other than segment output) 1 used the p54 to p57 pins as segment output pf5l port/segment outputs specif ication of p50 to p53 pins 0 used the p50 to p53 pins as port (other than segment output) 1 used the p50 to p53 pins as segment output caution for 78k0r/lf3, bits 3 and 7 must be set to 0. for 78k0r/lg3 and 78k0r/lh3, bit 7 must be set to 0. (6) segment enable register (segen) segen is a register that is used to enable or di sable segment output to segment output only pins. segen is set using a 1-bit or 8-bi t memory manipulation instruction. reset signal generation sets segen to 00h. remark the segment output only pi ns vary, depending on the product. ? 78k0r/lf3: seg8 to seg10 ? 78k0r/lg3: seg8 to seg14 ? 78k0r/lh3: seg8 to seg26
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 673 jun 20, 2011 figure 16-7. format of segment enable register (segen) ? 78k0r/lf3 address: f0081h after reset : 00h r/w symbol 7 6 5 4 3 2 1 0 segen 0 0 0 0 0 0 0 segen0 ? 78k0r/lg3 address: f0081h after reset : 00h r/w symbol 7 6 5 4 3 2 1 0 segen 0 0 0 0 0 0 segen1 segen0 ? 78k0r/lh3 address: f0081h after reset : 00h r/w symbol 7 6 5 4 3 2 1 0 segen 0 0 0 segen4 segen3 segen2 segen1 segen0 segenn output enable/disable to segment output only pins (n = 0 to 4) 0 disables segment output 1 enables segment output cautions 1. segen can be wri tten only once after reset release. 2. for 78k0r/lf3, bits 1 to 7 must be set to 0. for 78k0r/lg3, bits 2 to 7 must be set to 0. for 78k0r/lh3, bits 5 to 7 must be set to 0. the segment output only pi ns operated by segen4 to segen0 are as follows. segment output only pins segen register 78k0r/lf3 78k0r/lg3 78k0r/lh3 sege4 ? ? seg24 to seg26 pins sege3 ? ? seg20 to seg23 pins sege2 ? ? seg16 to seg19 pins sege1 ? seg12 to seg14 pins seg12 to seg15 pins sege0 seg8 to seg10 pins seg8 to seg11 pins seg8 to seg11 pins
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 674 jun 20, 2011 (7) input switch control register (isc) the segment output pins to be used alte rnatively with the ti04, ti02, and rxd3 pins are internally connected with a schmitt trigger buffer. to use these pins as segm ent outputs, input to the sc hmitt trigger buffer must be disabled, in order to prevent through-currents from entering. isc is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets isc to 00h. remark the segment output pins to be us ed alternatively with the ti02, ti04, and rxd3 pins vary, depending on the product. ? 78k0r/lf3: ti04/seg27/p53, ti02/seg28/p52, rxd3/seg30/p50 ? 78k0r/lg3: ti04/seg36/p53, ti02/seg37/p52, rxd3/seg39/p50 ? 78k0r/lh3: ti04/seg50/p53, ti02/seg51/p52, rxd3/seg53/p50 figure 16-8. format of input switch control register (isc) address: fff3ch after reset : 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 isc4 isc3 isc2 isc1 isc0 isc4 ti04/segxx/p53 schmitt trigger buffer control 0 disables input 1 enables input isc3 ti02/segxx/p52 schmitt trigger buffer control 0 disables input 1 enables input isc2 rxd3/segxx/p50 schmitt trigger buffer control 0 disables input 1 enables input caution be sure to clear bits 5 to 7 to ?0?. remark bits 0 and 1 of isc are not used with the lcd controller driver. to use the ti04/segxx/p53, ti02/segxx/p52, and rxd3/seg xx/p50 pins, set the pf5l and iscn (n = 2 to 4) bits as follows, according to the function to be used. pf5l iscn pin function 0 0 port output (default) 0 1 port input, timer input, or serial data input 1 0 segment output 1 1 setting prohibited
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 675 jun 20, 2011 16.4 lcd display data memory the lcd display data memory is mapped at addresses f0400h to f041fh (78k0r/l f3), f0400h to f0427h (78k0r/lg3) or f0400h to f0435h (78k0r/lh3). data in the lcd display data memory can be displayed on the lcd panel using the lcd controller/driver. figure 16-9 to 16-11 show the relationship between t he contents of the lcd di splay data memory and the segment/common outputs. the areas not to be used for display can be used as normal ram. figure 16-9. relationship between lcd display data memory cont ents and segment/common outputs (78k0r/lf3) (a) static, 2-time-slice, 3 -time-slice, and 4-time-slice f041eh f041dh f041ch seg30 seg29 seg28 b7 b6 b5 b4 b3 b2 b1 b0 com3 com2 com1 com0 com3 com2 com1 com0 f0405h f0404h f0403h f0402h f0401h f0400h seg5 seg4 seg3 seg2 seg1 seg0 a-pattern area b-pattern area (b) 8-time-slice f041eh f041dh f041ch seg30 seg29 seg28 b7 b6 b5 b4 b3 b2 b1 b0 com7 com6 com5 com4 com3 com2 com1 com0 f0405h f0404h f0403h f0402h f0401h f0400h seg5 seg4 seg3 seg2 seg1 seg0 note note note note note note note note note note note note note note note note note note note note note note note note note note note note note note note note note the com4 to com7 pins and seg0 to seg3 pins are used alternatively. to use the lcd display data memory when the number of time slices is eight, the area of f0400h to f0403h can be used for a purpose other than display, because it is not used for lcd display.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 676 jun 20, 2011 figure 16-10. relationship between lcd display data memory cont ents and segment/common outputs (78k0r/lg3) (a) static, 2-time-slice, 3 -time-slice, and 4-time-slice f0427h f0426h f0425h seg39 seg38 seg37 b7 b6 b5 b4 b3 b2 b1 b0 com3 com2 com1 com0 com3 com2 com1 com0 f0405h f0404h f0403h f0402h f0401h f0400h seg5 seg4 seg3 seg2 seg1 seg0 a-pattern area b-pattern area (b) 8-time-slice f0427h f0426h f0425h seg39 seg38 seg37 b7 b6 b5 b4 b3 b2 b1 b0 com7 com6 com5 com4 com3 com2 com1 com0 f0405h f0404h f0403h f0402h f0401h f0400h seg5 seg4 seg3 seg2 seg1 seg0 note note note note note note note note note note note note note note note note note note note note note note note note note note note note note note note note note the com4 to com7 pins and seg0 to seg3 pins are used alternatively. to use the lcd display data memory when the number of time slices is eight, the area of f0400h to f0403h can be used for a purpose other than display, because it is not used for lcd display.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 677 jun 20, 2011 figure 16-11. relationship between lcd display data memory cont ents and segment/common outputs (78k0r/lh3) (a) static, 2-time-slice, 3 -time-slice, and 4-time-slice f0435h f0434h f0433h seg53 seg52 seg51 b7 b6 b5 b4 b3 b2 b1 b0 com3 com2 com1 com0 com3 com2 com1 com0 f0405h f0404h f0403h f0402h f0401h f0400h seg5 seg4 seg3 seg2 seg1 seg0 a-pattern area b-pattern area (b) 8-time-slice f0435h f0434h f0433h seg53 seg52 seg51 b7 b6 b5 b4 b3 b2 b1 b0 com7 com6 com5 com4 com3 com2 com1 com0 f0405h f0404h f0403h f0402h f0401h f0400h seg5 seg4 seg3 seg2 seg1 seg0 note note note note note note note note note note note note note note note note note note note note note note note note note note note note note note note note note the com4 to com7 pins and seg0 to seg3 pins are used alternatively. to use the lcd display data memory when the number of time slices is eight, the area of f0400h to f0403h can be used for a purpose other than display, because it is not used for lcd display. to use the lcd display data memory when t he number of time slices is static, two, three, or four, the lower four bits and higher four bits of each address of the lcd display data memory become an a-pattern area and a b-pattern area, respectively. the correspondences between a-pattern area dat a and com signals are as follows: bit 0 ? com0, bit 1 ? com1, bit 2 ? com2, and bit 3 ? com3. the correspondences between b-pattern area dat a and com signals are as follows: bit 4 ? com0, bit 5 ? com1, bit 6 ? com2, and bit 7 ? com3. a-pattern area data will be displayed on the lcd panel when blon = lcdsel = 0 has been selected, and b-pattern area data will be displayed on the lcd panel when blon = 0 and lcdsel = 1 have been selected. when blon = 1 has been selected, a-pattern and b-pattern areas will be alternately displayed, according to the constant-period interrupt (intrtc) timing of the real-time counter (rtc).
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 678 jun 20, 2011 figure 16-12. example of display data wh en blinking display has been selected b7 b6 b5 b4 b3 b2 b1 b0 com3 com2 com1 com0 com3 com2 com1 com0 f0405h f0404h f0403h f0402h f0401h f0400h seg5 seg4 seg3 seg2 seg1 seg0 a-pattern area b-pattern area when selecting blinking display (blon = 1), a-pattern and b-pattern areas are alternately displayed. 16.5 setting lcd controller/driver set the lcd controller/driver using the following procedure. (1) external resistance division method <1> set the external resistance division method via the mdset0 and mdset1 bits (b its 4 and 5 of the lcdmd register) (mdset0 = mdset1 = 0). <2> to use segment output only pins, use the seg en register to enable segment output to them. to use segment output pins, which ar e alternatively used with port pins, us e the pfall register to set them to segment output. in addition, to use the segment out put pins, which are alter natively used with the ti04, ti02, and rxd3 pins, use the isc register to disable input to the schmitt trigger buffer. <3> set the display data in lcd display ram. <4> set the number of time slices and the bias mode via the lcdm0 to lcdm2 bits (bits 0 to 2 of the lcdm register). ? when setting static, 2-time-slice, 3-time-slice, or 4-time-slice go to step <5> ? when setting 8-time-slice go to step <6> <5> select the display data area via the lcdsel and blon bits (bits 3 and 4 of the lcdm register). <6> set the lcd source clock and lcd clock via the lcdc0 register. <7> set (scoc = 1) the scoc bit (bit 6 of the lcdm register). non-selected waveforms are output from all the s egment and common pins, and t he non-display status is entered. <8> start output corresponding to each data memory by se tting (lcdon = 1) the lcdon bit (bit 7 of the lcdm register).
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 679 jun 20, 2011 (2) internal voltage boosting method <1> set the internal voltage boosting method via the mdset0 and mdset1 bits (bits 4 and 5 of the lcdmd register) (mdset0 = 1, mdset1 = 0). <2> to use segment output only pins, use the segen register to enable segment output to them. to use segment output pins, which ar e alternatively used with port pins, us e the pfall register to set them to segment output. in addition, to use the segment out put pins, which are alter natively used with the ti04, ti02, and rxd3 pins, use the isc register to disable input to the schmitt trigger buffer. <3> set the display data in lcd display ram. <4> set the number of time slices and the bias mode via the lcdm0 to lcdm2 bits (bits 0 to 2 of the lcdm register). ? when setting static, 2-time-slice, 3-time-slice, or 4-time-slice go to step <5> ? when setting 8-time-slice go to step <6> (only 1/3 bias mode and 1/4 bias mode can be set for the internal voltage boost method.) <5> select the display data area via the lcdsel and blon bits (bits 3 and 4 of the lcdm register). <6> set the lcd source clock and lcd clock via the lcdc0 register. <7> set the reference voltage (adjust the contrast) via the vlcd register. <8> wait for the reference voltage setup time (2 ms (min.)) after setting of the vlcd register. <9> set (vlcon = 1) the vlcon bit (bit 5 of the lcdm register) to start the vo ltage boost circuit operation. <10> wait for the voltage boost wait time after setting of vlcon (see chapter 31 electrical specifications ). <11> set (scoc = 1) the scoc bit (bit 6 of the lcdm register). non-selected waveforms are output from all the s egment and common pins, and t he non-display status is entered. <12> start output corresponding to each data memory by se tting (lcdon = 1) the lcdon bit (bit 7 of the lcdm register). caution when stopping the operation of the voltage boost circuit, be sure to set scoc and lcdon to 0 before setting vlcon to 0. (3) capacitor spli t method <1> set the capacitor split method via the mdset0 and mdset1 bits (bit s 4 and 5 of the lcdmd register) (mdset0 = 0, mdset1 = 1). <2> to use segment output only pins, use the segen register to enable segment output to them. to use segment output pins, which ar e alternatively used with port pins, us e the pfall register to set them to segment output. in addition, to use the segment out put pins, which are alter natively used with the ti04, ti02, and rxd3 pins, use the isc register to disable input to the schmitt trigger buffer. <3> set the display data in lcd display ram. <4> set the number of time slices and the bias mode via the lcdm0 to lcdm2 bits (bits 0 to 2 of the lcdm register). (only 1/3 bias mode can be set for the capacitor split method) <5> select the display data area via the lcdsel and blon bits (bits 3 and 4 of the lcdm register). <6> set the lcd source clock and lcd clock via the lcdc0 register. <7> set (vlcon = 1) the vlcon bit (bit 5 of the lcdm register) to start the volt age reduction circuit operation. <8> wait for the voltage capacitor split wait time after setting of vlcon (see chapter 31 electrical specifications ).
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 680 jun 20, 2011 <9> set (scoc = 1) the scoc bit (bit 6 of the lcdm register). non-selected waveforms are output from all the s egment and common pins, and t he non-display status is entered. <10> start output corresponding to each data memory by se tting (lcdon = 1) the lcdon bit (bit 7 of the lcdm register). caution when stopping the operation of the capacitor split circuit, be sure to set scoc and lcdon to 0 before setting vlcon to 0. 16.6 common and segment signals each pixel of the lcd panel turns on when the potentia l difference between the co rresponding common and segment signals becomes higher than a specif ic voltage (lcd drive voltage, v lcd ). the pixels turn off when the potential difference becomes lower than v lcd . applying dc voltage to the common and segm ent signals of an lcd panel causes deter ioration. to avoid this problem, this lcd panel is driven by ac voltage. (1) common signals each common signal is selected sequentially according to a s pecified number of time slic es at the timing listed in table 16-3. in the static display mode, t he same signal is output to com0 to com3. in the two-time-slice mode, leave the com2 and com3 pins open. in the th ree-time-slice mode, leave the com3 pin open. use the com4 to com7 pins other than in t he eight-time-slice mode as open or segment pins. table 16-3. com signals com0 com1 com2 com3 static display mode two-time-slice mode open open open three-time-slice mode four-time-slice mode com signal number of time slices eight-time-slice mode com4 com5 com6 com7 note note note note note note note note note note note note note note note note note use the pins as open or segment pins.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 681 jun 20, 2011 (2) segment signals the segment signals correspond to the lcd display data memory (refer to 16.4 lcd display data memory ). when the number of time slices is eight, bits 0 to 7 of each byte are read in synchronization with com0 to com7, respectively. if a bit is 1, it is converted to the select vo ltage, and if it is 0, it is c onverted to the deselect voltage. the conversion results are output to the segment pins (seg4 to seg53). when the number of time slic es is number other than eight , bits 0 to 3 of each byte in a-pattern area are read in synchronization with com0 to com3, and bits 4 to 7 of each byte in b-pattern area are read in synchronization with com0 to com3, respectively. if a bit is 1, it is convert ed to the select voltage, and if it is 0, it is converted to the deselect voltage. the conver sion results are output to the segment pins (seg0 to seg53). check, with the information given above, what combination of front-surfa ce electrodes (corresponding to the segment signals) and rear-surface el ectrodes (corresponding to the common signals) forms display patterns in the lcd display data memory, and write the bit data that corresponds to t he desired display pattern on a one-to- one basis. lcd display data memory bits 1 to 3, bits 2 and 3, bi t 3, and f0400h to f0403h are not used for lcd display in the static display, two-time slot, th ree-time slot, and eight-time slot modes, respectively. so these bits can be used for purposes other than display. remark the mounted segment output pins vary depending on the product. ? 78k0r/lf3: seg0 to seg30 ? 78k0r/lg3: seg0 to seg39 ? 78k0r/lh3: seg0 to seg53
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 682 jun 20, 2011 (3) output waveforms of common and segment signals the voltages listed in t able 16-4 are output as co mmon and segment signals. when both common and segment signals are at t he select voltage, a display on-voltage of v lcd is obtained. the other combinations of the signals correspond to the display off-voltage. table 16-4. lcd drive voltage (a) static display mode select signal level deselect signal level segment signal common signal v ss /v lc0 v lc0 /v ss v lc0 /v ss ?v lcd /+v lcd 0 v/0 v (b) 1/2 bias method select signal level deselect signal level segment signal common signal v ss /v lc0 v lc0 /v ss select signal level v lc0 /v ss ?v lcd /+v lcd 0 v/0 v deselect signal level v lc1 = v lc2 ? v lcd /+ v lcd + v lcd /? v lcd (c) 1/3 bias method select signal level deselect signal level segment signal common signal v ss /v lc0 v lc1 /v lc2 select signal level v lc0 /v ss ?v lcd /+v lcd ? v lcd /+ v lcd deselect signal level v lc2 /v lc1 ? v lcd /+ v lcd + v lcd /? v lcd (d) 1/4 bias method select signal level deselect signal level segment signal common signal v lc0 /v ss v lc1 /v lc2 select signal level v ss /v lc0 +v lcd /?v lcd + v lcd /? v lcd deselect signal level v lc1 /v lc3 + v lcd /? v lcd ? v lcd /+ v lcd 1 2 1 2 1 2 1 2 1 3 1 3 1 3 1 3 1 4 1 4 1 4 1 4 1 3 1 3 1 2 1 2
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 683 jun 20, 2011 figure 16-13 shows the common signal waveforms, and figur e 16-14 shows the voltages and phases of the common and segment signals. figure 16-13. common signal waveforms (1/2) (a) static display mode comn (static display) t f = t v lc0 v ss v lcd t: one lcd clock period t f : frame frequency (b) 1/2 bias method comn (two-time slot mode) t f = 2 t v lc0 v ss v lcd v lc2 comn (three-time slot mode) t f = 3 t v lc0 v ss v lcd v lc2 t: one lcd clock period t f : frame frequency
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 684 jun 20, 2011 figure 16-13. common signal waveforms (2/2) (c) 1/3 bias method comn (three-time slot mode) t f = 3 t v lc0 v ss v lcd v lc1 v lc2 t f = 4 t comn (four-time slot mode) v lc0 v lcd v lc1 v lc2 v ss t: one lcd clock period t f : frame frequency < example of calculation of lcd frame fr equency (when four-time slot mode is used) > lcd clock: 32768/2 8 = 256 hz (when setting to lcdc0 = 04h) lcd frame frequency: 64 hz (d) 1/4 bias method comn v lc1 v lc0 v ss v lcd v lc2 v lc3 t f = 8 t (eight-time slot mode) t: one lcd clock period t f : frame frequency < example of calculation of lcd frame frequen cy (when eight-time slot mode is used) > lcd clock: 32768/2 8 = 256 hz (when setting to lcdc0 = 04h) lcd frame frequency: 32 hz
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 685 jun 20, 2011 figure 16-14. voltages and phases of common and segmen t signals (1/2) (a) static display mode select deselect common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt t: one lcd clock period (b) 1/2 bias method select deselect common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt v lc2 v lc2 t: one lcd clock period
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 686 jun 20, 2011 figure 16-14. voltages and phases of common and segmen t signals (2/2) (c) 1/3 bias method select deselect common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt v lc2 v lc2 v lc1 v lc1 t: one lcd clock period (d) 1/4 bias method v lc1 v lc0 v ss v lcd v lc0 v lc3 v lcd v lc3 v lc2 v lc2 v lc1 v ss t t t t select deselect common signal segment signal t: one lcd clock period
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 687 jun 20, 2011 16.7 display modes 16.7.1 static display example figure 16-16 shows how the three-digit lcd panel having the display pattern shown in figure 16-15 is connected to the segment signals (seg0 to seg23) and the common signal (com0). this exam ple displays data "12.3" in the lcd panel. the contents of the disp lay data memory (f0400h to f0417h) correspond to this display. the following description focuses on numeral "2." ( ) displa yed in the second digit. to display "2." in the lcd panel, it is necessary to apply the select or deselect voltage to t he seg8 to seg15 pins according to table 16-5 at the timing of the common signal com0; see figure 16-15 for the rela tionship between the segment signals and lcd segments. table 16-5. select and deselect voltages (com0) seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 segment common com0 select deselect select select deselect select select select according to table 16-5, it is dete rmined that the bit-0 pattern of the di splay data memory locations (f0408h to f040fh) must be 10110111. figure 16-17 shows the lcd drive wave forms of seg11 and seg12, and com0. when the select voltage is applied to seg11 at the timing of com0, an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. com1 to com3 are supplied with the same waveform as for com0. so, com0 to com3 may be connected together to increase the driving capacity. figure 16-15. static lcd display pattern and electrode connections seg 8n+3 seg 8n+2 seg 8n+5 seg 8n+1 seg 8n seg 8n+4 seg 8n+6 seg 8n+7 com0 remark 78k0r/lf3: n = 0 to 3 78k0r/lg3: n = 0 to 4 78k0r/lh3: n = 0 to 5
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 688 jun 20, 2011 figure 16-16. example of connecting static lcd panel 000001101110110110101110 bit 0 bit 2 bit 1 bit 3 timing strobe data memory address lcd panel f0400h 1 2 3 4 5 6 7 8 9 a b c d e f f0410h 1 2 3 4 5 6 7 seg 0 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 com 3 com 2 com 1 com 0 can be connected together
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 689 jun 20, 2011 figure 16-17. static l cd drive waveform examples t f v lc0 v ss com0 v lc0 v ss seg11 v lc0 v ss seg12 +v lcd 0 com0-seg12 - v lcd +v lcd 0 com0-seg11 - v lcd
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 690 jun 20, 2011 16.7.2 two-time-s lice display example figure 16-19 shows how the 6-digit lcd panel having the disp lay pattern shown in figure 16-18 is connected to the segment signals (seg0 to seg23) and the common signals (com 0 and com1). this example displays data "12345.6" in the lcd panel. the contents of the display data memory (f0400h to f 0417h) correspond to this display. the following description focuses on numeral "3" ( ) display ed in the fourth digit. to display "3" in the lcd panel, it is necessary to apply the select or des elect voltage to the seg12 to seg15 pins a ccording to table 16-6 at the timing of the common signals com0 and com1; see figure 16-18 for the relationship between t he segment signals and lcd segments. table 16-6. select and desel ect voltages (com0 and com1) seg12 seg13 seg14 seg15 segment common com0 select select deselect deselect com1 deselect select select select according to table 16-6, it is dete rmined that the display data memory loca tion (f040fh) that corresponds to seg15 must contain xx10. figure 16-20 shows examples of lcd drive waveforms between the seg15 signal and each common signal. when the select voltage is applied to seg15 at the timing of com1, an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. figure 16-18. two-time-slice lcd displ ay pattern and electrode connections seg 4n+2 seg 4n+3 seg 4n+1 seg 4n com0 com1 remark 78k0r/lf3: n = 0 to 6 78k0r/lg3: n = 0 to 9 78k0r/lh3: n = 0 to 12
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 691 jun 20, 2011 figure 16-19. example of connecting two-time-slice lcd panel 001110100011011101011101 000011101110001011111110 bit 3 bit 2 bit 1 bit 0 timing strobe data memory address lcd panel f0400h 1 2 3 4 5 6 7 8 9 a b c d e f f0410h 1 2 3 4 5 6 7 seg 0 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 com 3 com 2 com 1 com 0 open open : can always be used to store any data bec ause the two-time-slice mode is being used.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 692 jun 20, 2011 figure 16-20. two-time-slice lcd dri ve waveform examples (1/2 bias method) t f v lc0 v ss com0 v lc0 v ss v lc0 v ss seg15 +v lcd 0 com1-seg15 - v lcd +v lcd 0 com0-seg15 - v lcd v lc1,2 v lc1,2 v lc1,2 com1 +1/2v lcd +1/2v lcd - 1/2v lcd - 1/2v lcd
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 693 jun 20, 2011 16.7.3 three-time-s lice display example figure 16-22 shows how the 8-digit lcd panel having the disp lay pattern shown in figure 16-21 is connected to the segment signals (seg0 to seg23) and the common signals (com 0 to com2). this example displays data "123456.78" in the lcd panel. the contents of the display data memory (addresses f0400h to f0417h) correspond to this display. the following description focuses on numeral "6." ( ) displa yed in the third digit. to display "6." in the lcd panel, it is necessary to apply the select or desel ect voltage to the seg6 to seg8 pins accord ing to table 16-7 at the timing of the common signals com0 to com2; see figure 16-21 for the re lationship between the segment signals and lcd segments. table 16-7. select and desel ect voltages (com0 to com2) seg6 seg7 seg8 segment common com0 deselect select select com1 select select select com2 select select ? according to table 16-7, it is dete rmined that the display data memory lo cation (f0406h) that corresponds to seg6 must contain x110. figures 16-23 and 16-24 show examples of lcd drive waveforms between the seg6 signal and each common signal in the 1/2 and 1/3 bias methods, respective ly. when the select voltage is applied to seg6 at the timing of com1 or com2, an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. figure 16-21. three-time-slice lcd displ ay pattern and electrode connections seg 3n+2 seg 3n com0 com2 seg 3n+1 com1 remark 78k0r/lf3: n = 0 to 9 78k0r/lg3: n = 0 to 12 78k0r/lh3: n = 0 to 17
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 694 jun 20, 2011 figure 16-22. example of conn ecting three-time-slice lcd panel 001011011101110110111111 bit 0 001110011011011111001111 bit 1 bit 3 timing strobe data memory address lcd panel 1 2 3 4 5 6 7 8 9 a b c d e f 1 2 3 4 5 6 7 seg 0 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 com 3 com 2 com 1 com 0 open 00 10 10 00 10 11 00 10 bit 2 x? x? x? x? x? x? x? x? f0400h f0410h ?: can be used to store any data because there is no corres ponding segment in the lcd panel. : can always be used to store any data becaus e the three-time-slice mode is being used.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 695 jun 20, 2011 figure 16-23. three-time-slice lcd dri ve waveform examples (1/2 bias method) t f v lc0 v ss com0 v lc0 v ss v lc0 v ss com2 +v lcd 0 com1-seg6 - v lcd +v lcd 0 com0-seg6 - v lcd v lc1,2 v lc1,2 v lc1,2 com1 +1/2v lcd +1/2v lcd - 1/2v lcd - 1/2v lcd v lc0 v ss seg6 v lc1,2 +v lcd 0 com2-seg6 - v lcd +1/2v lcd - 1/2v lcd
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 696 jun 20, 2011 figure 16-24. three-time-slice lcd dri ve waveform examples (1/3 bias method) v lc0 v lc2 com0 +v lcd 0 com0-seg6 - v lcd v lc1 +1/3v lcd - 1/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 seg6 v lc1 v ss +v lcd 0 com1-seg6 - v lcd +1/3v lcd - 1/3v lcd +v lcd 0 com2-seg6 - v lcd +1/3v lcd - 1/3v lcd t f
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 697 jun 20, 2011 16.7.4 four-time-sli ce display example figure 16-26 shows how the 12-digit lcd panel having the disp lay pattern shown in figure 16-25 is connected to the segment signals (seg0 to seg23) and the common signals (com0 to com3). this example displays data "123456.789012" in the lcd panel. the cont ents of the display data memory ( addresses f0400h to f0417h) correspond to this display. the following description focuses on numeral "6." ( ) displa yed in the seventh digit. to display "6." in the lcd panel, it is necessary to apply the select or deselect voltage to the seg12 and seg13 pins according to table 16-8 at the timing of the common signals com0 to com3; see figure 16-25 for the relationship between the segment signals and lcd segments. table 16-8. select and desel ect voltages (com0 to com3) seg12 seg13 segment common com0 select select com1 deselect select com2 select select com3 select select according to table 16-8, it is dete rmined that the display data memory loca tion (f040ch) that corresponds to seg12 must contain 1101. figure 16-27 shows examples of lcd drive waveforms between the seg12 signal and each common signal. when the select voltage is applied to seg12 at the timing of com0, an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. figure 16-25. four-time-slice lcd displ ay pattern and electrode connections com0 seg 2n com1 seg 2n+1 com2 com3 remark 78k0r/lf3: n = 0 to 14 78k0r/lg3: n = 0 to 19 78k0r/lh3: n = 0 to 26
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 698 jun 20, 2011 figure 16-26. example of connecting four-time-slice lcd panel 000101101111111111110001 011111111010011111010111 011001010111011101110110 001010001011001000100010 bit 3 bit 2 bit 1 bit 0 timing strobe data memory address lcd panel 1 2 3 4 5 6 7 8 9 a b c d e f 1 2 3 4 5 6 7 seg 0 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 com 3 com 2 com 1 com 0 f0400h f0410h
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 699 jun 20, 2011 figure 16-27. four-time-slice lcd dri ve waveform examples (1/3 bias method) v lc0 v lc2 com0 +v lcd 0 com0-seg12 - v lcd v lc1 +1/3v lcd - 1/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 com3 v lc1 v ss +v lcd 0 com1-seg12 - v lcd +1/3v lcd - 1/3v lcd v lc0 v lc2 seg12 v lc1 v ss t f remark the waveforms for com2-seg12 and com3-seg12 are omitted.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 700 jun 20, 2011 16.7.5 eight-time-s lice display example figure 16-29 shows how the 15x8 dot lcd panel having the display pattern shown in figure 16-28 is connected to the segment signals (seg4 to seg18) and the common signals (com0 to com7). this example displays data "123" in the lcd panel. the contents of the displa y data memory (addresses f0404h to f0412h) correspond to this display. the following description focuses on numeral "3." ( ) display ed in the first digit. to display "3." in the lcd panel, it is necessary to apply the select or deselec t voltage to the seg4 to seg8 pins accord ing to table 16-8 at the timing of the common signals com0 to com7; see figure 16-28 for the re lationship between the segment signals and lcd segments. table 16-9. select and desel ect voltages (com0 to com7) seg4 seg5 seg6 seg7 seg8 segment common com0 select select select select select com1 deselect select deselect deselect deselect com2 deselect deselect select deselect deselect com3 deselect select deselect deselect deselect com4 select deselect deselect deselect deselect com5 select deselect deselect deselect select com6 deselect select select select deselect com7 deselect deselect de select deselect deselect according to table 16-9, it is dete rmined that the display data memory lo cation (f0404h) that corresponds to seg4 must contain 00110001. figure 16-30 shows examples of lcd drive waveforms between the seg4 signal and each common signal. when the select voltage is applied to seg4 at the timing of com0, a waveform is gener ated to turn on the corresponding lcd segment. figure 18-28. eight-time-s lice lcd display pattern a nd electrode connections com0 com1 com2 com3 com4 com5 com6 com7 sssss eeeee ggggg n+4 n+3 n+2 n+1 n remark 78k0r/lf3: n = 4 to 26 78k0r/lg3: n = 4 to 35 78k0r/lh3: n = 4 to 49
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 701 jun 20, 2011 figure 18-29. example of connect ing eight-time-slice lcd panel 001000111011111 011001000100010 bit 3 bit 2 bit 1 bit 0 timing strobe data memory address lcd panel bit 5 bit 4 bit 7 bit 6 f0404h 5 6 7 8 9 a b c d e f f0410h 1 2 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 com 3 com 2 com 1 com 0 com 7 com 6 com 5 com 4 001000010000001 001000100010001 001000000100100 001000001000010 011101111101110 000000000000000 seg 15 seg 16 seg 17 seg 18
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 702 jun 20, 2011 figure 16-30. eight-time-slice lcd dri ve waveform examples (1/4 bias method) v lc0 v lc2 v lc3 com0 +v lcd 0 - v lcd v lc1 +1/2v lcd - 1/2v lcd v ss +v lcd 0 - v lcd +1/4v lcd - 1/4v lcd t f v lc0 v lc2 v lc3 com1 v lc1 v ss v lc0 v lc2 v lc3 com2 v lc1 v ss v lc0 v lc2 v lc3 v lc1 v ss v lc0 v lc2 v lc3 com7 v lc1 v ss . . . . . . . . +1/4v lcd - 1/4v lcd +1/2v lcd - 1/2v lcd com0-seg4 seg4 com1-seg4 remark the waveforms for com3 to com6, co m2-seg4 to com7-seg4 are omitted.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 703 jun 20, 2011 16.8 supplying lcd drive voltages v lc0 , v lc1 , v lc2, and v lc3 with the 78k0r/lx3 microcontrollers, a lcd drive power supply can be generated using ei ther of three types of methods: external resistance division method, internal voltage boosting method, or capacitor split method. 16.8.1 external resi stance division method the 78k0r/lx3 microcontrollers can also use external voltage divider resistors fo r generating lcd drive power supplies, without using internal resistor s. figure 16-31 shows examples of l cd drive voltage connection, corresponding to each bias method. figure 16-31. examples of lcd dr ive power connections (external resistance division method) (1/2) (a) static display mode (b) 1/2 bias method v lc0 v lc0 v lc1 v lc2 v ss v dd v ss v lc1 note1 v lc2 note1 v lc3 v lc3 /p02 note2 v lc0 = v dd v lc0 v lc0 v lc1 v lc2 v ss v dd v ss v lc1 v lc2 v lc3 r r v lc0 = v dd v lc3 / p02 note notes 1. connect v lc1 and v lc2 directly to gnd or v lc0 . 2. v lc3 can be used as port (p02). note v lc3 can be used as port (p02). caution to stabilize the potential of the v lc0 to v lc3 pins, it is recommended to connect a capacitor of about 0.1 f between each of the pins from v lc0 to v lc3 and the gnd pin as needed.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 704 jun 20, 2011 figure 16-31. examples of lcd dr ive power connections (external resistance division method) (2/2) (c) 1/3 bias method (d) 1/4 bias method v lc0 v lc0 v lc1 v lc2 v ss v dd v ss v lc1 v lc2 r r v lc0 = v dd r v lc3 v lc3 / p02 note v lc0 v lc0 v lc1 v lc2 v ss v dd v ss v lc1 v lc2 r r v lc0 = v dd r v lc3 v lc3 r note v lc3 can be used as port (p02). caution to stabilize the potential of the v lc0 to v lc3 pins, it is recommended to connect a capacitor of about 0.1 f between each of the pins from v lc0 to v lc3 and the gnd pin as needed. 16.8.2 internal voltage boosting method the 78k0r/lx3 microcontrollers contain an internal voltage boost circuit for generat ing lcd drive power supplies. the internal voltage boost circuit and external capacitors (0.47 f 30%) are used to generate an lcd drive voltage. only 1/3 bias mode or 1/4 bias mode can be se t for the internal voltage boost method. the lcd drive voltage of the internal voltage boost method can supply a c onstant voltage, regar dless of changes in v dd , because it is a power supply separate from the main unit. in addition, a contrast can be adjusted by usi ng the lcd boost level control register (vlcd). table 16-10. lcd drive voltages (i nternal voltage boosting method) 1/3 bias method 1/4 bias method bias method lcd drive voltage pin v lc0 3 x v lc2 4 x v lc3 v lc1 2 x v lc2 3 x v lc3 v lc2 lcd reference voltage 2 x v lc3 v lc3 ? lcd reference voltage
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 705 jun 20, 2011 figure 16-32. examples of lcd drive power conn ections (internal voltage boosting method) (a) 1/3 bias method (b) 1/4 bias method v lc0 v dd v lc1 v lc2 c3 c2 c4 2xv lc2 3xv lc2 caph capl c1 v lc3 /p02 note internal reference voltage generator drive voltage generator v lc0 v dd v lc1 v lc2 c3 c2 c4 caph capl c1 v lc3 4xv lc3 c5 2xv lc3 3xv lc3 internal reference voltage generator drive voltage generator note v lc3 can be used as port (p02). remark use a capacitor with as little leakage as possible. in addition, make c1 a nonpolar capacitor. remark use a capacitor with as little leakage as possible. in addition, make c1 a nonpolar capacitor. 16.8.3 capacitor split method the 78k0r/lx3 microcontrollers contain an internal voltage reduction circuit for generating lcd drive power supplies. the internal voltage reduction circ uit and external capacitors (0.47 f 30%) are used to generate an lcd drive voltage. only 1/3 bias mode can be set for the capacitor split method. different from the external resistance di vision method, there is always no current flowing with the capac itor split method, so current consumption can be reduced. table 16-11. lcd drive volt ages (capacitor split method) 1/3 bias method bias method lcd drive voltage pin v lc0 v dd v lc1 2/3 x v dd v lc2 1/3 x v dd v lc3 ?
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 706 jun 20, 2011 figure 16-33. examples of lcd drive power c onnections (internal voltage boosting method) ? 1/3 bias method v lc0 v dd v lc1 v lc2 c2 c3 1/3 x v dd 2/3 x v dd caph capl c1 v lc3 /p02 note drive voltage generator v dd note v lc3 can be used as port (p02). remark use a capacitor with as little leakage as possible. in addition, make c1 a nonpolar capacitor. 16.9 selection of lcd display data with the 78k0r/lx3 microcontroller, to use the lcd display dat a memory when the number of ti me slices is static, two, three, or four, the lcd display data c an be selected from the following three types, according to the blon and lcdsel bit settings. ? displaying an a-pattern area data (lower four bits of lcd display data memory) ? displaying a b-pattern area data (higher four bits of lcd display data memory) ? alternately displaying a-pattern and b-pattern area data (blin king display corresponding to t he constant-period interrupt timing of the real-time counter (rtc)) caution when the lcd display data me mory is used when the number of ti me slices is eight, lcd display data (a-pattern, b-pattern, or blinki ng display) cannot be selected. 16.9.1 a-pattern area and b- pattern area data display when blon = lcdsel = 0, a-pattern area (lower four bits of the lcd display data me mory) data will be output as the lcd display data. when blon = 0, and lcdsel = 1, b-pattern area (higher four bits of the lcd di splay data memory) data will be output as the lcd display data. refer to 16.4 lcd display data memory about the display area.
78k0r/lx3 chapter 16 lcd controller/driver r01uh0004ej0501 rev.5.01 707 jun 20, 2011 16.9.2 blinking display (alternately disp laying a-pattern and b-pattern area data) when blon = 1 has been set, a-pattern and b-pattern area data will be alternately displayed, according to the constant-period interrupt (int rtc) timing of the real-time counter (rtc). refer to chapter 7 real-time counter about the setting of the rt c constant-period inte rrupt (intrtc) timing. for blinking display of the lcd, set inverted values to the b-pattern area bits corresponding to the a-pattern area bits. (example: set 1 to bit 0 of 00h, and set 0 to bit 4 of f0400h for blinking display.) when not setting blinking display of the lcd, set the same values. (example: set 1 to bit 2 of f0402h, and set 1 to bit 6 of f0402h for lighting display.) figure 16-34. example of l cd display data setting duri ng pattern-switching display b7 b6 b5 b4 b3 b2 b1 b0 com3 com2 com1 com0 com3 com2 com1 com0 f0405h f0404h f0403h f0402h f0401h f0400h seg5 seg4 seg3 seg2 seg1 seg0 a-pattern area b-pattern area set 1 for lighting display. set inverted value for blinking display. refer to 16.4 lcd display data memory about the display area. next, the timing operation of display switching is shown. figure 16-35. switching operation from a-pattern display to blinking display blon, lcdsel bits segment display rtc constant-period interrupt (intrtc) blon = 0, lcdsel = 0 blon = 1, lcdsel = 0 or 1 a-pattern a- pattern b-pattern a-pattern b-pattern blinking display always starts from an a pattern. figure 16-36. switching operation from blinking display to a-pattern display blon = 0, lcdsel = 0 blon = 1, lcdsel = 0 or 1 a-pattern b-pattern a-pattern b -pattern rtc constant-period interrupt (intrtc) blon, lcdsel bits segment display
78k0r/lx3 chapter 17 multiplier/divider r01uh0004ej0501 rev.5.01 708 jun 20, 2011 chapter 17 multiplier/divider 17.1 functions of multiplier/divider the multiplier/divider is mounted onto all 78k0r/lx3 microcontroller products. the multiplier/divider has the following functions. ? 16 bits 16 bits = 32 bits (multiplication) ? 32 bits 32 bits = 32 bits, 32-bit remainder (division) 17.2 configuration of multiplier/divider the multiplier/divider consis ts of the following hardware. table 17-1. configuration of multiplier/divider item configuration registers multiplication/division data register a (l) (mdal) multiplication/division data register a (h) (mdah) multiplication/division data register b (l) (mdbl) multiplication/division data register b (h) (mdbh) multiplication/division dat a register c (l) (mdcl) multiplication/division data register c (h) (mdch) control register multiplication/division control register (mduc) figure 17-1 shows a block diagram of the multiplier/divider.
78k0r/lx3 chapter 17 multiplier/divider r01uh0004ej0501 rev.5.01 709 jun 20, 2011 figure 17-1. block diagram of multiplier/divider internal bus f prs multiplication result (product) division result (remainder) division result (quotient) multiplier dividend divisor multiplicand multiplication/division data register c mdch mdcl counter data flow during division data flow during multiplication divmode multiplication/division control register (mduc) controller controller controller divst intmd clear start multiplication/division data register a mdah mdal multiplication/division data register b mdbh mdbl multiplication/division block
78k0r/lx3 chapter 17 multiplier/divider r01uh0004ej0501 rev.5.01 710 jun 20, 2011 (1) multiplication/division data register a (mdah, mdal) the mdah and mdal registers set the va lues that are used for a multiplicati on or division operation and store the operation result. they set the multiplier and multiplic and data in the multiplication mode, and set the dividend data in the division mode. furthermore, the operation result ( quotient) is stored in the mdah and mdal registers in the division mode. mdah and mdal can be set by a 16-bit manipulation instruction. reset signal generation clears these registers to 0000h. figure 17-2. format of multiplication/ division data register a (mdah, mdal) ffff3h ffff2h mdah mdah 15 mdah 14 mdah 13 mdah 12 mdah 11 mdah 10 mdah 9 mdah 8 mdah 7 mdah 6 mdah 5 mdah 4 mdah 3 mdah 2 mdah 1 mdah 0 ffff1h ffff0h mdal mdal 15 mdal 14 mdal 13 mdal 12 mdal 11 mdal 10 mdal 9 mdal 8 mdal 7 mdal 6 mdal 5 mdal 4 mdal 3 mdal 2 mdal 1 mdal 0 address: ffff0h, ffff1h, ffff2h, ffff3h after reset: 0000h, 0000h r/w symbol symbol cautions 1. do not rewrite the mdah and mdal va lues during division operat ion processing (while the multiplication/division control re gister (mduc) is 81h). the opera tion will be executed in this case, but the operation result w ill be an undefined value. 2. the mdah and mdal values read during divi sion operation processing (while mduc is 81h) will not be guaranteed. the following table shows the functions of md ah and mdal during operation execution. table 17-2. functions of mdah and mdal during operation execution divmode operation mode setting operation result 0 multiplication mode mdah: multiplier mdal: multiplicand ? 1 division mode mdah: divisor (higher 16 bits) mdal: dividend (lower 16 bits) mdah: division result (quotient) higher 16 bits mdal: division result (quotient) lower 16 bits remark divmode: bit 7 of the multiplica tion/division control register (mduc)
78k0r/lx3 chapter 17 multiplier/divider r01uh0004ej0501 rev.5.01 711 jun 20, 2011 (2) multiplication/division data register b (mdbl, mdbh) the mdbh and mdbl registers set the values that are us ed for multiplication or division operation and store the operation result. they store the operation result (product) in the multiplication mode and set the divisor data in the division mode. mdbh and mdbl can be set by a 16-bit manipulation instruction. reset signal generation clears these registers to 0000h. figure 17-3. format of multiplication/ division data register b (mdbh, mdbl) address: ffff4h, ffff5h, ffff6h, ffff7h after reset: 0000h, 0000h r/w symbol ffff7h ffff6h mdbh mdbh 15 mdbh 14 mdbh 13 mdbh 12 mdbh 11 mdbh 10 mdbh 9 mdbh 8 mdbh 7 mdbh 6 mdbh 5 mdbh 4 mdbh 3 mdbh 2 mdbh 1 mdbh 0 symbol ffff5h ffff4h mdbl mdbl 15 mdbl 14 mdbl 13 mdbl 12 mdbl 11 mdbl 10 mdbl 9 mdbl 8 mdbl 7 mdbl 6 mdbl 5 mdbl 4 mdbhl 3 mdbl 2 mdbl 1 mdbl 0 cautions 1. do not rewrite the mdbh and mdbl va lues during division operati on processing (while the multiplication/division control register (mduc) is 81h). the operation result will be an undefined value. 2. do not set mdbh and mdbl to 0000h in the division mode. if they are set, the operation result will be an undefined value. the following table shows the functions of md bh and mdbl during operation execution. table 17-3. functions of mdbh a nd mdbl during operation execution divmode operation mode setting operation result 0 multiplication mode ? mdbh: multiplication result (product) higher 16 bits mdbl: multiplication result (product) lower 16 bits 1 division mode mdbh: divisor (higher 16 bits) mdbl: dividend (lower 16 bits) ? remark divmode: bit 7 of the multiplica tion/division control register (mduc)
78k0r/lx3 chapter 17 multiplier/divider r01uh0004ej0501 rev.5.01 712 jun 20, 2011 (3) multiplication/division data register c (mdcl, mdch) the mdch and mdcl registers store rema inder value of the operation result in the division mode. they are not used in the multiplication mode. mdch and mdcl can be read by a 16-bit manipulation instruction. reset signal generation clears these registers to 0000h. figure 17-4. format of multiplication/ division data register c (mdch, mdcl) address: f00e0h, f00e1h, f00e2h, f00e3h after reset: 0000h, 0000h r f00e3h f00e2h mdch mdch 15 mdch 14 mdch 13 mdch 12 mdch 11 mdch 10 mdch 9 mdch 8 mdch 7 mdch 6 mdch 5 mdch 4 mdch 3 mdch 2 mdch 1 mdch 0 f00e1h f00e0h mdcl mdcl 15 mdcl 14 mdcl 13 mdcl 12 mdcl 11 mdcl 10 mdcl 9 mdcl 8 mdcl 7 mdcl 6 mdcl 5 mdcl 4 mdcl 3 mdcl 2 mdcl 1 mdcl 0 symbol symbol caution the mdch and mdcl values read during division operation pr ocessing (while the multiplication/division control register (mduc) is 81h) will not be guaranteed. table 17-4. functions of mdch a nd mdcl during operation execution divmode operation mode setting operation result 0 multiplication mode ? ? 1 division mode ? mdch: remainder (higher 16 bits) mdcl: remainder (lower 16 bits) remark divmode: bit 7 of the multiplica tion/division control register (mduc) the register configuration differs betwe en when multiplication is executed and when division is executed, as follows. ? register configuration during multiplication mdal (bits 15 to 0) mdah (bits 15 to 0) = [mdbh (bits 15 to 0), mdbl (bits 15 to 0)] ? register configuration during division [mdah (bits 15 to 0), mdal (bits 15 to 0)] [mdbh (bits 15 to 0), mdbl (bits 15 to 0)] = [mdah (bits 15 to 0), mdal (bits 15 to 0)] ??? [mdch (bits 15 to 0), mdcl (bits 15 to 0)]
78k0r/lx3 chapter 17 multiplier/divider r01uh0004ej0501 rev.5.01 713 jun 20, 2011 17.3 register controlling multiplier/divider the multiplier/divider is controlled by using t he multiplication/division control register (mduc). (1) multiplication/division control register (mduc) mduc is an 8-bit register that controls the operation of the multiplier/divider. mduc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 17-5. format of multiplicatio n/division control register (mduc) address: f00e8h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 <0> mduc divmode 0 0 0 0 0 0 divst divmode operation mode (multi plication/division) selection 0 multiplication mode 1 division mode divst note division operation start/stop 0 division operation processing complete 1 starts division operation/divisi on operation processing in progress note divst can only be set (1) in the division mode. in the division mode, division operation is started by setting (1) divst. divst is automatically cleared (0) when the operation ends. in the multiplication mode, operation is automatically started by setting the multiplier and multiplicand to mdah and mdal, respectively. cautions 1. do not rewrite divmode during operation processing (while divst is 1). if it is rewritten, the operation result will be an undefined value. 2. divst cannot be cleared (0) by using softw are during division opera tion processing (while divst is 1).
78k0r/lx3 chapter 17 multiplier/divider r01uh0004ej0501 rev.5.01 714 jun 20, 2011 17.4 operations of multiplier/divider 17.4.1 multiplication operation ? initial setting <1> set bit 7 (divmode) of the multiplicati on/division control register (mduc) to 0. <2> set the multiplicand to the multiplicat ion/division data register a (l) (mdal). <3> set the multiplier to the multiplicat ion/division data register a (h) (mdah). (there is no preference in the order of executing steps <2> and <3>. multip lication operation is automatically started when the multiplier and multiplicand are set to mdah and mdal, respectively.) ? during operation processing <4> wait for at least one clock. the operation will end when one clock has been issued. ? operation end <5> read the product (lower 16 bits) from the mu ltiplication/division data register b (l) (mdbl). <6> read the product (higher 16 bits) from the mult iplication/division data register b (h) (mdbh). (there is no preference in the order of executing steps <5> and <6>.) ? next operation <7> to execute multiplication operation next, start from the ?initial setting? for multiplication operation. <8> to execute division operation next, start from the ?initial setting? in 17.4.2 division operation . remark steps <1> to <7> correspond to <1> to <7> in figure 17-6 . figure 17-6. timing diagram of multiplication operation (0003h 0002h) mdah 0003h 0002h 0006h ffffh ffffh fffe000h 1fffeh initial value = 0 initial value = 0 initial value = 0 mdal mdbh divmode operation clock "0" <1> <2> <4> <3> <7> <5>, <6>
78k0r/lx3 chapter 17 multiplier/divider r01uh0004ej0501 rev.5.01 715 jun 20, 2011 17.4.2 division operation ? initial setting <1> set bit 7 (divmode) of the multiplicati on/division control register (mduc) to 1. <2> set the dividend (higher 16 bits) to the mu ltiplication/division data register a (h) (mdah). <3> set the dividend (lower 16 bits) to the mu ltiplication/division data register a (l) (mdal). <4> set the divisor (higher 16 bits) to the mult iplication/division data register b (h) (mdbh). <5> set the divisor (lower 16 bits) to the multip lication/division data register b (l) (mdbl). <6> set bit 0 (divst) of mduc to 1. (there is no preference in the order of executing steps <2> to <5>.) ? during operation processing <7> the operation will end when one of the following processing is completed. ? a wait of at least 16 clocks (the operat ion will end when 16 clocks have been issued.) ? a check whether divst has been cleared ? generation of a division completion interrupt (intmd) (the read values of mdbl, mdbh, mdch, and mdcl during operation processing are not guaranteed.) ? operation end <8> divst is cleared (0) and an interrupt request si gnal (intmd) is generated (end of operation). <9> read the quotient (lower 16 bits) from mdal. <10> read the quotient (higher 16 bits) from mdah. <11> read the remainder (lower 16 bits) from mu ltiplication/division data register c (l) (mdcl). <12> read the remainder (higher 16 bits) from the multiplication/division data register c (h) (mdch). (there is no preference in the order of executing steps <9> to <12>.) ? next operation <13> to execute multiplication operation ne xt, start from the ?initial setting? in 17.4.1 multiplication operation . <14> to execute division operation next, start from the ?initial setting? for division operation. remark steps <1> to <12> corresp ond to <1> to <12> in figure 17-7 .
78k0r/lx3 chapter 17 multiplier/divider r01uh0004ej0501 rev.5.01 716 jun 20, 2011 figure 17-7. timing diagram of division operation (example: 35 6 = 5, remainder 5) mdah, mdal 0000 008c 0000 0000 0000 0000 0000 0000 0000 0006 xxxx xxxx 0000 0230 0000 08c0 0000 2300 0000 8c00 0002 3000 0008 c000 0023 0000 008c 0000 0230 0000 08c0 0000 2300 0000 8c00 0000 3000 0000 c000 0001 0000 0002 0000 0002 0000 0005 0000 0005 divmode operation clock divst counter undefined intmd mdbh, mdbl xxxx xxxx mdch, mdcl xxxx xxxx 123456 <1> <2> <3> 789 a b c de f 0 0 0000 0023 <4> <5> <6> <7> <9>, <10> <11>, <12> <8> <8>
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 717 jun 20, 2011 chapter 18 dma controller the dma (direct memory access) controller is mounted onto all 78k0r/lx3 microcontroller products. data can be automatically transferred between the peripheral hardware supporting dma, sfrs, and internal ram without via cpu. as a result, the normal internal operation of the cpu a nd data transfer can be executed in parallel with transfer between the sfr and internal ram, and ther efore, a large capacity of data can be processed. in addition, real-time control using communication, timer, and a/d can also be realized. 18.1 functions of dma controller { number of dma channels: 2 { transfer unit: 8 or 16 bits { maximum transfer unit: 1024 times { transfer type: 2-cycle transfer (one transfer is proc essed in 2 clocks and the cpu stops during that processing.) { transfer mode: single-transfer mode { transfer target: between sfr and internal ram { transfer request: selectable from the following peripheral hardware interrupts 78k0r/lf3 ( pd78f150na: n = 0 to 2) 78k0r/lg3 ( pd78f150na: n = 3 to 5) 78k0r/lh3 ( pd78f150na: n = 6 to 8) peripheral hardware 80 pins 100 pins 128 pins channel 0 channel 1 channel 4 timer array unit 0 channel 5 csi00 ? csi01 ? ? csi10 uart0 ? uart1 serial array unit 0 iic10 serial array unit 1 uart3 a/d converter : supported, ? : not supported
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 718 jun 20, 2011 here are examples of functions using dma. ? successive transfer of serial interface ? batch transfer of analog data ? capturing a/d conversion result at fixed interval ? capturing port value at fixed interval 18.2 configuration of dma controller the dma controller includes the following hardware. table 18-1. configuration of dma controller item configuration address registers ? dma sfr address registers 0, 1 (dsa0, dsa1) ? dma ram address regist ers 0, 1 (dra0, dra1) count register ? dma byte count registers 0, 1 (dbc0, dbc1) control registers ? dma mode control registers 0, 1 (dmc0, dmc1) ? dma operation control registers 0, 1 (drc0, drc1) (1) dma sfr address register n (dsan) this is an 8-bit register that is used to set an sfr address that is the transfer source or destination of dma channel n. set the lower 8 bits of t he sfr addresses fff00h to fffffh note . this register is not automatically incr emented but fixed to a specific value. in the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address. dsan can be read or written in 8-bit units. however, it cannot be written during dma transfer. reset signal generation clears this register to 00h. note except for address ffffeh because the pmc register is allocated there. figure 18-1. format of dma sfr address register n (dsan) address: fffb0h (dsa0), fffb1h (dsa1) after reset: 00h r/w 7 6 5 4 3 2 1 0 dsan remark n: dma channel number (n = 0, 1)
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 719 jun 20, 2011 (2) dma ram address register n (dran) this is a 16-bit register that is used to set a ram a ddress that is the transfer s ource or destination of dma channel n. addresses of the internal ram area ot her than the general-purpose registers (fef00h to ffedfh in the case of the pd78f1500a, 78f1503a, and 78f1506a) can be set to this register. set the lower 16 bits of the ram address. this register is automatically increm ented when dma transfer has been started. it is incremented by +1 in the 8- bit transfer mode and by +2 in the 16-bit transfer mode. dma transfer is started from the address set to this dran register. when the data of the last address has been transferred, dran stops with the value of the last address +1 in the 8-bit transfer mode, and the last address +2 in the 16-bit transfer mode. in the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address. dran can be read or written in 8-bit or 16-bit units. however, it cannot be written during dma transfer. reset signal generation clears this register to 0000h. figure 18-2. format of dma ram address register n (dran) address: fffb2h, fffb3h (dra0), fffb4h, fffb5h (dra1) after reset: 0000h r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dran (n = 0, 1) remark n: dma channel number (n = 0, 1) dra0h: fffb3h dra1h: fffb5h dra0l: fffb2h dra1l: fffb4h
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 720 jun 20, 2011 (3) dma byte count register n (dbcn) this is a 10-bit register that is used to set the number of times dma channel n executes transfer. be sure to set the number of times of transfer to this dbcn regist er before executing dma transfer (up to 1024 times). each time dma transfer has been executed, this register is automatically decremented. by reading this dbcn register during dma transfer, the remaining number of times of transfer can be learned. dbcn can be read or written in 8-bit or 16-bit units. however, it cannot be written during dma transfer. reset signal generation clears this register to 0000h. figure 18-3. format of dma byte count register n (dbcn) address: fffb6h, fffb7h (dbc0), fffb8h, fffb9h (dbc1) after reset: 0000h r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dbcn 0 0 0 0 0 0 (n = 0, 1) dbcn[9:0] number of times of transfer (when dbcn is written) remaining number of times of transfer (when dbcn is read) 000h 1024 completion of transfer or waiting for 1024 times of dma transfer 001h 1 waiting for remaining one time of dma transfer 002h 2 waiting for remaining two times of dma transfer 003h 3 waiting for remaining three times of dma transfer ? ? ? ? ? ? ? ? ? 3feh 1022 waiting for remaining 1022 times of dma transfer 3ffh 1023 waiting for remaining 1023 times of dma transfer cautions 1. be sure to cl ear bits 15 to 10 to ?0?. 2. if the general-purpose register is specif ied or the internal ram space is exceeded as a result of continuous transfer, the general-purpose register or sfr space are written or read, resulting in loss of data in these spaces. be sure to set the num ber of times of transfer that is within the internal ram space. remark n: dma channel number (n = 0, 1) dbc0h: fffb7h dbc1h: fffb9h dbc0l: fffb6h dbc1l: fffb8h
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 721 jun 20, 2011 18.3 registers controlling dma controller dma controller is controlle d by the following registers. ? dma mode control register n (dmcn) ? dma operation control register n (drcn) remark n: dma channel number (n = 0, 1) (1) dma mode control register n (dmcn) dmcn is a register that is used to set a transfer mode of dma channel n. it is used to select a transfer direction, data size, setting of pending, and start source. bit 7 (stgn) is a software trigger that starts dma. rewriting bits 6, 5, and 3 to 0 of dmcn is prohibited during operation (when dstn = 1). dmcn can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 18-4. format of dma mode control register n (dmcn) (1/2) address: fffbah (dmc0), fffbbh (dmc1) after reset: 00h r/w symbol <7> <6> <5> <4> 3 2 1 0 dmcn stgn drsn dsn dwaitn ifcn3 ifcn2 ifcn1 ifcn0 stgn note 1 dma transfer start software trigger 0 no trigger operation 1 dma transfer is started when dma operation is enabled (denn = 1). dma transfer is started by writing 1 to stgn when dma operation is enabled (denn = 1). when this bit is read, 0 is always read. drsn selection of dma transfer direction 0 sfr to internal ram 1 internal ram to sfr dsn specification of transfer data size for dma transfer 0 8 bits 1 16 bits dwaitn note 2 pending of dma transfer 0 executes dma transfer upon dma start request (not held pending). 1 holds dma start request pending if any. dma transfer that has been held pending can be star ted by clearing the value of dwaitn to 0. it takes 2 clocks to actually hold dma transfer pending when the value of dwaitn is set to 1. notes 1. the software trigger (stgn) can be used regard less of the ifcn0 to ifcn3 bits values. 2. when dma transfer is held pending while using both dma channels, be sure to hold the dma transfer pending for both channels (by setting the dwait0 and dwait1 bits to 1). remark n: dma channel number (n = 0, 1)
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 722 jun 20, 2011 figure 18-4. format of dma mode control register n (dmcn) (2/2) address: fffbah (dmc0), fffbbh (dmc1) after reset: 00h r/w symbol <7> <6> <5> <4> 3 2 1 0 dmcn stgn drsn dsn dwaitn ifcn3 ifcn2 ifcn1 ifcn0 selection of dma start source note ifcn 3 ifcn 2 ifcn 1 ifcn 0 trigger signal trigger contents lf3 lg3 lh3 0 0 0 0 ? disables dma transfer by interrupt. (only software trigger is enabled.) 0 0 1 0 inttm00 timer channel 0 interrupt 0 0 1 1 inttm01 timer channel 1 interrupt 0 1 0 0 inttm04 timer channel 4 interrupt 0 1 0 1 inttm05 timer channel 5 interrupt intst0 uart0 transmission end interrupt ? 0 1 1 0 intcsi00 csi00 transfer end interrupt ? intsr0 uart0 reception end interrupt ? 0 1 1 1 intcsi01 csi01 transfer end interrupt ? ? intst1 uart1 transmission end interrupt intcsi10 csi10 transfer end interrupt 1 0 0 0 intiic10 iic10 transfer end interrupt 1 0 0 1 intsr1 uart1 reception end interrupt 1 0 1 0 intst3 uart3 transmission end interrupt 1 0 1 1 intsr3 uart3 reception end interrupt 1 1 0 0 intad a/d conversion end interrupt other than above setting prohibited note the software trigger (stgn) can be used r egardless of the ifcn0 to ifcn3 values. remarks 1. n: dma channel number (n = 0, 1) 2. : supported, ? : not supported
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 723 jun 20, 2011 (2) dma operation control register n (drcn) drcn is a register that is used to enable or disable transfer of dma channel n. rewriting bit 7 (denn) of this register is prohibited during operation (when dstn = 1). drcn can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 18-5. format of dma oper ation control register n (drcn) address: fffbch (drc0), fffbdh (drc1) after reset: 00h r/w symbol <7> 6 5 4 3 2 1 <0> drcn denn 0 0 0 0 0 0 dstn denn dma operation enable flag 0 disables operation of dma channel n (stops operating cock of dma). 1 enables operation of dma channel n. dmac waits for a dma trigger when dstn = 1 after dma operation is enabled (denn = 1). dstn dma transfer mode flag 0 dma transfer of dma channel n is completed. 1 dma transfer of dma channel n is not completed (still under execution). dmac waits for a dma trigger when dstn = 1 after dma operation is enabled (denn = 1). when a software trigger (stgn) or the start source trigger set by ifcn3 to ifcn0 is input, dma transfer is started. when dma transfer is completed after that, this bit is automatic ally cleared to 0. write 0 to this bit to forcibly te rminate dma transfer under execution. cautions 1. the dstn flag is automatically cl eared to 0 when a dma tr ansfer is completed. writing the denn flag is enab led only when dstn = 0. when a dma transfer is terminated without waiting for generation of the interrupt (intdman) of dm an, therefore, set dstn to 0 and then denn to 0 (for details, refer to 18.5.7 forced termination by software). 2. when the fsel bit of the os mc register has been set to 1, do not enable (denn = 1) dma operation for at least thr ee clocks after the setting. remark n: dma channel number (n = 0, 1)
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 724 jun 20, 2011 no no dstn = 1 dstn = 0 intdman = 1 dma trigger = 1? dbcn = 0000h ? yes yes denn = 1 setting dsan, dran, dbcn, and dmcn transmitting dma request receiving dma acknowledge dma transfer dran = dran + 1 (or + 2) dbcn = dbcn ? 1 denn = 0 set by software program operation by dma controller (hardware) set by software program 18.4 operation of dma controller 18.4.1 operation procedure <1> the dma controller is enabled to operate when denn = 1. before writing the other registers, be sure to set denn to 1. use 80h to write wit h an 8-bit manipulation instruction. <2> set an sfr address, a ram address, the number of time s of transfer, and a transfer mo de of dma transfer to the dsan, dran, dbcn, and dmcn registers. <3> the dma controller waits for a dma trigger when dstn = 1. use 81h to write with an 8-bit manipulation instruction. <4> when a software trigger (stgn) or a start source trigger specified by ifcn3 to ifcn0 is input, a dma transfer is started. <5> transfer is completed when the number of times of transfe r set by the dbcn register reaches 0, and transfer is automatically terminated by occurr ence of an interrupt (intdman). <6> stop the operation of the dma c ontroller by clearing denn to 0 w hen the dma controller is not used. figure 18-6. operation procedure remark n: dma channel number (n = 0, 1)
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 725 jun 20, 2011 18.4.2 transfer mode the following four modes can be selected for dma transfer by using bits 6 and 5 (drsn and dsn) of the dmcn register. drsn dsn dma transfer mode 0 0 transfer from sfr of 1-byte data (fixed add ress) to ram (address is incremented by +1) 0 1 transfer from sfr of 2-byte data (fixed add ress) to ram (address is incremented by +2) 1 0 transfer from ram of 1-byte data (address is incremented by +1) to sfr (fixed address) 1 1 transfer from ram of 2-byte data (address is incremented by +2) to sfr (fixed address) by using these transfer modes, up to 1024 bytes of data can be consecutively transferred by using the serial interface, data resulting from a/d conversion can be consecutively transferred, and port data c an be scanned at fixed time intervals by using a timer. 18.4.3 termination of dma transfer when dbcn = 00h and dma transfer is completed, the dstn bit is automatically cleared to 0. an interrupt request (intdman) is generated and transfer is terminated. when the dstn bit is cleared to 0 to forcibly terminate dma transfer, the dbcn and dr an registers hold the value when transfer is terminated. the interrupt request (intdman) is not ge nerated if transfer is forcibly terminated. remark n: dma channel number (n = 0, 1) 18.5 example of setting of dma controller 18.5.1 csi consecutive transmission a flowchart showing an example of setting for csi consecutive transmission is shown below. ? consecutive transmission of csi10 ? dma channel 0 is used for dma transfer. ? dma start source: intcsi10 (software trigger (stg0) only for the first start source) ? interrupt of csi10 is specified by ifc03 to if c00 (bits 3 to 0 of the dmc0 register) = 1000b. ? transfers ffb00h to ffbffh (256 bytes) of ram to fff44h of the transmit buffer (sio10) of csi.
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 726 jun 20, 2011 figure 18-7. example of setting for csi consecuti ve transmission note the dst0 flag is automatically cleared to 0 when a dma transfer is completed. writing the den0 flag is enabled only when dst0 = 0. to terminate a dma transfer without waiting for occurrence of the interrupt of dma0 (intdma0), set dst0 to 0 and then den0 to 0 (for details, refer to 18.5.7 forced termination by software ). the fist trigger for consecutive transmission is not started by the interr upt of csi. in this example, it start by a software trigger. csi transmission of the second time and onward is automatically executed. a dma interrupt (intdma0) occurs when the last trans mit data has been written to the data register. setting for csi transfer den0 = 1 dsa0 = 44h dra0 = fb00h dbc0 = 0100h dmc0 = 48h den0 = 0 dst0 = 1 stg0 = 1 start dma is started. intcsi10 occurs. reti end user program processing occurrence of intdma0 dst0 = 0 note dma0 transfer csi transmission hardware operation
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 727 jun 20, 2011 18.5.2 csi master reception a flowchart showing an example of setting for csi master reception is shown below. ? master reception (256 bytes) of csi00 ? dma channel 0 is used to read received data and dma channel 1 is used to write dummy data. ? dma start source: intcsi00 (if the same start source is specified for dma channels 0 and 1, the data of channel 0 is transferred, and then that of channel 1.) ? interrupt of csi00 is specified by ifc03 to ifc00 = if c13 to ifc10 (bits 3 to 0 of the dmcn register) = 0110b. ? data is transferred (received) from fff10h of the cs i data register (sio00) to ff100h to ff1ffh of ram (256 bytes). (in successive reception mode, the data that is to be received when the first buffer empty interrupt occurs is invalid because the data has not been received.) ? transfers dummy data ff101h to ff1ffh (255 bytes) of ram to fff10h of the data register (sio00) of csi. (dummy data is written to the first byte by using software (an instruction).)
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 728 jun 20, 2011 figure 18-8. example of setting of cons ecutively capturing a/d conversion results note the dstn flag is automatically cleared to 0 when a dma transfer is completed. writing the denn flag is enabled only when dstn = 0. to terminate a dma transfer without waiting for occurrence of the interrupt of dman (intdman), set dstn to 0 and then denn to 0 (for details, refer to 18.5.7 forcible termination by software ). because no csi interrupt is generated when reception starts during csi master re ception, dummy data is written using software in this example. the received data is automatically transfe rred from the first byte (in successive reception mode, the data that is to be received when the first buffer empty interrupt occurs is invalid because the valid data has not been received.). a dma interrupt (intdma1) occurs when the last dummy data has been writing to the data register. a dma interrupt (intdma0) occurs when the last received data has been read fr om the data register. to restart the dma transfer, the csi transfer must be completed. setting for csi transfer den0 = 1 den1 = 1 dsa0 = 10h dra0 = f100h dbc0 = 0100h dmc0 = 06h den0 = 0 dst0 = 1 dst1 = 1 start reti end user program processing dst0 = 0 note dma0 transfer csi reception dma1 transfer writing dummy data hardware operation dsa1 = 10h dra1 = f101h dbc1 = 00ffh dmc1 = 46h intcsi00 occurs. dst1 = 0 note den1 = 0 reti write dummy data to sio00 (= sdr00 [7:0]) intdma1 occurs. intdma0 occurs.
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 729 jun 20, 2011 18.5.3 csi transmission/reception a flowchart showing an example of setting for csi transmission/reception is shown below. ? transmission/reception (256 bytes) of csi00 ? dma channel 0 is used to read received data and dma channel 1 is used to write transmit data. ? dma start source: intcsi00 (if the same start source is specified for dma channels 0 and 1, the data of channel 0 is transferred, and then that of channel 1) ? interrupt of csi00 is specified by ifc03 to ifc00 = if c13 to ifc10 (bits 3 to 0 of the dmcn register) = 0110b. ? data is transferred (received) from fff10h of the cs i data register (sio00) to ff100h to ff1ffh of ram (256 bytes). (in successive transmission/reception mode, the data that is to be received when the first buffer empty interrupt occurs is invalid because the data has not been received.) ? transfers ff201h to ff2ffh (255 bytes) of ram to fff10h of the data register (sio00) of csi (transmission) (transmit data is written to the first by te by using software (an instruction).)
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 730 jun 20, 2011 figure 18-9. setting example of csi transmission/reception note the dstn flag is automatically cleared to 0 when a dma transfer is completed. writing the denn flag is enabled only when dstn = 0. to terminate a dma transfer without waiting for occurrence of the interrupt of dman (intdman), set dstn to 0 and then denn to 0 (for details, refer to 18.5.7 forcible termination by software ). during csi transfers, no csi interrupt is generated when the trans mitted data of the first byte is written. therefore, the transmitted data is written using software in this example. the dat a of the second and following bytes is automatically transmitted. the received data is automatically transfe rred from the first byte. (in successive transmission/reception, the data that is to be received when the first buffer empty interrupt occurs is invalid because the valid data has not been received.) a dma interrupt (intdma1) occurs when the last transmit data has been writing to the data register. a dma interrupt (intdma0) occurs when the last received data has been read fr om the data register. to restart the dma transfer, the csi transfer must be completed. setting for csi transfer den0 = 1 den1 = 1 dsa0 = 10h dra0 = f100h dbc0 = 0100h dmc0 = 06h den0 = 0 dst0 = 1 dst1 = 1 start reti end user program processing dst0 = 0 note dma0 transfer csi reception dma1 transfer csi transmission hardware operation dsa1 = 10h dra1 = f201h dbc1 = 00ffh dmc1 = 46h intcsi00 occurs. dst1 = 0 note den1 = 0 reti write transmit data to sio00 (= sdr00 [7:0]) intdma1 occurs. intdma0 occurs.
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 731 jun 20, 2011 18.5.4 consecutive capturing of a/d conversion results a flowchart of an example of setting for consecutivel y capturing a/d conversion results is shown below. ? consecutive capturing of a/d conversion results. ? dma channel 1 is used for dma transfer. ? dma start source: intad ? interrupt of a/d is specified by ifc13 to if c10 (bits 3 to 0 of the dmc1 register) = 1100b. ? transfers fff1eh and fff1fh (2 bytes) of the 12-bit a/d conversion result register to 512 bytes of ffce0h to ffedfh of ram.
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 732 jun 20, 2011 figure 18-10. example of setting of cons ecutively capturing a/d conversion results note the dst1 flag is automatically cleared to 0 when a dma transfer is completed. writing the den1 flag is enabled only when dst1 = 0. to terminate a dma transfer without waiting for occurrence of the interrupt of dma1 (intdma1), set dst1 to 0 and then den1 to 0 (for details, refer to 18.5.7 forced termination by software ). hardware operation den1 = 1 dsa1 = 1eh dra1 = fce0h dbc1 = 0100h dmc1 = 2ch dst1 = 1 starting a/d conversion den1 = 0 reti end intdma1 occurs. dst1 = 0 note intad occurs. dma1 transfer start user program processing
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 733 jun 20, 2011 18.5.5 uart consecutive r eception + ack transmission a flowchart illustrating an example of setting for uart consecutive reception + ack transmission is shown below. ? consecutively receives data fr om uart0 and outputs ack to p10 on completion of reception. ? dma channel 0 is used for dma transfer. ? dma start source: software trigger (dma transfer on occurrence of an interrupt is disabled.) ? transfers fff12h of uart receive data register 0 (rxd0) to 64 bytes of ffe00h to ffe3fh of ram.
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 734 jun 20, 2011 den0 = 1 dsa0 = 12h dra0 = fe00h dbc0 = 0040h dmc0 = 00h den0 = 0 note setting for uart reception dst0 = 1 user program processing stg0 = 1 p10 = 1 p10 = 0 intsr0 occurs. intdma0 occurs. dst0 = 0 dma0 transfer reti hardware operation start end reti intsr0 interrupt routine figure 18-11. example of setting for uar t consecutive reception + ack transmission note the dst0 flag is automatically cleared to 0 when a dma transfer is completed. writing the den0 flag is enabled only when dst0 = 0. to terminate a dma transfer without waiting for occurrence of the interrupt of dma0 (intdma0), set dst0 to 0 and then den0 to 0 (for details, refer to 18.5.7 forced termination by software ). remark this is an example where a software trigger is used as a dma start source. if ack is not transmitted and if only data is consecut ively received from uart, the uart reception end interrupt (intsr0) can be used to start dma for data reception.
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 735 jun 20, 2011 starting dma transfer dwaitn = 0 dwaitn = 1 wait for 2 clocks p10 = 1 wait for 9 clocks p10 = 0 main program 18.5.6 holding dma transfer pending by dwaitn when dma transfer is started, transfer is performed while an instruction is executed . at this time, the operation of the cpu is stopped and delayed for the duration of 2 clocks. if th is poses a problem to the operation of the set system, a dma transfer can be held pending by setting the dwaitn bit to 1. the dma transfer for a transfer trigger that occurred while dma transfer was held pending is executed after t he pending status is canceled. however, because only one transfer trigger can be held pending for each channel, even if multiple transfer triggers occur for one channel during the pending status, only one dma transfer is exec uted after the pending status is canceled. to output a pulse with a width of 10 clocks of the operatin g frequency from the p10 pin, for example, the clock width increases to 12 if a dma transfer is started midway. in this case, the dma transfer can be held pending by setting the dwaitn bit to 1. after setting the dwaitn bit to 1, it takes tw o clocks until a dma transfer is held pending. figure 18-12. example of setting for ho lding dma transfer pending by dwaitn caution when dma transfer is held pending while using both dma channels, be sure to held the dma transfer pending for both channels (by setting dwait0 and dwait1 to 1). if the dma transfer of one channel is executed while that of the other channel is held pend ing, dma transfer might not be held pending for the latter channel. remarks 1. n: dma channel number (n = 0, 1) 2. 1 clock: 1/f clk (f clk : cpu clock)
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 736 jun 20, 2011 dstn = 0 denn = 0 dstn = 0 ? no 2 clock wait yes dstn = 0 denn = 0 18.5.7 forced termination by software after dstn is set to 0 by software, it takes up to 2 clocks until a dma transfer is actually stopped and dstn is set to 0. to forcibly terminate a dma transfer by software without wa iting for occurrence of the in terrupt (intdman) of dman, therefore, perform either of the following processes. ? set the dstn bit to 0 (use drcn = 80h to write with an 8- bit manipulation instruction) by software, confirm by polling that the dstn bit has actually been cleared to 0, and then set the denn bit to 0 (use drcn = 00h to write with an 8- bit manipulation instruction). ? set the dstn bit to 0 (use drcn = 80h to write with an 8- bit manipulation instruction) by software and then set the denn bit to 0 (use drcn = 00h to write with an 8-bit manipulation instruction) tw o or more clocks after. ? to forcibly terminate dma transfer by software when using both dma channels (by setting dstn to 0), clear the dstn bit to 0 after the dma transfer is held pending by setti ng the dwait0 and dwait1 bits of both channels to 1. next, clear the dwait0 and dwait1 bits of both channels to 0 to cancel the pending status, and then clear the denn bit to 0. figure 18-13. forced terminati on of dma transfer (1/2) example 1 example 2 remarks 1. n: dma channel number (n = 0, 1) 2. 1 clock: 1/f clk (f clk : cpu clock)
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 737 jun 20, 2011 dwait0 = 1 dwait1 = 1 dst0 = 0 dst1 = 0 den0 = 0 den1 = 0 dwait0 = 0 dwait1 = 0 dwait0 = 1 dwait1 = 1 dstn = 0 denn = 0 dwait0 = 0 dwait1 = 0 figure 18-13. forced terminati on of dma transfer (2/2) example 3 ? procedure for forcibly terminating the dma ? procedure for forcibly terminating the dma transfer for one channel if both channels are used transfer for both channels if both channels are used caution in example 3, the system is not required to wait two clock cycles afte r the dwaitn bit is set to 1. in addition, the system does not have to wait two cl ock cycles after clearing the dstn bit to 0, because more than two clo ck cycles elapse from when the dstn bit is cleared to 0 to when the denn bit is cleared to 0. remarks 1. n: dma channel number (n = 0, 1) 2. 1 clock: 1/f clk (f clk : cpu clock)
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 738 jun 20, 2011 18.6 cautions on using dma controller (1) priority of dma during dma transfer, a request from the other dma chan nel is held pending even if generated. the pending dma transfer is started after the ongoing dma transfer is completed. if two dma requests are generated at the same time, however, dma channel 0 takes priority over dma channel 1. if a dma request and an interrupt request are generated at t he same time, the dma transfer takes precedence, and then interrupt servicing is executed. (2) dma response time the response time of dma transfer is as follows. table 17-2. response time of dma transfer minimum time maximum time response time 3 clocks 10 clocks note note the maximum time necessary to execute an inst ruction from internal ram is 16 clock cycles. cautions 1. the above response time does not include the two clock cycles required for a dma transfer. 2. when executing a dma pe nding instruction (see 18.6 (4)), the maximum response time is extended by the execu tion time of that instruct ion to be held pending. 3. do not specify successive transfer triggers for a ch annel within a period equal to the maximum response time plus one clock cycle, because they might be ignored. remark 1 clock: 1/f clk (f clk : cpu clock)
78k0r/lx3 chapter 18 dma controller r01uh0004ej0501 rev.5.01 739 jun 20, 2011 (3) operation in standby mode the dma controller operates as follows in the standby mode. table 18-3. dma operation in standby mode status dma operation halt mode normal operation stop mode stops operation. if dma transfer and stop instruction execution contend, dma transfer may be damaged. therefore, stop dma before executing the stop instruction. (4) dma pending instruction even if a dma request is generated, dma transfer is he ld pending immediately after the following instructions. ? call !addr16 ? call $!addr20 ? call !!addr20 ? call rp ? callt [addr5] ? brk ? bit manipulation instructions for registers if0l, if0h, if1l, if1h, if2l, if2h, mk0l, mk0h, mk1l, mk1h, mk2l, mk2h, pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, pr12h and psw each. (5) operation if address in ge neral-purpose register area or other than those of internal ram area is specified the address indicated by dra0n is incremented during dma transfer. if the address is incremented to an address in the general-purpose register area or exceeds th e area of the internal ram, the following operation is performed. z in mode of transfer from sfr to ram the data of that address is lost. z in mode of transfer from ram to sfr undefined data is transferred to sfr. in either case, malfunctioning may occur or damage may be done to the system. therefore, make sure that the address is within the internal ram area other than the general-pur pose register area. internal ram general-purpose registers dma transfer enabled area fff00h ffeffh ffee0h ffedfh
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 740 jun 20, 2011 chapter 19 interrupt functions 78k0r/lf3 78k0r/fg3 78k0r/lh3 80 pins 100 pins 128 pins external 30 33 33 maskable interrupts internal 8 12 13 19.1 interrupt function types the following two types of inte rrupt functions are used. (1) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into four priority groups by setting the priority specification flag registers (pr00l, pr00h, pr 01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, pr12h). multiple interrupt servicing can be applied to low-priority in terrupts when high-priority interrupts are generated. if two or more interrupt requests, each having the same priori ty, are simultaneously generat ed, then they are processed according to the priority of vectored interrupt servicing. for the priority order, see table 19-1 . a standby release signal is generated a nd stop and halt modes are released. external interrupt requests and internal interrupt requests are provided as maskable interrupts. (2) software interrupt this is a vectored interrupt generated by executing the brk instruction. it is acknowledged even when interrupts are disabled. the software interrupt does not undergo interrupt priority control.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 741 jun 20, 2011 19.2 interrupt sources and configuration the interrupt sources consist of maskable interrupts and software interrupts. in addition, they also have up to five reset sources (see table 19-1 ). the vector codes that stor e the program start address when branching due to the generation of a reset or various interrupt requests are two bytes each, so interrupts jump to a 64 k address of 00000h to 0ffffh. table 19-1. interrupt source list (1/3) interrupt source interrupt type internal/ external basic configuration type note 1 default priority note 2 name trigger vector table address lf 3 lg 3 lh 3 0 intwdti watchdog timer interval note 3 (75% of overflow time) 00004h internal (a) 1 intlvi low-voltage detection note 4 00006h 2 intp0 00008h 3 intp1 0000ah 4 intp2 0000ch 5 intp3 0000eh 6 intp4 00010h external (b) 7 intp5 pin input edge detection 00012h 8 intst3 end of uart3 transmission 00014h 9 intsr3 end of uart3 reception 00016h 10 intsre3 uart3 reception error occurrence 00018h 11 intdma0 end of dma0 transfer 0001ah 12 intdma1 end of dma1 transfer 0001ch intst0 end of uart0 transmission ? 13 intcsi00 end of csi00 communication 0001eh ? intsr0 end of uart0 reception ? 14 intcsi01 end of csi01 communication 00020h ? ? 15 intsre0 csi01/uart0 reception error occurrence 00022h intst1 end of uart1 transmission intcsi10 end of csi10 communication 16 intiic10 end of iic10 communication 00024h 17 intsr1 end of uart1 reception 00026h 18 intsre1 uart1 reception error occurrence 00028h 19 intiica end of iica communication 0002ah ? maskable internal (a) 20 inttm00 end of timer channel 0 count or capture 0002ch notes 1. the default priority determines the sequence of in terrupts if two or more maskable interrupts occur simultaneously. zero indicates the highest priority and 45 indicates the lowest priority. 2. basic configuration types (a) to (d) co rrespond to (a) to (d) in figure 19-1. 3. when bit 7 (wdtint) of the option byte (000c0h) is set to 1. 4. when bit 1 (lvimd) of the low-voltage detec tion register (lvim) is cleared to 0.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 742 jun 20, 2011 table 19-1. interrupt source list (2/3) interrupt source interrupt type internal/ external basic configuration type note 1 default priority note 2 name trigger vector table address lf 3 lg 3 lh 3 21 inttm01 end of timer channel 1 count or capture 0002eh 22 inttm02 end of timer channel 2 count or capture 00030h 23 inttm03 end of timer channel 3 count or capture 00032h 24 intad end of a/d conversion 00034h 25 intrtc fixed-cycle signal of real-time counter/alarm match detection 00036h internal (a) 26 intrtci interval signal dete ction of real-time counter 00038h external (c) 27 intkr key return signal detection 0003ah ? ? intst2 end of uart2 transmission/ intcsi20 end of csi20 communication/ 28 intiic20 end of iic20 communication 0003ch 29 intsr2 end of uart2 reception 0003eh 30 intsre2 uart2 reception error occurrence 00040h 31 inttm04 end of timer channel 4 count or capture 00042h 32 inttm05 end of timer channel 5 count or capture 00044h 33 inttm06 end of timer channel 6 count or capture 00046h internal (a) 34 inttm07 end of timer channel 7 count or capture 00048h 35 intp6 0004ah 36 intp7 0004ch 37 intp8 0004eh ? 38 intp9 00050h ? 39 intp10 00052h ? maskable external (b) 40 intp11 pin input edge detection 00054h ? notes 1. the default priority determines the sequence of in terrupts if two or more maskable interrupts occur simultaneously. zero indicates the highest priority and 45 indicates the lowest priority. 2. basic configuration types (a) to (d) co rrespond to (a) to (d) in figure 19-1.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 743 jun 20, 2011 table 19-1. interrupt source list (3/3) interrupt source interrupt type internal/ external basic configuration type note 1 default priority note 2 name trigger vector table address lf 3 lg 3 lh 3 41 inttm10 end of timer channel 10 count or capture 00056h 42 inttm11 end of timer channel 11 count or capture 00058h 43 inttm12 end of timer channel 12 count or capture 0005ah 44 inttm13 end of timer channel 13 count or capture 0005ch maskable internal (a) 45 intmd end of multiply/divide operation 0005eh software ? (d) ? brk execution of brk instruction 0007eh reset reset pin input poc power-on-clear lvi low-voltage detection note 3 wdt overflow of watchdog timer reset ? ? ? trap execution of illegal instruction note 4 00000h notes 1. the default priority determines the sequence of in terrupts if two or more maskable interrupts occur simultaneously. zero indicates the highest priority and 45 indicates the lowest priority. 2. basic configuration types (a) to (d) co rrespond to (a) to (d) in figure 19-1. 3. when bit 1 (lvimd) of the low-voltage detection register (lvim) is set to 1. 4. when the instruction code in ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circu it emulator or on-chip debug emulator.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 744 jun 20, 2011 figure 19-1. basic configurati on of interrupt function (1/2) (a) internal maskable interrupt if mk ie pr1 isp1 pr0 isp0 internal bus interrupt request priority controller vector table address generator standby release signal (b) external maskable interrupt (intpn) if mk ie pr1 isp1 pr0 isp0 internal bus external interrupt edge enable register (egp, egn) interrupt request edge detector priority controller vector table address generator standby release signal if: interrupt request flag ie: interrupt enable flag isp0: in-service priority flag 0 isp1: in-service priority flag 1 mk: interrupt mask flag pr0: priority specification flag 0 pr1: priority specification flag 1
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 745 jun 20, 2011 figure 19-1. basic configurati on of interrupt function (2/2) (c) external maskable interrupt (intkr) if mk krmn ie pr1 isp1 pr0 isp0 internal bus krn pin input priority controller vector table address generator standby release signal key interrupt detector key return mode register (krm) (d) software interrupt vector table address generator internal bus interrupt request if: interrupt request flag ie: interrupt enable flag isp0: in-service priority flag 0 isp1: in-service priority flag 1 mk: interrupt mask flag pr0: priority specification flag 0 pr1: priority specification flag 1
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 746 jun 20, 2011 19.3 registers controlling interrupt functions the following 6 types of registers are used to control the interrupt functions. ? interrupt request flag registers (i f0l, if0h, if1l, if1h, if2l, if2h) ? interrupt mask flag registers (mk0l, mk0h, mk1l, mk1h, mk2l, mk2h) ? priority specification flag registers (pr00l, pr00h , pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, pr12h) ? external interrupt rising edge enable registers (egp0, egp1) ? external interrupt falling edge enable registers (egn0, egn1) ? program status word (psw) table 19-2 shows a list of interrupt request flags, interrupt ma sk flags, and priority specification flags corresponding to interrupt request sources. table 19-2. flags corresponding to interrupt request sources (1/2) interrupt request flag interrupt mask flag priority specification flag lf3 lg3 lh3 interrupt source register register register intwdti wdtiif wdtimk wdtipr0, wdtipr1 intlvi lviif lvimk lvipr0, lvipr1 intp0 pif0 pmk0 ppr00, ppr10 intp1 pif1 pmk1 ppr01, ppr11 intp2 pif2 pmk2 ppr02, ppr12 intp3 pif3 pmk3 ppr03, ppr13 intp4 pif4 pmk4 ppr04, ppr14 intp5 pif5 if0l pmk5 mk0l ppr05, ppr15 pr00l, pr10l intst3 stif3 stmk3 stpr03, stpr13 intsr3 srif3 srmk3 srpr03, srpr13 intsre3 sreif3 sremk3 srepr03, srepr13 intdma0 dmaif0 dmamk0 dmapr00, dmapr10 intdma1 dmaif1 dmamk1 dmapr01, dmapr11 ? intst0 note 1 stif0 note 1 stmk0 note 1 stpr00, stpr10 note 1 ? intcsi00 note 1 csiif00 note 1 csimk00 note 1 csipr000, csipr100 note 1 ? intsr0 note 2 srif0 note 2 srmk0 note 2 srpr00, srpr10 note 2 ? ? intcsi01 note 2 csiif01 note 2 csimk01 note 2 csipr001, csipr101 note 2 intsre0 sreif0 if0h sremk0 mk0h srepr00, srepr10 pr00h, pr10h notes 1. do not use uart0 and csi00 at the same time because t hey share flags for the interrupt request sources. if one of the interrupt sources intst0 and intcsi00 is gener ated, bit 5 of if1h is set to 1. bit 5 of mk0h, pr00h, and pr10h supports these two interrupt sources. 2. do not use uart0 and csi01 at the same time because t hey share flags for the interrupt request sources. if one of the interrupt sources intsr0 and intcsi01 is gener ated, bit 6 of if0h is set to 1. bit 6 of mk0h, pr00h, and pr10h supports these two interrupt sources.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 747 jun 20, 2011 table 19-2. flags corresponding to interrupt request sources (2/2) interrupt request flag interrupt mask flag priority specification flag lf3 lg3 lh3 interrupt source register register register intst1 note 1 stif1 note 1 stmk1 note 1 stpr01, stpr11 note 1 intcsi10 note 1 csiif10 note 1 csimk10 note 1 csipr010, csipr110 note 1 intiic10 note 1 iicif10 note 1 iicmk10 note 1 iicpr010, iicpr110 note 1 intsr1 srif1 srmk1 srpr01, srpr11 intsre1 sreif1 sremk1 srepr01, srepr11 ? intiica iicaif iicamk iicapr0, iicapr1 inttm00 tmif00 tmmk00 tmpr000, tmpr100 inttm01 tmif01 tmmk01 tmpr001, tmpr101 inttm02 tmif02 tmmk02 tmpr002, tmpr102 inttm03 tmif03 if1l tmmk03 mk1l tmpr003, tmpr103 pr01l, pr11l intad adif admk adpr0, adpr1 intrtc rtcif rtcmk rtcpr0, rtcpr1 intrtci rtciif rtcimk rtcipr0, rtcipr1 ? ? intkr krif krmk krpr0, krpr1 intst2 note 2 stif2 note 2 stmk2 note 2 stpr02, stpr12 note 2 intcsi20 note 2 csiif20 note 2 csimk20 note 2 csipr020, csipr120 note 2 intiic20 note 2 iicif20 note 2 iicmk20 note 2 iicpr020, iicpr120 note 2 intsr2 srif2 srmk2 srpr02, srpr12 intsre2 sreif2 sremk2 srepr02, srepr12 inttm04 tmif04 if1h tmmk04 mk1h tmpr004, tmpr104 pr01h, pr11h inttm05 tmif05 tmmk05 tmpr005, tmpr105 inttm06 tmif06 tmmk06 tmpr006, tmpr106 inttm07 tmif07 tmmk07 tmpr007, tmpr107 intp6 pif6 pmk6 ppr06, ppr16 intp7 pif7 pmk7 ppr07, ppr17 ? intp8 pif8 pmk8 ppr08, ppr18 ? intp9 pif9 pmk9 ppr09, ppr19 ? intp10 pif10 if2l pmk10 mk2l ppr010, ppr110 pr02l, pr12l ? intp11 pif11 pmk11 ppr011, ppr111 inttm10 tmif10 tmmk10 tmpr010, tmpr110 inttm11 tmif11 tmmk11 tmpr011, tmpr111 inttm12 tmif12 tmmk12 tmpr012, tmpr112 inttm13 tmif13 tmmk13 tmpr013, tmpr113 intmd mdif if2h mdmk mk2h mdpr0, mdpr1 pr02h, pr12h notes 1. do not use uart1, csi10, and iic10 at the same time because they share flags for the interrupt request sources. if one of the interrupt sources intst1, intcsi 10, and intiic10 is generated, bit 0 of if1l is set to 1. bit 0 of mk1l, pr01l, and pr11l s upports these three interrupt sources. 2. do not use uart2, csi20, and iic20 at the same time because they share flags for the interrupt request sources. if one of the interrupt sources intst2, intcsi 20, and intiic20 is generated, bit 4 of if1h is set to 1. bit 4 of mk1h, pr01h, and pr11h s upports these three interrupt sources.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 748 jun 20, 2011 (1) interrupt request flag registers (i f0l, if0h, if1l, if1h, if2l, if2h) the interrupt request flags are set to 1 when the correspondi ng interrupt request is generated or an instruction is executed. they are cleared to 0 w hen an instruction is executed upon a cknowledgment of an interrupt request or upon reset signal generation. when an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered. if0l, if0h, if1l, if1h, if2l, and if2h can be set by a 1-bit or 8-bit memory manipulation instruction. when if0l and if0h, if1l and if1h, and if2l and if2h are combined to form 16-bit registers if0, if 1, and if2, they can be set by a 16-bit memory manipulation instruction. reset signal generation clears these registers to 00h. cautions 1. when operating a timer, serial interface, or a/d converter a fter standby release, operate it once after clearing the interrupt request flag. an interrupt request flag may be set by noise. 2. when manipulating a flag of the interrupt request flag regist er, use a 1-bit memory manipulation instruction (clr1). when describing in c langua ge, use a bit manipulatio n instruction such as ?if0l.0 = 0;? or ?_asm(?clr1 if0l, 0?);? because the compiled assembler mu st be a 1-bit memory manipulation instruction (clr1). if a program is described in c language using an 8-bit memory manipulation instruction such as ?if0l &= 0xfe;? and compiled, it becom es the assembler of three instructions. mov a, if0l and a, #0feh mov if0l, a in this case, even if th e request flag of another bit of the same interrupt request flag register (if0l) is set to 1 at the timing between ?mov a, if0l? and ?mov if 0l, a?, the flag is cleared to 0 at ?mov if0l, a?. therefore, care must be exerc ised when using an 8-bit memory manipulation instruction in c language. remark if an instruction that writes data to this register is execut ed, the number of instru ction execution clocks increases by 2 clocks.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 749 jun 20, 2011 figure 19-2. format of interrupt request flag regist ers (if0l, if0h, if1l, if1h , if2l, if2h) (78k0r/lf3) address: fffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l pif5 pif4 pif3 pif2 pif1 pif0 lviif wdtiif address: fffe1h after reset: 00h r/w symbol <7> 6 5 <4> <3> <2> <1> <0> if0h sreif0 0 0 dmaif1 dmaif0 sreif3 srif3 stif3 address: fffe2h after reset: 00h r/w symbol <7> <6> <5> <4> 3 <2> <1> <0> if1l tmif03 tmif02 tmif01 tmif00 0 sreif1 srif1 csiif10 iicif10 stif1 address: fffe3h after reset: 00h r/w symbol <7> <6> <5> <4> 3 <2> <1> <0> if1h tmif04 sreif2 srif2 csiif20 iicif20 stif2 0 rtciif rtcif adif address: fffd0h after reset: 00h r/w symbol 7 6 5 <4> <3> <2> <1> <0> if2l 0 0 0 pif7 pif6 tmif07 tmif06 tmif05 address: fffd1h after reset: 00h r/w symbol 7 6 <5> <4> <3> <2> <1> 0 if2h 0 0 mdif tmif13 tmif12 tmif11 tmif10 0 xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status caution be sure to clear bits 5, 6 of if 0h, bit 3 of if1l, bit 3 of if1h, bits 5 to 7 of if2l, bits 0, 6, 7 of if2h to 0.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 750 jun 20, 2011 figure 19-3. format of interrupt request flag regist ers (if0l, if0h, if1l, if1h , if2l, if2h) (78k0r/lg3) address: fffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l pif5 pif4 pif3 pif2 pif1 pif0 lviif wdtiif address: fffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h sreif0 srif0 csiif00 stif0 dmaif1 dmaif0 sreif3 srif3 stif3 address: fffe2h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if1l tmif03 tmif02 tmif01 tmif00 iicaif sreif1 srif1 csiif10 iicif10 stif1 address: fffe3h after reset: 00h r/w symbol <7> <6> <5> <4> 3 <2> <1> <0> if1h tmif04 sreif2 srif2 csiif20 iicif20 stif2 0 rtciif rtcif adif address: fffd0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if2l pif10 pif9 pif8 pif7 pif6 tmif07 tmif06 tmif05 address: fffd1h after reset: 00h r/w symbol 7 6 <5> <4> <3> <2> <1> <0> if2h 0 0 mdif tmif13 tmif12 tmif11 tmif10 pif11 xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status caution be sure to clear bit 3 of if1h, bits 6, 7 of if2h to 0.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 751 jun 20, 2011 figure 19-4. format of interrupt request flag regist ers (if0l, if0h, if1l, if1h , if2l, if2h) (78k0r/lh3) address: fffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l pif5 pif4 pif3 pif2 pif1 pif0 lviif wdtiif address: fffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h sreif0 csiif01 srif0 csiif00 stif0 dmaif1 dmaif0 sreif3 srif3 stif3 address: fffe2h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if1l tmif03 tmif02 tmif01 tmif00 iicaif sreif1 srif1 csiif10 iicif10 stif1 address: fffe3h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if1h tmif04 sreif2 srif2 csiif20 iicif20 stif2 krif rtciif rtcif adif address: fffd0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if2l pif10 pif9 pif8 pif7 pif6 tmif07 tmif06 tmif05 address: fffd1h after reset: 00h r/w symbol 7 6 <5> <4> <3> <2> <1> <0> if2h 0 0 mdif tmif13 tmif12 tmif11 tmif10 pif11 xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status caution be sure to clear bi ts 6, 7 of if2h to 0.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 752 jun 20, 2011 (2) interrupt mask flag registers (mk 0l, mk0h, mk1l, mk1h, mk2l, mk2h) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. mk0l, mk0h, mk1l, mk1h, mk2l, and mk2h can be set by a 1-bit or 8-bit memory manipulation instruction. when mk0l and mk0h, mk1l and mk1h, and mk2l and mk2h are combined to form 16-bit registers mk0, mk1, and mk2, they can be set by a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. remark if an instruction that writes data to this register is execut ed, the number of instru ction execution clocks increases by 2 clocks. figure 19-5. format of interrupt mask flag register s (mk0l, mk0h, mk1l, mk1h, mk2l, mk2h) (78k0r/lf3) address: fffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk wdtimk address: fffe5h after reset: ffh r/w symbol <7> 6 5 <4> <3> <2> <1> <0> mk0h sremk0 1 1 dmamk1 dmamk0 sremk3 srmk3 stmk3 address: fffe6h after reset: ffh r/w symbol <7> <6> <5> <4> 3 <2> <1> <0> mk1l tmmk03 tmmk02 tmmk01 tmmk00 1 sremk1 srmk1 csimk10 iicmk10 stmk1 address: fffe7h after reset: ffh r/w symbol <7> <6> <5> <4> 3 <2> <1> <0> mk1h tmmk04 sremk2 srmk2 csimk20 iicmk20 stmk2 1 rtcimk rtcmk admk address: fffd4h after reset: ffh r/w symbol 7 6 5 <4> <3> <2> <1> <0> mk2l 1 1 1 pmk7 pmk6 tmmk07 tmmk06 tmmk05 address: fffd5h after reset: ffh r/w symbol 7 6 <5> <4> <3> <2> <1> 0 mk2h 1 1 mdmk tmmk13 tmmk12 tmmk11 tmmk10 1 xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled caution be sure to set bits 5, 6 of mk 0h, bit 3 of mk1l, bit 3 of mk1h, bits 5 to 7 of mk2l, bits 0, 6, 7 of mk2h to 1.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 753 jun 20, 2011 figure 19-6. format of interrupt mask flag register s (mk0l, mk0h, mk1l, mk1h, mk2l, mk2h) (78k0r/lg3) address: fffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk wdtimk address: fffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h sremk0 srmk0 csimk00 stmk0 dmamk1 dmamk0 sremk3 srmk3 stmk3 address: fffe6h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk1l tmmk03 tmmk02 tmmk01 tmmk00 iicamk sremk1 srmk1 csimk10 iicmk10 stmk1 address: fffe7h after reset: ffh r/w symbol <7> <6> <5> <4> 3 <2> <1> <0> mk1h tmmk04 sremk2 srmk2 csimk20 iicmk20 stmk2 1 rtcimk rtcmk admk address: fffd4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk2l pmk10 pmk9 pmk8 pmk7 pmk6 tmmk07 tmmk06 tmmk05 address: fffd5h after reset: ffh r/w symbol 7 6 <5> <4> <3> <2> <1> <0> mk2h 1 1 mdmk tmmk13 tmmk12 tmmk11 tmmk10 pmk11 xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled caution be sure to set bit 3 of mk 1h, bits 6, 7 of mk2h to 1.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 754 jun 20, 2011 figure 19-7. format of interrupt mask flag register s (mk0l, mk0h, mk1l, mk1h, mk2l, mk2h) (78k0r/lh3) address: fffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk wdtimk address: fffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h sremk0 csimk01 srmk0 csimk00 stmk0 dmamk1 dmamk0 sremk3 srmk3 stmk3 address: fffe6h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk1l tmmk03 tmmk02 tmmk01 tmmk00 iicamk sremk1 srmk1 csimk10 iicmk10 stmk1 address: fffe7h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk1h tmmk04 sremk2 srmk2 csimk20 iicmk20 stmk2 krmk rtcimk rtcmk admk address: fffd4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk2l pmk10 pmk9 pmk8 pmk7 pmk6 tmmk07 tmmk06 tmmk05 address: fffd5h after reset: ffh r/w symbol 7 6 <5> <4> <3> <2> <1> <0> mk2h 1 1 mdmk tmmk13 tmmk12 tmmk11 tmmk10 pmk11 xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled caution be sure to set bits 6, 7 of mk2h to 1.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 755 jun 20, 2011 (3) priority specification flag re gisters (pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, pr12h) the priority specification flag regist ers are used to set the corresponding maskable interrupt priority level. a priority level is set by using the pr0xy and pr1xy regi sters in combination (xy = 0l, 0h, 1l, 1h, 2l, or 2h). pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr 10h, pr11l, pr11h, pr12l, and pr12h can be set by a 1-bit or 8-bit memory manipulation instruction. if pr00l and pr00h, pr01l and pr01h, pr02l and pr02h, pr10l and pr10h, pr11l and pr11h, and pr12l and pr12h are combined to form 16-bit registers pr00, pr01, pr02, pr10, pr11, and pr12, they can be set by a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. remark if an instruction that writes data to this register is execut ed, the number of instru ction execution clocks increases by 2 clocks. figure 19-8. format of priority specification flag registers (pr00l , pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12 l, pr12h) (78k0r/lf3) (1/2) address: fffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr00l ppr05 ppr04 ppr03 ppr02 ppr01 ppr00 lvipr0 wdtipr0 address: fffech after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr10l ppr15 ppr14 ppr13 ppr12 ppr11 ppr10 lvipr1 wdtipr1 address: fffe9h after reset: ffh r/w symbol <7> 6 5 <4> <3> <2> <1> <0> pr00h srepr00 1 1 dmapr01 dmapr00 srepr03 srpr03 stpr03 address: fffedh after reset: ffh r/w symbol <7> 6 5 <4> <3> <2> <1> <0> pr10h srepr10 1 1 dmapr11 dmapr10 srepr13 srpr13 stpr13 address: fffeah after reset: ffh r/w symbol <7> <6> <5> <4> 3 <2> <1> <0> pr01l tmpr003 tmpr002 tmpr001 tmpr000 1 srepr01 srpr01 csipr010 iicpr010 stpr01 address: fffeeh after reset: ffh r/w symbol <7> <6> <5> <4> 3 <2> <1> <0> pr11l tmpr103 tmpr102 tmpr101 tmpr100 1 srepr11 srpr11 csipr110 iicpr110 stpr11 caution be sure to set bits 5, 6 of pr00h and pr10h, bit 3 of pr01l and pr11l to 1.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 756 jun 20, 2011 figure 19-8. format of priority specification flag registers (pr00l , pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12 l, pr12h) (78k0r/lf3) (2/2) address: fffebh after reset: ffh r/w symbol <7> <6> <5> <4> 3 <2> <1> <0> pr01h tmpr004 srepr02 srpr02 csipr020 iicpr020 stpr02 1 rtcipr0 rtcpr0 adpr0 address: fffefh after reset: ffh r/w symbol <7> <6> <5> <4> 3 <2> <1> <0> pr11h tmpr104 srepr12 srpr12 csipr120 iicpr120 stpr12 1 rtcipr1 rtcpr1 adpr1 address: fffd8h after reset: ffh r/w symbol 7 6 5 <4> <3> <2> <1> <0> pr02l 1 1 1 ppr07 ppr06 tmpr007 tmpr006 tmpr005 address: fffdch after reset: ffh r/w symbol 7 6 5 <4> <3> <2> <1> <0> pr12l 1 1 1 ppr17 ppr16 tmpr107 tmpr106 tmpr105 address: fffd9h after reset: ffh r/w symbol 7 6 <5> <4> <3> <2> <1> 0 pr02h 1 1 mdpr0 tmpr013 tmpr012 tmpr011 tmpr010 1 address: fffddh after reset: ffh r/w symbol 7 6 <5> <4> <3> <2> <1> 0 pr12h 1 1 mdpr1 tmpr113 tmpr112 tmpr111 tmpr110 1 xxpr1x xxpr0x priority level selection 0 0 specify level 0 (high priority level) 0 1 specify level 1 1 0 specify level 2 1 1 specify level 3 (low priority level) caution be sure to set bit 3 of pr01h and pr11h, bits 5 to 7 of pr02l and pr12l, bits 0, 6, 7 of pr02h and pr12h to 1.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 757 jun 20, 2011 figure 19-9. format of priority specification flag registers (pr00l , pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12 l, pr12h) (78k0r/lg3) (1/2) address: fffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr00l ppr05 ppr04 ppr03 ppr02 ppr01 ppr00 lvipr0 wdtipr0 address: fffech after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr10l ppr15 ppr14 ppr13 ppr12 ppr11 ppr10 lvipr1 wdtipr1 address: fffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr00h srepr00 srpr00 csipr000 stpr00 dmapr01 dmapr00 srepr03 srpr03 stpr03 address: fffedh after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr10h srepr10 srpr10 csipr100 stpr10 dmapr11 dmapr10 srepr13 srpr13 stpr13 address: fffeah after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr01l tmpr003 tmpr002 tmpr001 tmpr000 iicapr0 srepr01 srpr01 csipr010 iicpr010 stpr01 address: fffeeh after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr11l tmpr103 tmpr102 tmpr101 tmpr100 iicapr1 srepr11 srpr11 csipr110 iicpr110 stpr11
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 758 jun 20, 2011 figure 19-9. format of priority specification flag registers (pr00l , pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12 l, pr12h) (78k0r/lg3) (2/2) address: fffebh after reset: ffh r/w symbol <7> <6> <5> <4> 3 <2> <1> <0> pr01h tmpr004 srepr02 srpr02 csipr020 iicpr020 stpr02 1 rtcipr0 rtcpr0 adpr0 address: fffefh after reset: ffh r/w symbol <7> <6> <5> <4> 3 <2> <1> <0> pr11h tmpr104 srepr12 srpr12 csipr120 iicpr120 stpr12 1 rtcipr1 rtcpr1 adpr1 address: fffd8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr02l ppr010 ppr09 ppr08 ppr07 ppr06 tmpr007 tmpr006 tmpr005 address: fffdch after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr12l ppr110 ppr19 ppr18 ppr17 ppr16 tmpr107 tmpr106 tmpr105 address: fffd9h after reset: ffh r/w symbol 7 6 <5> <4> <3> <2> <1> <0> pr02h 1 1 mdpr0 tmpr013 tmpr012 tmpr011 tmpr010 ppr011 address: fffddh after reset: ffh r/w symbol 7 6 <5> <4> <3> <2> <1> <0> pr12h 1 1 mdpr1 tmpr113 tmpr112 tmpr111 tmpr110 ppr111 xxpr1x xxpr0x priority level selection 0 0 specify level 0 (high priority level) 0 1 specify level 1 1 0 specify level 2 1 1 specify level 3 (low priority level) caution be sure to set bit 3 of pr01h and pr 11h, bits 6, 7 of pr02h and pr12h to 1.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 759 jun 20, 2011 figure 19-10. format of priority specification flag registers (pr00l , pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12 l, pr12h) (78k0r/lh3) (1/2) address: fffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr00l ppr05 ppr04 ppr03 ppr02 ppr01 ppr00 lvipr0 wdtipr0 address: fffech after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr10l ppr15 ppr14 ppr13 ppr12 ppr11 ppr10 lvipr1 wdtipr1 address: fffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr00h srepr00 csipr001 srpr00 csipr000 stpr00 dmapr01 dmapr00 srepr03 srpr03 stpr03 address: fffedh after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr10h srepr10 csipr101 srpr10 csipr100 stpr10 dmapr11 dmapr10 srepr13 srpr13 stpr13 address: fffeah after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr01l tmpr003 tmpr002 tmpr001 tmpr000 iicapr0 srepr01 srpr01 csipr010 iicpr010 stpr01 address: fffeeh after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr11l tmpr103 tmpr102 tmpr101 tmpr100 iicapr1 srepr11 srpr11 csipr110 iicpr110 stpr11
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 760 jun 20, 2011 figure 19-10. format of priority specification flag registers (pr00l , pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12 l, pr12h) (78k0r/lh3) (2/2) address: fffebh after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr01h tmpr004 srepr02 srpr02 csipr020 iicpr020 stpr02 krpr0 rtcipr0 rtcpr0 adpr0 address: fffefh after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr11h tmpr104 srepr12 srpr12 csipr120 iicpr120 stpr12 krpr1 rtcipr1 rtcpr1 adpr1 address: fffd8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr02l ppr010 ppr09 ppr08 ppr07 ppr06 tmpr007 tmpr006 tmpr005 address: fffdch after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr12l ppr110 ppr19 ppr18 ppr17 ppr16 tmpr107 tmpr106 tmpr105 address: fffd9h after reset: ffh r/w symbol 7 6 <5> <4> <3> <2> <1> <0> pr02h 1 1 mdpr0 tmpr013 tmpr012 tmpr011 tmpr010 ppr011 address: fffddh after reset: ffh r/w symbol 7 6 <5> <4> <3> <2> <1> <0> pr12h 1 1 mdpr1 tmpr113 tmpr112 tmpr111 tmpr110 ppr111 xxpr1x xxpr0x priority level selection 0 0 specify level 0 (high priority level) 0 1 specify level 1 1 0 specify level 2 1 1 specify level 3 (low priority level) caution be sure to set bits 6, 7 of pr02h and pr12h to 1. (4) external interrupt rising edge en able registers (egp0, egp1), external interrupt falling edge enable registers (egn0, egn1) these registers specify the valid edge for intp0 to intp11. egp0, egp1, egn0, and egn1 can be set by a 1-bi t or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 761 jun 20, 2011 figure 19-11. format of external interrupt rising edge en able registers (egp0, egp1 ) and external interrupt falling edge enable register s (egn0, egn1) (78k0r/lf3) address: fff38h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp0 egp7 egp6 egp5 egp4 egp3 egp2 egp1 egp0 address: fff39h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn0 egn7 egn6 egn5 egn4 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 7) 0 0 edge detection disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges figure 19-12. format of external interrupt rising edge en able registers (egp0, egp1 ) and external interrupt falling edge enable registers (egn 0, egn1) (78k0r/lg3, 78k0r/lh3) address: fff38h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp0 egp7 egp6 egp5 egp4 egp3 egp2 egp1 egp0 address: fff39h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn0 egn7 egn6 egn5 egn4 egn3 egn2 egn1 egn0 address: fff3ah after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp1 0 0 0 0 egp11 egp10 egp9 egp8 address: fff3bh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn1 0 0 0 0 egn11 egn10 egn9 egn8 egpn egnn intpn pin valid edge selection (n = 0 to 11) 0 0 edge detection disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges table 19-3 shows the ports corresponding to egpn and egnn.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 762 jun 20, 2011 table 19-3. ports correspo nding to egpn and egnn detection enable register edge detection port interrupt request signal lf3 lg3 lh3 egp0 egn0 p120 intp0 egp1 egn1 p30 intp1 egp2 egn2 p31 intp2 egp3 egn3 p33 intp3 egp4 egn4 p14 intp4 egp5 egn5 p32 intp5 egp6 egn6 p11 intp6 egp7 egn7 p15 intp7 egp8 egn8 p34 intp8 ? egp9 egn9 p81 intp9 ? egp10 egn10 p16 intp10 ? egp11 egn11 p80 intp11 ? caution select the port mode by clearing egpn a nd egnn to 0 because an edge may be detected when the external interrupt function is switched to the port function. remark n = 0 to 11
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 763 jun 20, 2011 (5) program status word (psw) the program status word is a register used to hold the instruction executio n result and the current status for an interrupt request. the ie flag that sets maskable interr upt enable/disable and the isp0 and isp1 flags that controls multiple interrupt servicing are mapped to the psw. besides 8-bit read/write, this register can carry out operations using bit m anipulation instructions and dedicated instructions (ei and di). when a vector ed interrupt request is acknowledged, if the brk instructio n is executed, the contents of the psw are automatic ally saved into a stack and the ie flag is re set to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of the ack nowledged interrupt are transferred to the isp0 and isp1 flags. the psw contents are also saved in to the stack with the push psw instruction. they are restored from the stack with the ret i, retb, and pop psw instructions. reset signal generation sets psw to 06h. figure 19-13. configuration of program status word <7> ie <6> z <5> rbs1 <4> ac <3> rbs0 <2> isp1 <1> isp0 0 cy psw after reset 06h isp1 0 0 1 1 enables interrupt of level 0 (while interrupt of level 1 or 0 is being serviced). enables interrupt of level 0 and 1 (while interrupt of level 2 is being serviced). enables interrupt of level 0 to 2 (while interrupt of level 3 is being serviced). enables all interrupts (waits for acknowledgment of an interrupt). ie 0 1 disabled enabled priority of interrupt currently being serviced interrupt request acknowledgment enable/disable used when normal instruction is executed isp0 0 1 0 1
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 764 jun 20, 2011 19.4 interrupt servicing operations 19.4.1 maskable interrupt acknowledgment a maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cl eared to 0. a vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the ie flag is set to 1). howeve r, a low-priority interrupt r equest is not acknowledged during servicing of a higher priority interrupt request. the times from generation of a maskable interrupt request unt il vectored interrupt servicing is performed are listed in table 19-4 below. for the interrupt request acknowledgment timing, see figures 19-15 and 19-16 . table 19-4. time from generation of maskable inte rrupt until servicing minimum time maximum time note servicing time 9 clocks 14 clocks note if an interrupt request is generated just before the ret instruction, the wait time becomes longer. remark 1 clock: 1/f clk (f clk : cpu clock) if two or more maskable interrupt requests are generated si multaneously, the request with a higher priority level specified in the priority specification flag is acknowledged fi rst. if two or more interrupts requests have the same priority level, the request with the highest defau lt priority is acknowledged first. an interrupt request that is held pending is a cknowledged when it becomes acknowledgeable. figure 19-14 shows the interrupt requ est acknowledgment algorithm. if a maskable interrupt request is ackno wledged, the contents are sa ved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the priority specification flag corre sponding to the acknowledged interrupt are transferred to the isp1 and isp0 flags. the vector table dat a determined for each interrupt request is the loaded into the pc and branched. restoring from an interrupt is possible by using the reti instruction.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 765 jun 20, 2011 figure 19-14. interrupt request acknowledgment pr ocessing algorithm yes no yes no yes no no yes no ie = 1? vectored interrupt servicing start if = 1? mk = 0? ( pr 1, pr 0) (isp1, isp0) yes (interrupt request generation) no (low priority) interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending higher priority than other interrupt requests simultaneously generated? higher default priority note than other interrupt requests simultaneously generated? if: interrupt request flag mk: interrupt mask flag pr0: priority specification flag 0 pr1: priority specification flag 1 ie: flag that controls acknowledgment of mask able interrupt request (1 = enable, 0 = disable) isp0, isp1: flag that indicates the priority leve l of the interrupt currently being serviced (see figure 19-8 ) note for the default priority, refer to table 19-1 interrupt source list .
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 766 jun 20, 2011 figure 19-15. interrupt request a cknowledgment timing (minimum time) 9 clocks instruction instruction cpu processing if 6 clocks psw and pc saved, jump to interrupt servicing interrupt servicing program remark 1 clock: 1/f clk (f clk : cpu clock) figure 19-16. interrupt request a cknowledgment timing (maximum time) 14 clocks instruction ret instruction cpu processing if 6 clocks 6 clocks psw and pc saved, jump to interrupt servicing interrupt servicing program remark 1 clock: 1/f clk (f clk : cpu clock) 19.4.2 software interrupt request acknowledgment a software interrupt acknowledge is acknowledged by br k instruction execution. software interrupts cannot be disabled. if a software interrupt request is acknowledged, the content s are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and the contents of the vector table (0007eh, 0007fh) are loaded into the pc and branched. restoring from a software interrupt is possi ble by using the retb instruction. caution do not use the reti instruction fo r restoring from the software interrupt.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 767 jun 20, 2011 19.4.3 multiple interrupt servicing multiple interrupt servicing occurs when another interrupt re quest is acknowledged during execution of an interrupt. multiple interrupt servicing does not occur unless the interr upt request acknowledgment ena bled state is selected (ie = 1). when an interrupt request is acknowledged, interrupt requ est acknowledgment becomes disabled (ie = 0). therefore, to enable multiple interrupt servicing, it is necessary to set (1) the ie flag with the ei inst ruction during interrupt servici ng to enable interrupt acknowledgment. moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority c ontrol and programmable priority control. programmable priority control is used for multiple interrupt servicing. in the interrupt enabled state, if an interr upt request with a priority equal to or hi gher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple inte rrupt servicing. if an interrupt with a priority lower than t hat of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrup t servicing. interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. when servicing of the current interrupt ends, t he pending interrupt request is acknowledged following execution of at least one main processing instruction execution. table 19-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and figure 19-17 shows multiple interrupt servicing examples. table 19-5. relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servicing maskable interrupt request priority level 0 (pr = 00) priority level 1 (pr = 01) priority level 2 (pr = 10) priority level 3 (pr = 11) multiple interrupt request interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 ie = 1 ie = 0 ie = 1 ie = 0 software interrupt request isp1 = 0 isp0 = 0 { { isp1 = 0 isp0 = 1 { { { isp1 = 1 isp0 = 0 { { { { maskable interrupt isp1 = 1 isp0 = 1 { { { { { software interrupt { { { { { remarks 1. { : multiple interrupt servicing enabled 2. : multiple interrupt servicing disabled 3. isp0, isp1, and ie are flags contained in the psw. isp1 = 0, isp0 = 0: an interrupt of level 1 or level 0 is being serviced. isp1 = 0, isp0 = 1: an interrupt of level 2 is being serviced. isp1 = 1, isp0 = 0: an interrupt of level 3 is being serviced. isp1 = 1, isp0 = 1: wait for an interrupt acknowledgment. ie = 0: interrupt request acknowledgment is disabled. ie = 1: interrupt request acknowledgment is enabled. 4. pr is a flag contained in pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, and pr12h. pr = 00: specify level 0 with pr1 = 0, pr0 = 0 (higher priority level) pr = 01: specify level 1 with pr1 = 0, pr0 = 1 pr = 10: specify level 2 with pr1 = 1, pr0 = 0 pr = 11: specify level 1 with pr1 = 1, pr0 = 1 (lower priority level)
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 768 jun 20, 2011 figure 19-17. examples of multip le interrupt se rvicing (1/2) example 1. multiple inte rrupt servicing occurs twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 11) intyy (pr = 10) intzz (pr = 01) ie = 0 ie = 0 ie = 0 ie = 1 ie = 1 ie = 1 during servicing of interrupt intxx, two interrupt requests , intyy and intzz, are acknowl edged, and multiple interrupt servicing takes place. before each interrupt request is ackn owledged, the ei instruction must always be issued to enable interrupt request acknowledgment. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 10) intyy (pr = 11) ei reti ie = 0 ie = 0 ei 1 instruction execution reti ie = 1 ie = 1 interrupt request intyy issued during servicing of interrupt in txx is not acknowledged because its priority is lower than that of intxx, and multiple interrupt se rvicing does not take place. the int yy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 00: specify level 0 with pr1 = 0, pr0 = 0 (higher priority level) pr = 01: specify level 1 with pr1 = 0, pr0 = 1 pr = 10: specify level 2 with pr1 = 1, pr0 = 0 pr = 11: specify level 1 with pr1 = 1, pr0 = 1 (lower priority level) ie = 0: interrupt request acknowledgment is disabled ie = 1: interrupt request acknowledgment is enabled.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 769 jun 20, 2011 figure 19-17. examples of multip le interrupt se rvicing (2/2) example 3. multiple interrupt servicing do es not occur because inte rrupts are not enabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 11) intyy (pr = 00) ie = 0 ie = 0 ie = 1 ie = 1 interrupts are not enabled during servicing of interrupt intxx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt servicing do es not take place. the intyy interrupt request is held pending, and is acknowledged following executi on of one main processing instruction. pr = 00: specify level 0 with pr1 = 0, pr0 = 0 (higher priority level) pr = 01: specify level 1 with pr1 = 0, pr0 = 1 pr = 10: specify level 2 with pr1 = 1, pr0 = 0 pr = 11: specify level 1 with pr1 = 1, pr0 = 1 (lower priority level) ie = 0: interrupt request acknowledgment is disabled ie = 1: interrupt request acknowledgment is enabled.
78k0r/lx3 chapter 19 interrupt functions r01uh0004ej0501 rev.5.01 770 jun 20, 2011 19.4.4 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending un til the end of executi on of the next instruction. t hese instructions (interrupt request hold instructions) are listed below. ? mov psw, #byte ? mov psw, a ? mov1 psw. bit, cy ? set1 psw. bit ? clr1 psw. bit ? retb ? reti ? pop psw ? btclr psw. bit, $addr8 ? ei ? di ? skc ? sknc ? skz ? sknz ? manipulation instructions for the if0l, if0h, if1l, if1h, if2l, if2h, mk0l, mk0h, mk1l, mk1h, mk2l, mk2h, pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr 10h, pr11l, pr11h, pr12l, and pr12h registers. caution the brk instruction is not one of the above-listed interrupt requ est hold instructions. however, the software interrupt activated by executing the brk instruction causes th e ie flag to be cleared. therefore, even if a maskable interrupt request is generated during execution of the brk instruction, the interrupt request is not acknowledged. figure 19-18 shows the timing at which interrupt requests are held pending. figure 19-18. interrupt request hold instruction n instruction m psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other t han interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (interrupt request).
78k0r/lx3 chapter 20 key interrupt function r01uh0004ej0501 rev.5.01 771 jun 20, 2011 chapter 20 key interrupt function 78k0r/lf3 78k0r/lg3 78k0r/lh3 item 80 pins 100 pins 128 pins key interrupt ? 8 ch 20.1 functions of key interrupt a key interrupt (intkr) can be generated by setting the ke y return mode register (krm) and inputting a falling edge to the key interrupt input pins (kr0 to kr7). table 20-1. assignment of k ey interrupt detection pins flag description krm0 controls kr0 signal in 1-bit units. krm1 controls kr1 signal in 1-bit units. krm2 controls kr2 signal in 1-bit units. krm3 controls kr3 signal in 1-bit units. krm4 controls kr4 signal in 1-bit units. krm5 controls kr5 signal in 1-bit units. krm6 controls kr6 signal in 1-bit units. krm7 controls kr7 signal in 1-bit units. 20.2 configuration of key interrupt the key interrupt includes the following hardware. table 20-2. configuration of key interrupt item configuration control register key return mode register (krm)
78k0r/lx3 chapter 20 key interrupt function r01uh0004ej0501 rev.5.01 772 jun 20, 2011 figure 20-1. block diag ram of key interrupt intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 20.3 register controlling key interrupt (1) key return mode register (krm) this register controls the krm0 to krm7 bits using the kr0 to kr7 signals, respectively. krm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 20-2. format of key return mode register (krm) krm7 does not detect key interrupt signal detects key interrupt signal krmn 0 1 key interrupt mode control krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 address: fff37h after reset: 00h r/w symbol 765432 0 cautions 1. if any of the krm0 to krm7 bits used is set to 1, set bits 0 to 7 (pu70 to pu77) of the corresponding pull-up resistor register 7 (pu7) to 1. 2. an interrupt will be generated if the target bit of the krm re gister is set while a low level is being input to the key interrupt input pin. to ignore th is interrupt, set the krm register after disabling interrupt servicing by using the in terrupt mask flag. afterward, clear the interrupt request flag and enable interrupt servicing after waiting for the key interrupt input low- level width (250 ns or more). 3. the bits not used in the key inte rrupt mode can be used as normal ports. remark n = 0 to 7
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 773 jun 20, 2011 chapter 21 standby function 21.1 standby function and configuration 21.1.1 standby function the standby function is mounted onto all 78k0r/lx3 microcontroller products. the standby function reduces the operat ing current of the system, and the fo llowing two modes are available. (1) halt mode halt instruction execution sets the halt mode. in the ha lt mode, the cpu operation cl ock is stopped. if the high- speed system clock oscillator, internal high-speed oscillator, 20 mhz internal high-speed oscillator, or subsystem clock oscillator is operating before the halt mode is set, oscillation of each clock continues. in this mode, the operating current is not decreased as much as in the stop mode, but the halt mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations frequently. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the high-speed system clock oscillator and internal high-speed oscillator stop, stopping the whole s ystem, thereby considerably reducing the cpu operating current. because this mode can be cleared by an interrupt reques t, it enables intermittent operations to be carried out. however, because a wait time is required to secure the o scillation stabilization time after the stop mode is released when the x1 clock is selected, select t he halt mode if it is necessary to star t processing immediately upon interrupt request generation. in either of these two modes, all the co ntents of registers, flags and data memo ry just before the standby mode is set are held. the i/o port output latches and output buffer statuses are also held. cautions 1. the stop mode can be used only when the cpu is operat ing on the main system clock. the stop mode cannot be set while the cpu operat es with the subsystem cl ock. the halt mode can be used when the cpu is operating on either the main system clock or the subsystem clock. 2. when shifting to the stop mode, be sure to stop the peripheral hard ware operation operating with main system clock before executing stop instruction. 3. the following sequence is recommended for ope rating current reductio n of the a/d converter when the standby function is u sed: first clear bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0 to stop the a/d c onversion operation, and then execute the stop instruction. 4. it can be selected by the option byte whether th e internal low-speed oscillator continues oscillating or stops in the halt or stop mode. fo r details, see chapter 26 option byte. 5. the stop instruction cannot be executed when the cpu operat es on the 20 mhz internal high- speed oscillation clock. be sure to execute the stop inst ruction after shifting to internal high- speed oscillation clock operation. 21.1.2 registers controlling standby function the standby function is controlled by the following two registers. ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) remark for the registers that start, st op, or select the clock, see chapter 5 clock generator .
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 774 jun 20, 2011 (1) oscillation stabilization time c ounter status register (ostc) this is the register that indicates the count status of the x1 clock osci llation stabilization time counter. the x1 clock oscillation stabilization time can be checked in the following case, ? if the x1 clock starts oscillation while the internal hi gh-speed oscillation clock or subsystem clock is being used as the cpu clock. ? if the stop mode is entered and then re leased while the internal high-speed oscillation clock is being used as the cpu clock with the x1 clock oscillating. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lvi, wdt, and executing an illegal instruction), the stop instruction and mstop (bit 7 of csc regist er) = 1 clear this register to 00h. figure 21-1. format of oscillation stabilizati on time counter status register (ostc) address: fffa2h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc most 8 most 9 most 10 most 11 most 13 most 15 most 17 most 18 oscillation stabilization time status most 8 most 9 most 10 most 11 most 13 most 15 most 17 most 18 f x = 10 mhz f x = 20 mhz 0 0 0 0 0 0 0 0 2 8 /f x max. 25.6 s max. 12.8 s max. 1 0 0 0 0 0 0 0 2 8 /f x min. 25.6 s min. 12.8 s min. 1 1 0 0 0 0 0 0 2 9 /f x min. 51.2 s min. 25.6 s min. 1 1 1 0 0 0 0 0 2 10 /f x min. 102.4 s min. 51.2 s min. 1 1 1 1 0 0 0 0 2 11 /f x min. 204.8 s min. 102.4 s min. 1 1 1 1 1 0 0 0 2 13 /f x min. 819.2 s min. 409.6 s min. 1 1 1 1 1 1 0 0 2 15 /f x min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 1 1 0 2 17 /f x min. 13.11 ms min. 6.55 ms min. 1 1 1 1 1 1 1 1 2 18 /f x min. 26.21 ms min. 13.11 ms min. cautions 1. after the above time has elapsed, the bits are set to 1 in order from most8 and remain 1. 2. the oscillation stabilization time count er counts up to the oscillation stabilization time set by osts. if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 3. the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 775 jun 20, 2011 (2) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillation stabilization wait time when the stop mode is released. when the x1 clock is selected as the cpu clock, the oper ation waits for the time set using osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confi rm with ostc that the desired oscillation stabilization time has elapsed after the stop m ode is released. the oscillati on stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 07h. figure 21-2. format of oscillation stabiliz ation time select register (osts) address: fffa3h after reset: 07h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 oscillation stabilization time selection osts2 osts1 osts0 f x = 10 mhz f x = 20 mhz 0 0 0 2 8 /f x 25.6 s setting prohibited 0 0 1 2 9 /f x 51.2 s 25.6 s 0 1 0 2 10 /f x 102.4 s 51.2 s 0 1 1 2 11 /f x 204.8 s 102.4 s 1 0 0 2 13 /f x 819.2 s 409.6 s 1 0 1 2 15 /f x 3.27 ms 1.64 ms 1 1 0 2 17 /f x 13.11 ms 6.55 ms 1 1 1 2 18 /f x 26.21 ms 13.11 ms cautions 1. to set the stop mode wh en the x1 clock is used as the cp u clock, set osts before executing the stop instruction. 2. setting the oscillation stabilization time to 20 s or less is prohibited. 3. before changing the setting of the osts regi ster, confirm that the count operation of the ostc register is completed. 4. do not change the value of the osts regist er during the x1 clock oscillation stabilization time. 5. the oscillation stabilization time counter count s up to the oscillation stabilization time set by osts. if the stop mode is en tered and then released while the internal high-speed oscillation clock is being used as the cp u clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the o scillation stabilization time set by osts is set to ostc after stop mode is released. 6. the x1 clock oscillation stabilization wait ti me does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 776 jun 20, 2011 21.2 standby function operation 21.2.1 halt mode (1) halt mode the halt mode is set by executing t he halt instruction. ha lt mode can be set regardless of whether the cpu clock before the setting was the high-speed system clock, in ternal high-speed oscillation clock, 20 mhz internal high- speed oscillation clock, or subsystem clock. the operating statuses in t he halt mode are shown below.
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 777 jun 20, 2011 table 21-1. operating statuses in halt mode (1/3) when halt instruction is executed while cpu is operating on main system clock halt mode setting item when cpu is operating on internal high-speed oscillation clock (f ih ) or 20 mhz internal high-speed oscillation clock (f ih20 ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f ex ) system clock clock supply to the cpu is stopped f ih operation continues (cannot be stopped) status before halt mode was set is retained f x operation continues (cannot be stopped) cannot operate main system clock f ex status before halt mode was set is retained cannot operate operation continues (cannot be stopped) subsystem clock f xt status before halt mode was set is retained f il set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: oscillates ? wton = 1 and wdstbyon = 0: stops cpu operation stopped flash memory operation stopped ram status before halt mode was set is retained at voltage higher than poc detection voltage. port (latch) status before halt mode was set is retained timer array unit (tau) real-time counter (rtc) operable watchdog timer set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: operates ? wton = 1 and wdstbyon = 0: stops clock output/buzzer output a/d converter d/a converter operational amplifier voltage reference serial array unit (sau) serial interface (iica) lcd controller/driver multiplier/divider dma controller power-on-clear function low-voltage detection function external interrupt key interrupt operable remarks 1. f ih : internal high-speed oscillation clock, f ih20 : 20 mhz internal high-speed oscillation clock f x : x1 oscillation clock, f ex : external main system clock f xt : xt1 oscillation clock, f il : internal low-speed oscillation clock 2. the functions mounted depend on the product. refer to 1.4 block diagram and 1.5 outline of functions .
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 778 jun 20, 2011 table 21-1. operating statuses in halt mode (2/3) when halt instruction is executed while cpu is operating on subsystem clock halt mode setting item when cpu is operating on xt1 clock (f xt ) system clock clock supply to the cpu is stopped f ih f x status before halt mode was set is retained main system clock f ex operates or stops by external clock input subsystem clock f xt operation continues (cannot be stopped) f il set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: oscillates ? wton = 1 and wdstbyon = 0: stops cpu operation stopped flash memory operation stopped (wait state in low-power consumption mode) ram status before halt mode was set is retained at voltage higher than poc detection voltage. port (latch) status before halt mode was set is retained timer array unit (tau) real-time counter (rtc) operable watchdog timer set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: operates ? wton = 1 and wdstbyon = 0: stops clock output/buzzer output operable a/d converter cannot operate d/a converter operational amplifier voltage reference serial array unit (sau) operable serial interface (iica) cannot operate lcd controller/driver multiplier/divider dma controller power-on-clear function low-voltage detection function external interrupt key interrupt operable remarks 1. f ih : internal high-speed oscillation clock, f ih20 : 20 mhz internal high-speed oscillation clock f x : x1 oscillation clock, f ex : external main system clock f xt : xt1 oscillation clock, f il : internal low-speed oscillation clock 2. the functions mounted depend on the product. refer to 1.4 block diagram and 1.5 outline of functions .
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 779 jun 20, 2011 table 21-1. operating statuses in halt mode (3/3) when halt instruction is executed while cpu is operating on subsystem clock halt mode setting item when cpu is operating on xt1 clock (f xt ) (subsystem clock halt mode (rtclpc = 1)) system clock clock supply to the cpu is stopped f ih f x status before halt mode was set is retained main system clock f ex operates or stops by external clock input subsystem clock f xt operation continues (cannot be stopped) f il set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: oscillates ? wton = 1 and wdstbyon = 0: stops cpu operation stopped flash memory operation stopped (wait state in low-power consumption mode) ram status before halt mode was set is retained at voltage higher than poc detection voltage. port (latch) status before halt mode was set is retained timer array unit (tau) cannot operate real-time counter (rtc) operable watchdog timer set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: operates ? wton = 1 and wdstbyon = 0: stops clock output/buzzer output operable a/d converter d/a converter operational amplifier voltage reference serial array unit (sau) serial interface (iica) cannot operate lcd controller/driver operable multiplier/divider dma controller operation stopped power-on-clear function low-voltage detection function external interrupt key interrupt operable remarks 1. f ih : internal high-speed oscillation clock, f ih20 : 20 mhz internal high-speed oscillation clock f x : x1 oscillation clock, f ex : external main system clock f xt : xt1 oscillation clock, f il : internal low-speed oscillation clock 2. rtclpc: bit 7 of the operation speed m ode control register (osmc). 3. the functions mounted depend on the product. refer to 1.4 block diagram and 1.5 outline of functions .
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 780 jun 20, 2011 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the ha lt mode is released. if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 21-3. halt mode release by interrupt request generation halt instruction wait note operating mode halt mode operating mode oscillation status of cpu standby release signal interrupt request high-speed system clock, internal high-speed oscillation clock, 20 mhz internal high-speed oscillation clock, or subsystem clock note the wait time is as follows: ? when vectored interrupt servicing is carried out when main system clock is used: 10 to 12 clocks when subsystem clock is used: 8 to 10 clocks ? when vectored interrupt servicing is not carried out when main system clock is used: 5 or 6 clocks when subsystem clock is used: 3 or 4 clocks remark the broken lines indicate the case when the interr upt request which has released the standby mode is acknowledged.
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 781 jun 20, 2011 (b) release by reset signal generation when the reset signal is generated, halt mode is rele ased, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 21-4. halt mode release by reset (1) when high-speed system clock is used as cpu clock halt instruction reset signal high-speed system clock (x1 oscillation) halt mode reset period oscillates oscillation stopped oscillates status of cpu normal operation (high-speed system clock) oscillation stabilization time (2 8 /f x to 2 11 /f x , 2 13 /f x , 2 15 /f x , 2 17 /f x , 2 18 /f x ) normal operation (internal high-speed oscillation clock) oscillation stopped starting x1 oscillation is specified by software. reset processing (about 2.1 to 5.8 ms) (2) when internal high-speed oscilla tion clock or 20 mhz internal high-speed oscillation clo ck is used as cpu clock halt instruction reset signal normal operation (internal high-speed oscillation clock or 20 mhz internal high-speed oscillation clock) halt mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu wait for oscillation accuracy stabilization reset processing (about 2.1 to 5.8 ms) internal high-speed oscillation clock or 20 mhz internal high-speed oscillation clock (3) when subsystem clo ck is used as cpu clock halt instruction reset signal subsystem clock (xt1 oscillation) normal operation (subsystem clock) halt mode reset period normal operation mode (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stopped starting xt1 oscillation is specified by software. reset processing (about 2.1 to 5.8 ms) remark f x : x1 clock oscillation frequency
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 782 jun 20, 2011 21.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by executing t he stop instruction, and it can be se t only when the cpu clock before the setting was the main system clock. cautions 1. because the interrupt requ est signal is used to clear the sta ndby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction and th e system returns to the operating mode as soon as the wait time set using the oscillation stabilizat ion time select register (osts) has elapsed. 2. the stop instruction canno t be executed when the cpu operat es on the 20 mhz internal high- speed oscillation clock. be sure to execute the stop instructi on after shifting to internal high- speed oscillation clock operation. the operating statuses in t he stop mode are shown below.
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 783 jun 20, 2011 table 21-2. operating statuses in stop mode when stop instruction is executed while cpu is operating on main system clock stop mode setting item when cpu is operating on internal high-speed oscillation clock (f ih ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f ex ) system clock clock supply to the cpu is stopped f ih f x main system clock f ex stopped subsystem clock f xt status before stop mode was set is retained f il set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: oscillates ? wton = 1 and wdstbyon = 0: stops cpu flash memory operation stopped ram status before stop mode was set is retained at voltage higher than poc detection voltage. port (latch) status before stop mode was set is retained timer array unit (tau) cannot operate real-time counter (rtc) operable watchdog timer set by bits 0 (wdstbyon) and 4 (wton) of option byte (000c0h) ? wton = 0: stops ? wton = 1 and wdstbyon = 1: operates ? wton = 1 and wdstbyon = 0: stops clock output/buzzer output oper able only when subsystem clock is selected as the count clock a/d converter operation stopped d/a converter operational amplifier voltage reference operable serial array unit (sau) cannot operate serial interface (iica) wake-up by address match operable lcd controller/driver operable only when subsystem clock is selected as lcd source clock multiplier/divider dma controller cannot operate power-on-clear function low-voltage detection function external interrupt key interrupt operable remarks 1. f ih : internal high-speed oscillation clock, f x : x1 oscillation clock f ex : external main system clock, f xt : xt1 oscillation clock f il : internal low-speed oscillation clock 2. the functions mounted depend on the product. refer to 1.4 block diagram and 1.5 outline of functions .
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 784 jun 20, 2011 cautions 1. to use the peripheral hard ware that stops operation in the stop mode, and the peripheral hardware for which the clock that stops osc illating in the stop mode after th e stop mode is released, restart the peripheral hardware. 2. to stop the internal low-speed oscillation clock in the stop mode, use an option byte to stop the watchdog timer operation in the ha lt/stop mode (bit 0 (wdstbyon) of 000c0h = 0), and then execute the stop instruction. 3. to shorten oscillation stabilization time after the stop mode is released when the cpu operates with the high-speed system clock (x1 oscillation), te mporarily switch the cpu clock to the internal high-speed oscillation clock before the next execution of the stop inst ruction. before changing the cpu clock from the internal hi gh-speed oscillation clock to the high-speed system clock (x1 oscillation) after the stop mode is released, check th e oscillation stabilization time with the oscillation stabilization time count er status register (ostc). 4. the stop instruction cannot be executed when th e cpu operates on the 20 mh z internal high-speed oscillation clock. be sure to execu te the stop instruction after sh ifting to intern al high-speed oscillation clock operation. (2) stop mode release figure 21-5. operation timing when stop mode is released (when unmasked interrupt request is generated) stop mode stop mode release high-speed system clock (x1 oscillation) high-speed system clock (external clock input) internal high-speed oscillation clock high-speed system clock (x1 oscillation) is selected as cpu clock when stop instruction is executed high-speed system clock (external clock input) is selected as cpu clock when stop instruction is executed internal high-speed oscillation clock is selected as cpu clock when stop instruction is executed wait for oscillation accuracy stabilization halt status (oscillation stabilization time set by osts) note clock switched by software clock switched by software high-speed system clock high-speed system clock wait (2 clocks) wait (1 clock) supply of the cpu clock is stopped (about 23.3 to 30.7 s) high-speed system clock supply of the cpu clock is stopped (about 23.3 to 30.7 s) internal high-speed oscillation clock note when the oscillation stabilization time set by osts is equal to or shorter than 61 s, the halt status is retained to a maximum of "61 s + wait time." the stop mode can be released by the following two sources.
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 785 jun 20, 2011 (a) release by unmasked interrupt request when an unmasked interrupt request is ge nerated, the stop mode is released. after the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 21-6. stop mode release by interrupt request generation (1/2) (1) when high-speed system clock (x 1 oscillation) is used as cpu clock normal operation (high-speed system clock) normal operation (high-speed system clock) oscillates oscillates stop instruction stop mode wait (set by osts) standby release signal oscillation stabilization wait (halt mode status) oscillation stopped high-speed system clock (x1 oscillation) status of cpu oscillation stabilization time (set by osts) interrupt request (2) when high-speed system clock (external clock in put) is used as cpu clock interrupt request stop instruction standby release signal status of cpu high-speed system clock (external clock input) oscillates normal operation (high-speed system clock) stop mode oscillation stopped oscillates normal operation (high-speed system clock) wait (2 clocks) supply of the cpu clock is stopped (about 23.3 to 30.7 s) remark the broken lines indicate the case when the inte rrupt request that has released the standby mode is acknowledged.
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 786 jun 20, 2011 figure 21-6. stop mode release by interrupt request generation (2/2) (3) when internal high-speed osc illation clock is used as cpu clock standby release signal status of cpu internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) oscillates stop mode oscillation stopped wait for oscillation accuracy stabilization interrupt request stop instruction wait (1 clock ) normal operation (internal high-speed oscillation clock) supply of the cpu clock is stopped (about 23.3 to 30.7 s) oscillates remark the broken lines indicate the case when the inte rrupt request that has released the standby mode is acknowledged.
78k0r/lx3 chapter 21 standby function r01uh0004ej0501 rev.5.01 787 jun 20, 2011 (b) release by reset signal generation when the reset signal is generated, stop mode is rel eased, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 21-7. stop mode release by reset (1) when high-speed system clock is used as cpu clock stop instruction reset signal high-speed system clock (x1 oscillation) normal operation (high-speed system clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stabilization time (checked by using ostc register) oscillation stopped starting x1 oscillation is specified by software. oscillation stopped reset processing (about 2.1 to 5.8 ms) (2) when internal high-speed osc illation clock is used as cpu clock stop instruction reset signal internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped status of cpu oscillates oscillation stopped wait for oscillation accuracy stabilization reset processing (about 2.1 to 5.8 ms) remark f x : x1 clock oscillation frequency
78k0r/lx3 chapter 22 reset function r01uh0004ej0501 rev.5.01 788 jun 20, 2011 chapter 22 reset function the following five operations are available to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop detection (3) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (4) internal reset by comparison of supply voltage of the low-voltage detector (lvi) or input voltage (exlvi) from external input pin, and detection voltage (5) internal reset by execution of illegal instruction note external and internal resets start program execution from the address at 0000h and 0001h when the reset signal is generated. a reset is effected when a low level is input to the reset pi n, the watchdog timer overflows, or by poc and lvi circuit voltage detection or execut ion of illegal instruction note , and each item of hardware is set to the status shown in tables 22-1 and 22-2. each pin is high impedance during reset signal generat ion or during the oscillation stabilization time just after a reset release, except for p130, which is low-level output. when a low level is input to the reset pin, the device is reset. it is released fr om the reset status when a high level is input to the reset pin and program ex ecution is started with the internal high-speed oscillation clock after reset processing. a reset by the watchdog timer is automatically released, and program execution starts using the internal high- speed oscillation clock (see figures 22-2 to 22-4 ) after reset processing. reset by poc and lvi circuit power supply detection is automatically released when v dd v por or v dd v lvi after the reset, and program execution starts using the internal high-speed oscillation clock (see chapter 23 power-on-clear circuit and chapter 24 low- voltage detector ) after reset processing. note the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. cautions 1. for an external reset, input a low level for 10 s or more to the reset pin (to perform an external reset upon power application, a low l evel of at least 10 s must be continued during the period in which the s upply voltage is within the operating range (v dd 1.8 v)). 2. during reset input, the x1 clo ck, xt1 clock, internal high-speed oscillation clock, and internal low-speed oscillation clock stop o scillating. external main system clock input becomes invalid. 3. when the stop mode is released by a reset, th e ram contents in the stop mode are held during reset input. 4. when reset is effected, port pin p140 is set to low-level output and ot her port pins become high- impedance, because each sfr and 2nd sfr are initialized. remark v por : poc power supply rise detection voltage v lvi : lvi detection voltage
78k0r/lx3 chapter 22 reset function r01uh0004ej0501 rev.5.01 789 jun 20, 2011 figure 22-1. block di agram of reset function lvirf wdrf reset control flag register (resf) internal bus watchdog timer reset signal reset power-on clear circuit reset signal low-voltage detector reset signal reset signal reset signal to lvim/lvis register clear set clear set trap reset signal by execution of illegal instruction set clear resf register read signal caution an lvi circuit internal r eset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level select register
78k0r/lx3 chapter 22 reset function r01uh0004ej0501 rev.5.01 790 jun 20, 2011 figure 22-2. timing of reset by reset input delay hi-z normal operation cpu clock reset period (oscillation stop) normal operation (internal high-speed oscillation clock) reset internal reset signal port pin (except p130) port pin (p130) note high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. reset processing (about 2.1 to 5.8 ms) wait for oscillation accuracy stabilization delay (about 30 to 170 s) note set p130 to high-level output by software. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. figure 22-3. timing of reset du e to watchdog timer overflow normal operation reset period (oscillation stop) cpu clock watchdog timer overflow internal reset signal hi-z port pin (except p130) port pin (p130) note high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) wait for oscillation accuracy stabilization reset processing (about 195 to 322 s) note set p130 to high-level output by software. caution a watchdog timer internal reset resets the watchdog timer. remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal.
78k0r/lx3 chapter 22 reset function r01uh0004ej0501 rev.5.01 791 jun 20, 2011 figure 22-4. timing of reset in stop mode by reset input delay normal operation cpu clock reset period (oscillation stop) reset internal reset signal stop instruction execution stop status (oscillation stop) high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock hi-z port pin (except p130) port pin (p130) note starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) wait for oscillation accuracy stabilization reset processing (about 2.1 to 5.8 ms) delay (about 30 to 170 s) note set p130 to high-level output by software. remarks 1. when reset is effected, p130 outputs a low level. if p130 is set to output a high level before reset is effected, the output signal of p130 ca n be dummy-output as the cpu reset signal. 2. for the reset timing of the power-on-cl ear circuit and low-voltage detector, see chapter 23 power- on-clear circuit and chapter 24 low-voltage detector .
78k0r/lx3 chapter 22 reset function r01uh0004ej0501 rev.5.01 792 jun 20, 2011 table 22-1. operation st atuses during reset period item during reset period system clock clock supply to the cpu is stopped. f ih operation stopped f x operation stopped (x1 and x2 pins are input port mode) main system clock f ex clock input invalid (pin is input port mode) subsystem clock f xt operation stopped (xt1 and xt2 pins are input port mode) f il cpu flash memory operation stopped ram operation stopped (the value, however, is reta ined when the voltage is at least the power-on- clear detection voltage.) port (latch) set p130 to low-level output. the port pins except for p130 become high impedance. timer array unit (tau) real-time counter (rtc) watchdog timer clock output/buzzer output a/d converter d/a converter operational amplifier voltage reference serial array unit (sau) serial interface (iica) operation stopped lcd controller/driver operation stopped (com only pin, seg only pin, com/seg alternate pin: gnd ou tput, seg/general-purpose port alternate pin: input port, v lc0 to v lc2 pins: high-impedance output, v lc3 /p02 pin, caph/p00 pin, capl/p01 pin: input port) multiplier/divider dma controller operation stopped power-on-clear function dete ction operation possible low-voltage detection function operation stopped (however, operation continues at lvi reset) external interrupt key interrupt bcd correction circuit (bcd) operation stopped remarks 1. f ih : internal high-speed oscillation clock, f x : x1 oscillation clock f ex : external main system clock, f xt : xt1 oscillation clock f il : internal low-speed oscillation clock 2. the functions mounted depend on the product. refer to 1.4 block diagram and 1.5 outline of functions .
78k0r/lx3 chapter 22 reset function r01uh0004ej0501 rev.5.01 793 jun 20, 2011 table 22-2. hardware statuses after reset acknowledgment (1/4) hardware after reset acknowledgment note 1 program counter (pc) the contents of the reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 06h data memory undefined note 2 ram general-purpose registers undefined note 2 port registers (p0 to p15) (output latches) 00h port mode registers (pm0 to pm12, pm14, pm15) ffh port input mode registers 1, 7 (pim1, pim7) 00h port output mode registers 1, 7, 8 (pom1, pom7, pom8) 00h pull-up resistor option registers (pu0, pu1, pu3 to pu5, pu7 to pu10, pu12, pu14) 00h clock operation mode control register (cmc) 00h clock operation status control register (csc) c0h processor mode control register (pmc) 00h system clock control register (ckc) 09h 20 mhz internal high-speed oscillation control register (dscctl) 00h oscillation stabilization time counter status register (ostc) 00h oscillation stabilization time select register (osts) 07h noise filter enable registers 0, 1 (nfen0, nfen1) 00h peripheral enable registers 0 (per0) 00h operation speed mode control register (osmc) 00h input switch control register (isc) 00h timer data registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13 (tdr00, tdr01, tdr02, tdr03, tdr04, tdr05, tdr06, tdr07, tdr10, tdr11, tdr12, tdr13) 0000h timer mode registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13 (tmr00, tmr01, tmr02, tmr03, tmr04, tmr05, tmr06, tmr07, tmr10, tmr11, tmr12, tmr13) 0000h timer status registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13 (tsr00, tsr01, tsr02, tsr03, tsr04, tsr05, tsr06, tsr07, tsr10, tsr11, tsr12, tsr13) 0000h timer input select register 0, 1 (tis0, tis1) 00h timer channel counter regist ers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13 (tcr00, tcr01, tcr02, tcr03, tcr04, tcr05, tcr06, tcr07, tcr10, tcr11, tcr12, tcr13) ffffh timer channel enable status regi sters 0, 1 (te0, te1) 0000h timer array units 0, 1 (tau0, tau1) timer channel start trigger regi sters 0, 1 (ts0, ts1) 0000h notes 1. during reset signal generation or oscillation stabilizatio n time wait, only the pc contents among the hardware statuses become undefined. all other hardwar e statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. remark the sfr and 2nd sfr provided differ depending on the product. refer to 3.2.4 special function registers (sfrs) and 3.2.5 extended special function registers (2nd sfrs: 2nd special function registers) .
78k0r/lx3 chapter 22 reset function r01uh0004ej0501 rev.5.01 794 jun 20, 2011 table 22-2. hardware statuses after reset acknowledgment (2/4) hardware status after reset acknowledgment note 1 timer channel stop trigger regi sters 0, 1 (tt0, tt1) 0000h timer clock select registers 0, 1 (tps0, tps1) 0000h timer channel output regist ers 0, 1 (to0, to1) 0000h timer channel output enable regist ers 0, 1 (toe0, toe1) 0000h timer channel output level registers 0, 1 (tol0, tol1) 0000h timer array units 0, 1 (tau0, tau1) timer channel output mode regist ers 0, 1 (tom0, tom1) 0000h sub-count register (rsubc) 0000h second count register (sec) 00h minute count register (min) 00h hour count register (hour) 12h week count register (week) 00h day count register (day) 01h month count register (month) 01h year count register (year) 00h watch error correction register (subcud) 00h alarm minute register (alarmwm) 00h alarm hour register (alarmwh) 12h alarm week register (alarmww) 00h real-time counter control register 0 (rtcc0) 00h real-time counter control register 1 (rtcc1) 00h real-time counter real-time counter control register 2 (rtcc2) 00h clock output/buzzer output controller clock output select registers 0, 1 (cks0, cks1) 00h watchdog timer enable register (wdte) 1ah/9ah note 2 10-bit a/d conversion result register (adcr) 0000h 8-bit a/d conversion result register (adcrh) 00h a/d converter mode register (adm) 00h a/d converter mode register 1 (adm1) 00h analog reference voltage control register (advrc) 00h analog input channel specification register (ads) 00h a/d converter a/d port configuration register (adpc) 10h d/a conversion value setting register s w0, w1 (dacsw0, dacsw1) 0000h 8-bit d/a conversion value setting r egisters 0, 1 (dacs0, dacs1) 00h d/a converter d/a converter mode register (dam) 00h operational amplifier operational amplifier control register (oac) 00h voltage reference analog reference voltage control register (advrc) 00h notes 1. during reset signal generation or oscillation stabilizatio n time wait, only the pc contents among the hardware statuses become undefined. all other hardwar e statuses remain unchanged after reset. 2. the reset value of wdte is dete rmined by the option byte setting. remark the sfr and 2nd sfr mount ed depend on the product. refer to 3.2.4 special function registers (sfrs) and 3.2.5 extended special function register s (2nd sfrs: 2nd special function registers) .
78k0r/lx3 chapter 22 reset function r01uh0004ej0501 rev.5.01 795 jun 20, 2011 table 22-2. hardware statuses after reset acknowledgment (3/4) hardware status after reset acknowledgment note serial data registers 00, 01, 02, 03, 10, 11, 12, 13 (sdr00, sdr01, sdr02, sdr03, sdr10, sdr11, sdr12, sdr13) 0000h serial status registers 00, 01, 02, 03, 10, 11, 12, 13 (ssr00, ssr01, ssr02, ssr03, ssr10, ssr11, ssr12, ssr13) 0000h serial flag clear trigger registers 00, 01, 02, 03, 10, 11, 13 (sir00, sir01, sir02, sir03, sir10, sir11, sir13) 0000h serial mode registers 00, 01, 02, 03, 10, 11, 12, 13 (smr00, smr01, smr02, smr03, smr10, smr11, smr12, smr13) 0020h serial communication operation setting r egisters 00, 01, 02, 03, 10, 11, 12, 13 (scr00, scr01, scr02, scr03, scr10, scr11, scr12, scr13) 0087h serial channel enable status re gisters 0, 1 (se0, se1) 0000h serial channel start trigger r egisters 0, 1 (ss0, ss1) 0000h serial channel stop trigger registers 0, 1 (st0, st1) 0000h serial clock select registers 0, 1 (sps0, sps1) 0000h serial output registers 0, 1 (so0, so1) 0f0fh serial array units 0, 1 (sau0, sau1) serial output enable register s 0, 1 (soe0, soe1) 0000h shift register (iica) 00h control register 0 (iicctl0) 00h control register 1 (iicctl1) 00h slave address register (sva) 00h iica low-level width setting register 0 (iicwl) ffh iica high-level width setting register 0 (iicwh) ffh status register (iics) 00h serial interface iica flag register (iicf) 00h lcd mode register (lcdmd) 00h lcd display mode register (lcdm) 00h lcd clock control register 0 (lcdc0) 00h lcd boost level control register (vlcd) 0fh port function register (pfall) 00h segment enable register (segen) 00h lcd controller/driver input switch control register (isc) 00h multiplication/division data r egister a (mdal, mdah) 0000h multiplication/division data r egister b (mdbl, mdbh) 0000h multiplication/division data r egister c (mdcl, mdch) 0000h multiplier/divider multiplication/division control register (mduc) 00h key interrupt key return mode register (krm) 00h note during reset signal generation or oscillation stabilizat ion time wait, only the pc contents among the hardware statuses become undefined. all other hardwar e statuses remain unchanged after reset. remark the sfr and 2nd sfr mount ed depend on the product. refer to 3.2.4 special functi on registers (sfrs) and 3.2.5 extended special function register s (2nd sfrs: 2nd special function registers) .
78k0r/lx3 chapter 22 reset function r01uh0004ej0501 rev.5.01 796 jun 20, 2011 table 22-2. hardware statuses a fter reset acknowledgment (4/4) hardware status after reset acknowledgment note 1 reset function reset control flag register (resf) undefined note 2 low-voltage detection register (lvim) 00h note 3 low-voltage detector low-voltage detection level select register (lvis) 0eh note 2 sfr address registers 0, 1 (dsa0, dsa1) 00h ram address registers 0l, 0h, 1l, 1h (dra0l, dra0h, dra1l, dra1h) 00h byte count registers 0l, 0h, 1l, 1h (dbc0l, dbc0h, dbc1l, dbc1h) 00h mode control registers 0, 1 (dmc0, dmc1) 00h dma controller operation control registers 0, 1 (drc0, drc1) 00h request flag registers 0l, 0h, 1l, 1h, 2l, 2h (if0l, if0h, if1l, if1h, if2l, if2h) 00h mask flag registers 0l, 0h, 1l, 1h, 2l, 2h (mk0l, mk0h, mk1l, mk1h, mk2l, mk2h) ffh priority specification flag registers 00l, 00h, 01l, 01h, 02l, 02h, 10l, 10h, 11l, 11h, 12l, 12h (pr00l, pr00h, pr01l, pr01h, pr10l, pr10h, pr11l, pr11h, pr02l, pr02h, pr12l, pr12h) ffh external interrupt rising edge enable registers 0, 1 (egp0, egp1) 00h interrupt external interrupt falling edge enable r egisters 0, 1 (egn0, egn1) 00h regulator regulator mode control register (rmc) 00h bcd correction circuit (bcd) bcd correction result register (bcdadj) undefined notes 1. during reset signal generation or oscillation stabilizatio n time wait, only the pc contents among the hardware statuses become undefined. all other hardwar e statuses remain unchanged after reset. 2. these values vary depending on the reset source. reset source register reset input reset by poc reset by execution of illegal instruction reset by wdt reset by lvi trap bit set (1) held held wdrf bit held set (1) held resf lvirf bit cleared (0) cleared (0) held held set (1) lvis cleared (0eh) cleared (0eh) cleared (0eh) cleared (0eh) held 3. this value varies depending on the reset source and the option byte. remark the sfr and 2nd sfr mount ed depend on the product. refer to 3.2.4 special functi on registers (sfrs) and 3.2.5 extended special function register s (2nd sfrs: 2nd special function registers) .
78k0r/lx3 chapter 22 reset function r01uh0004ej0501 rev.5.01 797 jun 20, 2011 22.1 register for confirming reset source many internal reset generation sources exist in the 78k0r/lx3 microcontrollers. the reset control flag register (resf) is used to store which source has generated the reset request. resf can be read by an 8-bit memory manipulation instruction. reset input, reset by power-on-clear (poc) circui t, and reading resf clear trap, wdrf, and lvirf. figure 22-5. format of reset control flag register (resf) address: fffa8h after reset: undefined r symbol 7 6 5 4 3 2 1 0 resf trap note 1 undefined undefined wdrf note 1 undefined undefined undefined lvirf note 1 trap internal reset request by execution of illegal instruction note 2 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. wdrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. notes 1. the value after reset varies depending on the reset source. 2. the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-cir cuit emulator or on-chip debug emulator. cautions 1. do not read data by a 1-bit memory manipulation instruction. 2. do not make a judgment based on only the read value of the r esf register 8-bit data, because bits other than trap, wdrf, and lvirf become undefined. 3. when the lvi default start fu nction (bit 0 (lvioff) of 000c1h = 0) is used, lvirf flag may become 1 from the beginning de pending on the power-on waveform. the status of resf when a reset request is generated is shown in table 22-3. table 22-3. resf status when reset request is generated reset source flag reset input reset by poc reset by execution of illegal instruction reset by wdt reset by lvi trap set (1) held held wdrf held set (1) held lvirf cleared (0) cleared (0) held held set (1)
78k0r/lx3 chapter 23 power-on-clear circuit r01uh0004ej0501 rev.5.01 798 jun 20, 2011 chapter 23 power-on-clear circuit 23.1 functions of power-on-clear circuit the power-on-clear circuit (poc) is mounted onto all 78k0r/lx3 microcontroller products. the power-on-clear circuit has the following functions. ? generates internal reset signal at power on. the reset signal is released when the supply voltage (v dd ) exceeds 1.61 v 0.09 v. caution if the low-voltage detector (l vi) is set to on by an option byte by default, the reset signal is not released until the supply voltage (v dd ) exceeds 2.07 v 0.2 v. ? compares supply voltage (v dd ) and detection voltage (v pdr = 1.59 v 0.09 v), generates internal reset signal when v dd < v pdr . caution if an internal reset signal is generated in the poc circuit, the r eset control flag register (resf) is cleared to 00h. remark this product incorporates multiple hardware functions that generate an internal reset signal. a flag that indicates the reset source is located in the reset control flag register (resf) for when an internal reset signal is generated by the watchdog timer (wdt), low-voltage-detector (lvi), or illegal instruction execution. resf is not cleared to 00h and the flag is set to 1 when an internal reset signal is generated by wdt or lvi. for details of resf, see chapter 22 reset function .
78k0r/lx3 chapter 23 power-on-clear circuit r01uh0004ej0501 rev.5.01 799 jun 20, 2011 23.2 configuration of power-on-clear circuit the block diagram of the power-on-clear circuit is shown in figure 23-1. figure 23-1. block diagram of power-on-clear circuit ? + reference voltage source internal reset signal v dd v dd 23.3 operation of power-on-clear circuit ? an internal reset signal is generated on power application. when the supply voltage (v dd ) exceeds the detection voltage (v pdr = 1.61 v 0.09 v), the reset status is released. caution if the low-voltage detector (l vi) is set to on by an option byte by default, the reset signal is not released until the supply voltage (v dd ) exceeds 2.07 v 0.2 v. ? the supply voltage (v dd ) and detection voltage (v pdr = 1.59 v 0.09 v) are compared. when v dd < v pdr , the internal reset signal is generated. the timing of generation of the internal reset signal by th e power-on-clear circuit and low-voltage detector is shown below.
78k0r/lx3 chapter 23 power-on-clear circuit r01uh0004ej0501 rev.5.01 800 jun 20, 2011 figure 23-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector (1/2) (1) when lvi is off upon power a pplication (option byte: lvioff = 1) internal high-speed oscillation clock (f ih ) high-speed system clock (f mx ) (when x1 oscillation is selected) starting oscillation is specified by software v pdr = 1.59 v (typ.) v lvi operation stops v por = 1.61 v (typ.) starting oscillation is specified by software cpu 0 v supply voltage (v dd ) 1.8 v note 1 0.5 v/ms (min.) note 2 starting oscillation is specified by software wait for oscillation accuracy stabilization note 4 wait for oscillation accuracy stabilization note 3 wait for oscillation accuracy stabilization note 3 set lvi to be used for reset set lvi to be used for reset set lvi to be used for interrupt normal operation (internal high-speed oscillation clock) note 5 operation stops reset period (oscillation stop) reset period (oscillation stop) normal operation (internal high-speed oscillation clock) note 5 normal operation (internal high-speed oscillation clock ) note 5 reset processing (about 2.1 to 5.8 ms) reset processing (about 2.1 to 5.8 ms) internal reset signal reset processing (about 195 to 322 ms) notes 1. the operation guaranteed range is 1.8 v v dd 5.5 v. to make the state at lower than 1.8 v reset state when the supply voltage falls, use the reset function of t he low-voltage detector, or input the low level to the reset pin. 2. if the rate at which the voltage rises to 1.8 v after power application is slower t han 0.5 v/ms (min.), input a low level to the reset pin before the voltage reaches to 1.8 v, or set lvi to on by default by using an option byte (option byte: lvioff = 0). 3. the reset processing time, such as when waiting for internal voltage stabilization, includes the oscillation accuracy stabilization time of the internal high-speed oscillation clock. 4. the internal reset processing time includes the oscill ation accuracy stabilization time of the internal high- speed oscillation clock. 5. the internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be selected as the cpu clock. to us e the x1 clock, use the ostc regi ster to confirm the lapse of the oscillation stabilization time. to use the xt1 clock, use the timer functi on for confirmation of the lapse of the stabilization time. caution set the low-voltage detector by software after the reset stat us is released (see chapter 24 low- voltage detector). remark v lvi : lvi detection voltage v por : poc power supply rise detection voltage v pdr : poc power supply fall detection voltage
78k0r/lx3 chapter 23 power-on-clear circuit r01uh0004ej0501 rev.5.01 801 jun 20, 2011 figure 23-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector (2/2) (2) when lvi is on upon power app lication (option byte: lvioff = 0) internal high-speed oscillation clock (f ih ) high-speed system clock (f mx ) (when x1 oscillation is selected) v pdr = 1.59 v (typ.) v lvi operation stops v por = 1.61 v (typ.) cpu 0 v supply voltage (v dd ) 1.8 v note 1 v lvi = 2.07 v (typ.) wait for oscillation accuracy stabilization note 3 wait for oscillation accuracy stabilization note 3 wait for oscillation accuracy stabilization note 3 set lvi (v lvi = 2.07 v) to be used for reset (default) set lvi (v lvi = 2.07 v) to be used for reset (default) change lvi detection voltage (v lvi ) set lvi to be used for interrupt starting oscillation is specified by software starting oscillation is specified by software starting oscillation is specified by software normal operation (internal high-speed oscillation clock) note 2 normal operation (internal high-speed oscillation clock) note 2 operation stops reset period (oscillation stop) normal operation (internal high-speed oscillation clock) note 2 reset period (oscillation stop) reset processing time reset processing time (about 195 to 322 s) poc processing time reset processing time poc processing time internal reset signal note 4 note 4 notes 1. the operation guaranteed range is 1.8 v v dd 5.5 v. to make the state at lower than 1.8 v reset state when the supply voltage falls, use the reset function of t he low-voltage detector, or input the low level to the reset pin. 2. the internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be selected as the cpu clock. to us e the x1 clock, use the ostc regi ster to confirm the lapse of the oscillation stabilization time. to use the xt1 clock, use the timer functi on for confirmation of the lapse of the stabilization time. 3. the internal reset processing time includes the oscill ation accuracy stabilization time of the internal high- speed oscillation clock. 4. the following times are required between reaching the poc detection voltage (1 .59 v (typ.)) and starting normal operation. ? when the time to reach 2.07 v (typ.) from 1.59 v (typ.) is less than 5.8 ms: a poc processing time of about 2.1 to 6.2 ms is required between reaching 1. 59 v (typ.) and starting normal operation. ? when the time to reach 2.07 v (typ.) from 1.59 v (typ.) is greater than 5.8 ms: a reset processing time of about 195 to 322 s is required between reaching 2.07 v (typ.) and starting normal operation. caution set the low-voltage detector by software after the reset stat us is released (see chapter 24 low- voltage detector). remark v lvi : lvi detection voltage v por : poc power supply rise detection voltage v pdr : poc power supply fall detection voltage
78k0r/lx3 chapter 23 power-on-clear circuit r01uh0004ej0501 rev.5.01 802 jun 20, 2011 23.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in t he vicinity of the poc detection voltage (v por , v pdr ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrar ily set by taking the following action. after releasing the reset signal, wait for the supply volta ge fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports. figure 23-3. example of software processing after reset release (1/2) ? if supply voltage fluctuation is 50 ms or le ss in vicinity of poc detection voltage ; check the reset source, etc. note 2 note 1 reset initialization processing <1> 50 ms has passed? (tmif0n = 1?) initialization processing <2> setting timer array unit (to measure 50 ms) ; initial setting for port. setting of division ratio of system clock, such as setting of timer or a/d converter. yes no power-on-clear clearing wdt ; f clk = internal high-speed oscillation clock (4.08 mhz (max.)) (default) source: f clk (4.08 mhz (max.))/2 11 , where comparison value = 100: ? 50 ms timer starts (ts0n = 1). notes 1. if reset is generated again during this period, initialization processing <2> is not started. 2. a flowchart is shown on the next page. remark n = 0 to 7
78k0r/lx3 chapter 23 power-on-clear circuit r01uh0004ej0501 rev.5.01 803 jun 20, 2011 figure 23-3. example of software processing after reset release (2/2) ? checking reset source yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector no wdrf of resf register = 1? lvirf of resf register = 1? yes no reset processing by illegal instruction execution note trap of resf register = 1? yes note the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator.
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 804 jun 20, 2011 chapter 24 low-voltage detector 24.1 functions of low-voltage detector the low-voltage detector (lvi) is mounted onto all 78k0r/lx3 microcontroller products. the low-voltage detector has the following functions. ? the lvi circuit compares the supply voltage (v dd ) with the detection voltage (v lvi ) or the input voltage from an external input pin (exlvi) with the detection voltage (v exlvi = 1.21 v 0.1 v), and generates an internal reset or internal interrupt signal. ? the low-voltage detector (lvi) can be set to on by an option byte by default. if it is set to on to raise the power supply from the poc detection voltage (v por = 1.61 v (typ.)) or lower, the inte rnal reset signal is generated when the supply voltage (v dd ) < detection voltage (v lvi = 2.07 v 0.2 v). after that, the internal reset signal is generated when the supply voltage (v dd ) < detection voltage (v lvi = 2.07 v 0.1 v). ? the supply voltage (v dd ) or the input voltage from the external input pin (exlvi) can be selected to be detected by software. ? a reset or an interrupt can be selected to be generated after detection by software. ? detection levels (v lvi ,16 levels) of supply voltage can be changed by software. ? operable in stop mode. the reset and interrupt signals are generated as follows depending on selection by software. selection of level detection of supply voltage (v dd ) (lvisel = 0) selection level detection of input voltage from external input pin (exlvi) (lvisel = 1) selects reset (lvimd = 1). selects interrupt (lvimd = 0). selects reset (lvimd = 1). selects interrupt (lvimd = 0). generates an internal reset signal when v dd < v lvi and releases the reset signal when v dd v lvi . generates an internal interrupt signal when v dd drops lower than v lvi (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ). generates an internal reset signal when exlvi < v exlvi and releases the reset signal when exlvi v exlvi . generates an internal interrupt signal when exlvi drops lower than v exlvi (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ). remark lvisel: bit 2 of low-voltage detection register (lvim) lvimd: bit 1 of lvim while the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input pin is more than or less than the detection level can be checked by readi ng the low-voltage detection fl ag (lvif: bit 0 of lvim). when the low-voltage detector is used to reset, bit 0 (lvirf) of the reset control flag register (resf) is set to 1 if reset occurs. for details of resf, see chapter 22 reset function .
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 805 jun 20, 2011 24.2 configuration of low-voltage detector the block diagram of the low-voltage detector is shown in figure 24-1. figure 24-1. block diagram of low-voltage detector lvis1 lvis0 lvion ? + reference voltage source v dd internal bus n-ch low-voltage detection level select register (lvis) low-voltage detection register (lvim) lvis2 lvis3 lvif intlvi internal reset signal 4 lvisel exlvi/p120/ intp0 lvimd v dd low-voltage detection level selector selector selector 24.3 registers controlling low-voltage detector the low-voltage detector is contro lled by the following registers. ? low-voltage detection register (lvim) ? low-voltage detection level select register (lvis) ? port mode register 12 (pm12) (1) low-voltage detection register (lvim) this register sets low-voltag e detection and the operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h.
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 806 jun 20, 2011 figure 24-2. format of low-volta ge detection register (lvim) <0> lvif <1> lvimd <2> lvisel 3 0 4 0 5 0 6 0 <7> lvion symbol lvim address: fffa9h after reset: 00h note 1 r/w note 2 lvion notes 3, 4 enables low-voltage detection operation 0 disables operation 1 enables operation lvisel note 3 voltage detection selection 0 detects level of supply voltage (v dd ) 1 detects level of input voltage from external input pin (exlvi) lvimd note 3 low-voltage detection operation m ode (interrupt/reset) selection 0 ? lvisel = 0: generates an internal interrupt signal when the supply voltage (v dd ) drops lower than the detection voltage (v lvi ) (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ). ? lvisel = 1: generates an interrupt signal when the input voltage from an external input pin (exlvi) drops lower than the detection voltage (v exlvi ) (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ). 1 ? lvisel = 0: generates an internal reset signal when the supply voltage (v dd ) < detection voltage (v lvi ) and releases the reset signal when v dd v lvi . ? lvisel = 1: generates an internal reset signal when the input voltage from an external input pin (exlvi) < detection voltage (v exlvi ) and releases the reset signal when exlvi v exlvi . lvif low-voltage detection flag 0 ? lvisel = 0: supply voltage (v dd ) detection voltage (v lvi ), or when lvi operation is disabled ? lvisel = 1: input voltage from external input pin (exlvi) detection voltage (v exlvi ), or when lvi operation is disabled 1 ? lvisel = 0: supply voltage (v dd ) < detection voltage (v lvi ) ? lvisel = 1: input voltage from external input pin (exlvi) < detection voltage (v exlvi ) notes 1. the reset value changes depending on the rese t source and the setting of the option byte. this register is not cleared (00h) by lvi reset. it is set to ?82h? when a reset signal other than lv i is applied if option byte lvioff = 0, and to ?00h? if option byte lvioff = 1. 2. bit 0 is read-only. 3. lvion, lvimd, and lvisel are cleared to 0 in the case of a reset other than an lvi reset. these are not cleared to 0 in the case of an lvi reset.
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 807 jun 20, 2011 note 4. when lvion is set to 1, operation of t he comparator in the lvi circuit is started. use software to wait for the following periods of time, between when lvion is set to 1 and when the voltage is confirmed with lvif. ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) the lvif value for these periods may be set/cleared regardless of the voltage le vel, and can therefore not be used. also, the lviif interrupt request flag may be set to 1 in these periods. cautions 1. to stop lvi, be sure to clear (0) lvion by using a 1-bit memory manipulation instruction. 2. input voltage from external input pin (exlvi) must be exlvi < v dd . 3. when lvi is used in interrupt mode (lvimd = 0) and lvisel is set to 0, an interrupt request signal (intlvi) that disables lvi operation (clears lvion) when the supply voltage (v dd ) is less than or equal to the detection voltage (v lvi ) (if lvisel = 1, input vo ltage of external input pin (exlvi) is less than or equa l to the detection voltage (v exlvi )) is generated and lviif may be set to 1.
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 808 jun 20, 2011 (2) low-voltage detection l evel select register (lvis) this register selects the low-voltage detection level. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation input sets this register to 0eh. figure 24-3. format of low-voltage dete ction level select register (lvis) 0 lvis0 1 lvis1 2 lvis2 3 lvis3 4 0 5 0 6 0 7 0 symbol lvis address: fffaah after reset: 0eh note r/w lvis3 lvis2 lvis1 lvis0 detection level 0 0 0 0 v lvi0 (4.22 0.1 v) 0 0 0 1 v lvi1 (4.07 0.1 v) 0 0 1 0 v lvi2 (3.92 0.1 v) 0 0 1 1 v lvi3 (3.76 0.1 v) 0 1 0 0 v lvi4 (3.61 0.1 v) 0 1 0 1 v lvi5 (3.45 0.1 v) 0 1 1 0 v lvi6 (3.30 0.1 v) 0 1 1 1 v lvi7 (3.15 0.1 v) 1 0 0 0 v lvi8 (2.99 0.1 v) 1 0 0 1 v lvi9 (2.84 0.1 v) 1 0 1 0 v lvi10 (2.68 0.1 v) 1 0 1 1 v lvi11 (2.53 0.1 v) 1 1 0 0 v lvi12 (2.38 0.1 v) 1 1 0 1 v lvi13 (2.22 0.1 v) 1 1 1 0 v lvi14 (2.07 0.1 v) 1 1 1 1 v lvi15 (1.91 0.1 v) note the reset value changes depending on the reset source. if the lvis register is reset by lvi, it is not reset but holds the current value. t he value of this register is reset to ?0eh? if a reset other than by lvi is effected. cautions 1. be sure to cl ear bits 4 to 7 to ?0?.
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 809 jun 20, 2011 cautions 2. change the lvis value with either of the following methods. ? when changing the value after stopping lvi <1> stop lvi (lvion = 0). <2> change the lvis register. <3> set to the mode used as an interrupt (lvimd = 0). <4> mask lvi interrupts (lvimk = 1). <5> enable lvi operation (lvion = 1). <6> before cancelling the lv i interrupt mask (lvimk = 0), clear it with software because an lviif flag may be set when lvi operation is enabled. ? when changing the value after setting to th e mode used as an interrupt (lvimd = 0) <1> mask lvi interrupts (lvimk = 1). <2> set to the mode used as an interrupt (lvimd = 0). <3> change the lvis register. <4> before cancelling the lv i interrupt mask (lvimk = 0), clear it with software because an lviif flag may be set when the lvis register is changed. 3. when an input voltage from the externa l input pin (exlvi) is detected, the detection voltage (v exlvi ) is fixed. therefore, setting of lvis is not necessary. (3) port mode register 12 (pm12) when using the p120/exlvi/intp0 pin for ex ternal low-voltage detection potential input, set pm120 to 1. at this time, the output latch of p120 may be 0 or 1. pm12 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 24-4. format of port mode register 12 (pm12) 0 pm120 1 1 2 1 3 1 4 1 5 1 6 1 7 1 symbol pm12 address: fff2ch after reset: ffh r/w pm120 p120 pin i/o mode selection 0 output mode (output buffer on) 1 input mode (output buffer off)
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 810 jun 20, 2011 24.4 operation of low-voltage detector the low-voltage detector can be us ed in the following two modes. (1) used as reset (lvimd = 1) ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ), generates an internal reset signal when v dd < v lvi , and releases internal reset when v dd v lvi . ? if lvisel = 1, compares the input voltage from external input pin (exlvi) and detection voltage (v exlvi ), generates an internal reset signal when exlvi < v exlvi , and releases internal reset when exlvi v exlvi . remark the low-voltage detector (lvi) can be set to on by an opt ion byte by default. if it is set to on to raise the power supply from t he poc detection voltage (v por = 1.61 v (typ.)) or lower, the internal reset signal is generated when the supply voltage (v dd ) < detection voltage (v lvi = 2.07 v 0.2 v). after that, the internal reset signal is generated when the supply voltage (v dd ) < detection voltage (v lvi = 2.07 v 0.1 v). (2) used as interrupt (lvimd = 0) ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ). when v dd drops lower than v lvi (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ), generates an interrupt signal (intlvi). ? if lvisel = 1, compares the i nput voltage from external input pin (exlvi) and detection voltage (v exlvi = 1.21 v 0.1 v). when exlvi drops lower than v exlvi (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ), generates an interrupt signal (intlvi). while the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input pin is more than or less than the detection level can be checked by readi ng the low-voltage detection fl ag (lvif: bit 0 of lvim). remark lvimd: bit 1 of low-voltage detection register (lvim) lvisel: bit 2 of lvim
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 811 jun 20, 2011 24.4.1 when used as reset (1) when detecting level of supply voltage (v dd ) (a) when lvi default start function stopped is set (lvioff = 1) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low-vo ltage detection register (lvim) to 0 (detects level of supply voltage (v dd )) (default value). <3> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltag e detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for the following periods of time (total 210 s). ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) <6> wait until it is checked that (supply voltage (v dd ) detection voltage (v lvi )) by bit 0 (lvif) of lvim. <7> set bit 1 (lvimd) of lvim to 1 (generates reset when the level is detected). figure 24-5 shows the timing of the internal reset signal generated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <7> above. cautions 1. be sure to execute <1>. when lvim k = 0, an interrupt may o ccur immediately after the processing in <4>. 2. if supply voltage (v dd ) detection voltage (v lvi ) when lvimd is set to 1, an internal reset signal is not generated. ? when stopping operation be sure to clear (0) lvimd and then lvion by us ing a 1-bit memory manipulation instruction.
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 812 jun 20, 2011 figure 24-5. timing of low-voltage dete ctor internal reset signal generation (bit: lvisel = 0, option byte: lvioff = 1) l <1> <2> <4> <5> <6> <7> v lvi v pdr = 1.59 v (typ.) v por = 1.61 v (typ.) internal reset signal set lvi to be used for reset supply voltage (v dd ) lvimk flag (set by software) time h note 1 lvisel flag (set by software) lvion flag (set by software) not cleared not cleared not cleared not cleared wait time <3> cleared cleared cleared lvif flag lvimd flag (set by software) lvirf flag note 3 lvi reset signal cleared by software cleared by software poc reset signal note 2 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lviif flag of the interrupt request flag registers and the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag r egister (resf). for details of resf, see chapter 22 reset function . remarks 1. <1> to <7> in figure 24-5 above correspond to <1> to <7> in the description of ?when starting operation? in 24.4.1 (1) (a) when lvi default star t function stopped is set (lvioff = 1). 2. v por : poc power supply rise detection voltage v pdr : poc power supply fall detection voltage
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 813 jun 20, 2011 (b) when lvi default start function enabled is set (lvioff = 0) ? when starting operation start in the following initial setting state. ? set bit 7 (lvion) of lvim to 1 (enables lvi operation) ? clear bit 2 (lvisel) of the low-voltage detection regi ster (lvim) to 0 (detects level of supply voltage (v dd )) ? set the low-voltage detection level selectio n register (lvis) to 0eh (default value: v lvi = 2.07 v 0.1 v ). ? set bit 1 (lvimd) of lvim to 1 (generat es reset when the level is detected) ? set bit 0 (lvif) of lvim to 0 (?supply voltage (v dd ) detection voltage (v lvi )?) figure 24-6 shows the timing of the internal rese t signal generated by the low-voltage detector. ? when stopping operation be sure to clear (0) lvimd and then lvion by using a 1-bit memory manipulation instruction. caution even when the lvi default start function is u sed, if it is set to lvi operation prohibition by the software, it operates as follows: ? does not perform low-voltage detection during lvion = 0. ? if a reset is generated while lvion = 0, lv ion will be re-set to 1 when the cpu starts after reset release. there is a period when low-voltage detection cannot be performed normally, however, when a reset occurs due to wdt and illegal instruction execution. this is due to the fact that while the pulse width detected by lvi must be 200 s max., lvion = 1 is set upon reset occurrence, and th e cpu starts operating without waiting for the lvi stabilization time.
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 814 jun 20, 2011 figure 24-6. timing of low-voltage dete ctor internal reset signal generation (bit: lvisel = 0, option byte: lvioff = 0) l v lvi = 2.07 v (typ.) v por = 1.61 v (typ.) v pdr = 1.59 v (typ.) h h internal reset signal supply voltage (v dd ) lvimk flag (set by software) lvisel flag (set by software) lvion flag (set by software) lvif flag lvimd flag (set by software) lvirf flag lvi reset signal poc reset signal time h note 1 not cleared not cleared not cleared not cleared cleared by software cleared by software cleared by software note 2 cleared cleared interrupt operation mode is set by setting lvimd to 0 (lvi interrupt is masked) change lvi detection voltage (v lvi ) reset mode is set by setting lvimd to 1 v lvi value after a change notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. lvirf is bit 0 of the reset control flag register (resf). when the lvi default start function (b it 0 (lvioff) of 000c1h = 0) is used, the lvirf flag may become 1 from the beginning due to the power-on waveform. for details of resf, see chapter 22 reset function . remark v por : poc power supply rise detection voltage v pdr : poc power supply fall detection voltage
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 815 jun 20, 2011 (2) when detecting level of input vo ltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regist er (lvim) to 1 (detects le vel of input voltage from external input pin (exlvi)). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for the following periods of time (total 210 s). ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) <5> wait until it is checked that (input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.))) by bit 0 (lvif) of lvim. <6> set bit 1 (lvimd) of lvim to 1 (generates reset signal when the level is detected). figure 24-7 shows the timing of the internal reset signal generated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <6> above. cautions 1. be sure to execute <1>. when lvim k = 0, an interrupt may oc cur immediately after the processing in <3>. 2. if input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.)) when lvimd is set to 1, an intern al reset signal is not generated. 3. input voltage from external input pin (exlvi) must be exlvi < v dd . ? when stopping operation be sure to clear (0) lvimd and then lvion by using a 1-bit memory manipulation instruction.
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 816 jun 20, 2011 figure 24-7. timing of low-voltage dete ctor internal reset signal generation (bit: lvisel = 1) v exlvi set lvi to be used for reset lvimk flag (set by software) lvif flag lvirf flag note 3 lvi reset signal internal reset signal lvion flag (set by software) lvimd flag (set by software) lvisel flag (set by software) <1> <2> <3> <4> wait time <5> <6> note 2 not cleared not cleared not cleared not cleared not cleared not cleared not cleared not cleared not cleared cleared by software cleared by software time h note 1 input voltage from external input pin (exlvi) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lviif flag of the interrupt request flag registers and the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag r egister (resf). for details of resf, see chapter 22 reset function . remark <1> to <6> in figure 24-7 above correspond to <1> to <6> in the description of ? when starting operation? in 24.4.1 (2) when detecting level of inpu t voltage from external input pin (exlvi) .
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 817 jun 20, 2011 24.4.2 when used as interrupt (1) when detecting level of supply voltage (v dd ) (a) when lvi default start function stopped is set (lvioff = 1) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low-vo ltage detection register (lvim) to 0 (detects level of supply voltage (v dd )) (default value). clear bit 1 (lvimd) of lvim to 0 (generates interrupt signal when the level is detected) (default value). <3> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltag e detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for the following periods of time (total 210 s). ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) <6> confirm that ?supply voltage (v dd ) detection voltage (v lvi )? when detecting the falling edge of v dd , or ?supply voltage (v dd ) < detection voltage (v lvi )? when detecting the rising edge of v dd , at bit 0 (lvif) of lvim. <7> clear the interrupt request flag of lvi (lviif) to 0. <8> release the interrupt mask flag of lvi (lvimk). <9> execute the ei instruction (w hen vector interrupts are used). figure 24-8 shows the timing of the interrupt signal gener ated by the low-voltage detec tor. the numbers in this timing chart correspond to <1> to <8> above. ? when stopping operation be sure to clear (0) lvion by using a 1-bit memory manipulation instruction.
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 818 jun 20, 2011 figure 24-8. timing of low-voltage de tector interrupt signal generation (bit: lvisel = 0, option byte: lvioff = 1) intlvi l <1> <3> <6> <7> <2> <4> l v lvi v por = 1.61 v (typ.) v pdr = 1.59 v (typ.) internal reset signal supply voltage (v dd ) lvimk flag (set by software) lvisel flag (set by software) lvion flag (set by software) lvimd flag (set by software) lvif flag lviif flag cleared by software <8> cleared by software <5> wait time note 3 note 2 note 2 note 2 note 1 note 3 time notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). 3. if lvi operation is disabled when the supply voltage (v dd ) is less than or equal to the detection voltage (v lvi ), an interrupt request signal (intlvi) is generated and lviif may be set to 1. remarks 1. <1> to <8> in figure 24-8 above correspond to <1> to <8> in the description of ?when starting operation? in 24.4.2 (1) (a) when lvi default star t function stopped is set (lvioff = 1). 2. v por : poc power supply rise detection voltage v pdr : poc power supply fall detection voltage
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 819 jun 20, 2011 (b) when lvi default start function enabled is set (lvioff = 0) ? when starting operation <1> start in the following initial setting state. ? set bit 7 (lvion) of lvim to 1 (enables lvi operation) ? clear bit 2 (lvisel) of the low-voltage detection re gister (lvim) to 0 (detects level of supply voltage (v dd )) ? set the low-voltage detection level selectio n register (lvis) to 0eh (default value: v lvi = 2.07 v 0.1 v ). ? set bit 1 (lvimd) of lvim to 1 (generat es reset when the level is detected) ? set bit 0 (lvif) of lvim to 0 (detects falling edge ?supply voltage (v dd ) detection voltage (v lvi )?) <2> clear bit 1 (lvimd) of lvim to 0 (generates inte rrupt signal when the level is detected) (default value). <3> release the interrupt mask flag of lvi (lvimk). <4> execute the ei instruction (w hen vector interrupts are used). figure 24-9 shows the timing of the interrupt signal gener ated by the low-voltage detec tor. the numbers in this timing chart correspond to <1> to <3> above. ? when stopping operation be sure to clear (0) lvion by using a 1-bit memory manipulation instruction. cautions 1. even when the lvi default start function is used, if it is set to lvi operation prohibition by the software, it operates as follows: ? does not perform low-voltage detection during lvion = 0. ? if a reset is generated while lvion = 0, lvion will be re-set to 1 when the cpu starts after reset release. there is a period when low- voltage detection cannot be performed normally, however, when a reset occurs due to wd t and illegal instruction execution. this is due to the fact that while the pulse width detected by lvi must be 200 s max., lvion = 1 is set upon reset occurrence, and th e cpu starts operating without waiting for the lvi stabilization time. 2. when the lvi default start function (bit 0 (lviof f) of 000c1h = 0) is used, the lvirf flag may become 1 from the beginning due to the power-on waveform. for details of resf, see chapter 22 reset function.
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 820 jun 20, 2011 figure 24-9. timing of low-voltage de tector interrupt signal generation (bit: lvisel = 0, option byte: lvioff = 0) intlvi l v lvi = 2.07 v (typ.) v por = 1.61 v (typ.) v pdr = 1.59 v (typ.) <1> <2> internal reset signal supply voltage (v dd ) lvimk flag (set by software) lvisel flag (set by software) lvion flag (set by software) lvimd flag (set by software) lvif flag lviif flag cleared by software <3> cleared by software note 2 note 2 note 3 note 1 time v lvi value after a change mask lvi interrupts (lvimk = 1) cancelling the lvi interrupt mask (lvimk = 0) change lvi detection voltage (v lvi ) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. if lvi operation is disabled when the supply voltage (v dd ) is less than or equal to the detection voltage (v lvi ), an interrupt request signal (intlvi) is generated and lviif may be set to 1. 3. the lviif flag may be set when the lvi detection voltage is changed. remarks 1. <1> to <3> in figure 24-9 above correspond to <1> to <3> in the description of ?when starting operation? in 24.4.2 (1) (b) when lvi default start function enabled is set (lvioff = 0). 2. v por : poc power supply rise detection voltage v pdr : poc power supply fall detection voltage
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 821 jun 20, 2011 (2) when detecting level of input vo ltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regist er (lvim) to 1 (detects le vel of input voltage from external input pin (exlvi)). clear bit 1 (lvimd) of lvim to 0 (generates interrupt signal when the level is detected) (default value). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for the following periods of time (total 210 s). ? operation stabilization time (10 s (max.)) ? minimum pulse width (200 s (min.)) <5> confirm that ?input voltage fr om external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.))? when detecting the falling edge of exlvi, or ?input vo ltage from external input pin (exlvi) < detection voltage (v exlvi = 1.21 v (typ.))? when detecting the rising e dge of exlvi, at bit 0 (lvif) of lvim. <6> clear the interrupt request flag of lvi (lviif) to 0. <7> release the interrupt mask flag of lvi (lvimk). <8> execute the ei instruction (w hen vector interrupts are used). figure 24-10 shows the timing of the interrupt signal gener ated by the low-voltage detec tor. the numbers in this timing chart correspond to <1> to <7> above. caution input voltage from external i nput pin (exlvi) must be exlvi < v dd . ? when stopping operation be sure to clear (0) lvion by using a 1-bit memory manipulation instruction.
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 822 jun 20, 2011 figure 24-10. timing of low-voltage detector interrupt signal generation (bit: lvisel = 1) v exlvi l lvimk flag (set by software) lvif flag intlvi lviif flag lvion flag (set by software) lvisel flag (set by software) lvimd flag (set by software) input voltage from external input pin (exlvi) time <1> note 1 <7> cleared by software <2> <3> <5> note 2 note 2 note 2 <6> cleared by software <4> wait time note 3 note 3 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). 3. if lvi operation is disabled when the input voltage of ex ternal input pin (exlvi) is less than or equal to the detection voltage (v exlvi ), an interrupt request signal (intlvi) is generated and lviif may be set to 1. remark <1> to <7> in figure 24-10 above correspond to <1> to <7> in the description of ?when starting operation? in 24.4.2 (2) when detecting level of inpu t voltage from external input pin (exlvi) .
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 823 jun 20, 2011 24.5 cautions for low-voltage detector (1) measures method when supply voltage (v dd ) frequently fluctuates in the vici nity of the lvi detection voltage (v lvi ) in a system where the supply voltage (v dd ) fluctuates for a certain period in t he vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. operation example 1: when used as reset the system may be repeatedly reset and released from the reset status. the time from reset release through microcontroller op eration start can be set arbitrarily by the following action. after releasing the reset signal, wait for the supply voltage fl uctuation period of each system by means of a software counter that uses a timer, and then initialize the ports (see figure 24-11 ). remark if bit 2 (lvisel) of the low voltage detection register (lvim) is set to ?1?, the meanings of the above words change as follows. ? supply voltage (v dd ) input voltage from external input pin (exlvi) ? detection voltage (v lvi ) detection voltage (v exlvi = 1.21 v)
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 824 jun 20, 2011 figure 24-11. example of software processing after reset release (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage ; check the reset source, etc. note ; setting of detection level by lvis. the low-voltage detector operates (lvion = 1). reset initialization processing <1> 50 ms has passed? (tmif0n = 1?) initialization processing <2> setting timer array unit (to measure 50 ms) ; initial setting for port. setting of division ratio of system clock, such as setting of timer or a/d converter. yes no setting lvi clearing wdt detection voltage or higher (lvif = 0?) yes restarting timer array unit (tt0n = 1 ts0n = 1) no ; the timer counter is cleared and the timer is started. lvi reset ; f clk = internal high-speed oscillation clock (4.08 mhz (max.)) (default) source: f clk (4.08 mhz (max.))/2 11 , where comparison value = 100: ? 50 ms timer starts (ts0n = 1). note a flowchart is shown on the next page. remarks 1. if bit 2 (lvisel) of the low voltage detection regist er (lvim) is set to ?1?, the meanings of the above words change as follows. ? supply voltage (v dd ) input voltage from external input pin (exlvi) ? detection voltage (v lvi ) detection voltage (v exlvi = 1.21 v) 2. n = 0 to 7
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 825 jun 20, 2011 figure 24-11. example of software processing after reset release (2/2) ? checking reset source yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector yes wdrf of resf register = 1? lvirf of resf register = 1? yes no reset processing by illegal instruction execution note trap of resf register = 1? no note when instruction code ffh is executed. reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. remark if bit 2 (lvisel) of the low voltage detection register (lvim) is set to ?1?, the meanings of the above words change as follows. ? supply voltage (v dd ) input voltage from external input pin (exlvi) ? detection voltage (v lvi ) detection voltage (v exlvi = 1.21 v)
78k0r/lx3 chapter 24 low-voltage detector r01uh0004ej0501 rev.5.01 826 jun 20, 2011 operation example 2: when used as interrupt interrupt requests may be generated frequently. take the following action. confirm that ?supply voltage (v dd ) detection voltage (v lvi )? when detecting the falling edge of v dd , or ?supply voltage (v dd ) < detection voltage (v lvi )? when detecting the rising edge of v dd , in the servicing routine of the lvi interrupt by using bit 0 (lvif) of the low-voltage detection register (lvim). clear bit 1 (lviif) of interrupt request flag register 0l (if0l) to 0. for a system with a long supply voltage fluctuation period near the lvi detect ion voltage, take the above action after waiting for the supply voltage fluctuation time. remark if bit 2 (lvisel) of the low voltage detection register (lvim) is set to ?1?, the meanings of the above words change as follows. ? supply voltage (v dd ) input voltage from external input pin (exlvi) ? detection voltage (v lvi ) detection voltage (v exlvi = 1.21 v) (2) delay from the time lvi reset source is generated until the time lvi reset has been generated or released there is some delay from the time supply voltage (v dd ) < lvi detection voltage (v lvi ) until the time lvi reset has been generated. in the same way, there is also some delay from the time lvi detection voltage (v lvi ) supply voltage (v dd ) until the time lvi reset has been released (see figure 24-12 ). figure 24-12. delay from the time lvi reset source is genera ted until the time lvi reset has been generated or released supply voltage (v dd ) v lvi lvif flag lvi reset signal <1> time <1> <1>: minimum pu lse width (200 s (min.))
78k0r/lx3 chapter 25 regulator r01uh0004ej0501 rev.5.01 827 jun 20, 2011 chapter 25 regulator 25.1 regulator overview all 78k0r/lx3 microcontroller products contain a circuit for operati ng the device with a constant voltage. at this time, in order to stabilize the regulator output voltage, connect the regc pin to v ss via a capacitor (0.47 to 1 f). also, use a capacitor with good characteristics, si nce it is used to stabilize internal voltage. the regulator output voltage is norma lly 2.4 v (typ.), and in the low-powe r consumption mode, 1.8 v (typ.). 25.2 registers controlling regulator (1) regulator mode c ontrol register (rmc) this register sets the output voltage of the regulator. rmc is set with an 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 25-1. format of regulator mode control register (rmc) address: f00f4h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 rmc rmc[7:0] control of output voltage of regulator 5ah fixed to low-power consumption mode (1.8 v) 00h switches normal power mode (2.4 v) and low-power consumption mode (1.8 v) according to the condition (refer to table 25-1 ) other than above setting prohibited cautions 1. the rmc register can be rewritten only in the low-power consumption mode (refer to table 25-1). in other words, rewrite this register during cpu operation wit h the subsystem clock (f xt ) while the high-speed system clock (f mx ), the high-speed internal oscillation clock, and the 20 mhz internal high-speed oscillation clock (f ih20 ) are both stopped. 2. when using the setting fixed to the low cons umption current mode, the rmc register can be used in the following cases. f clk 1 mhz and external oscillator (x1 clock (f x ), external main system clock (f ex )) stop. f clk 1 mhz, f x /f ex 5 mhz and the internal hi gh-speed oscillator stop. both the internal high-speed oscillator and external oscillator (f x /f ex 5 mhz) stop or either one stops.
78k0r/lx3 chapter 25 regulator r01uh0004ej0501 rev.5.01 828 jun 20, 2011 cautions 3. in low-power consumpt ion mode, use the regulator with f clk fixed to 1 mhz when executing self programming. 4. a wait is required to change the operat ion speed mode control register (osmc) after changing the rmc register. wait for 2 ms by software when setting to low-power consumption mode and 10 s when setting to normal power mode, as described in the procedure shown below. ? when setting to low- power consumption mode <1> select a frequency of 1 mhz for f clk . <2> set rmc to 5ah (set the regulat or to low-power consumption mode). <3> wait for 2 ms. <4> set flpc and fsel of os mc to 1 and 0, respectively. ? when setting to normal power mode <1> set rmc to 00h (set the re gulator to normal power mode). <2> wait for 10 s. <3> change flpc and fsel of osmc. <4> change the f clk frequency. table 25-1. regulator output voltage conditions mode output voltage condition in stop mode (except during ocd mode) when both the high-speed system clock (f mx ), the high-speed internal oscillation clock (f ih ), and the 20 mhz internal high-speed oscillation clock (f ih20 ) are stopped during cpu operati on with the subsystem clock (f sub ) low-power consumption mode 1.8 v when both the high-speed system clock (f mx ), the high-speed internal oscillation clock (f ih ), and the 20 mhz internal high-speed oscillation clock (f ih20 ) are stopped during the halt mode when the cpu operation with the subsystem clock (f sub ) has been set normal power mode 2.4 v other than above
78k0r/lx3 chapter 26 option byte r01uh0004ej0501 rev.5.01 829 jun 20, 2011 chapter 26 option byte 26.1 functions of option bytes addresses 000c0h to 000c3h of the flash memory of t he 78k0r/lx3 microcontrollers form an option byte area. option bytes consist of user option byte (000c0h to 000c2h) and on-chip debug option byte (000c3h). upon power application or resetting and starting, an option byte is automatically referenced and a specified function is set. when using the product, be sure to set t he following functions by using the option bytes. to use the boot swap operation during self programming, 000c0h to 000c3h are replaced by 010c0h to 010c3h. therefore, set the same values as 000c0h to 000c3h to 010c0h to 010c3h. caution be sure to set ffh to 000c2h (000c2h/ 010c2h when the boot swap operation is used). 26.1.1 user option byte (000c0h to 000c2h/010c0h to 010c2h) (1) 000c0h/010c0h { operation of watchdog timer ? operation is stopped or enabl ed in the halt or stop mode. { setting of interval time of watchdog timer { operation of watchdog timer ? operation is stopped or enabled. { setting of window open period of watchdog timer { setting of interval interrupt of watchdog timer ? used or not used caution set the same value as 000c0 h to 010c0h when the boot swap operation is used because 000c0h is replaced by 010c0h. (2) 000c1h/010c1h { setting of lvi upon reset release (upon power application) ? lvi is on or off by default upon reset release (rese t by reset pin excluding lvi, poc, wdt, or illegal instructions). { setting of internal high-speed oscillator frequency ? select from 1 mhz, 8 mhz, or 20 mhz. caution set the same value as 000c1 h to 010c1h when the boot swap operation is used because 000c1h is replaced by 010c1h. (3) 000c2h/010c2h { be sure to set ffh, as these addresses are reserved areas. caution set ffh to 010c2h when the boot swap ope ration is used because 0 00c2h is replaced by 010c2h.
78k0r/lx3 chapter 26 option byte r01uh0004ej0501 rev.5.01 830 jun 20, 2011 26.1.2 on-chip debug option byte (000c3h/ 010c3h) { control of on-chip debug operation ? on-chip debug operation is disabled or enabled. { handling of data of flash memory in case of failure in on-chip debug security id authentication ? data of flash memory is erased or not erased in case of failure in on-chip debug security id authentication. caution set the same value as 000c3 h to 010c3h when the boot swap operation is used because 000c3h is replaced by 010c3h. 26.2 format of user option byte the format of user option byte is shown below. figure 26-1. format of user option byte (000c0h/010c0h) (1/2) address: 000c0h/010c0h note 1 7 6 5 4 3 2 1 0 wdtinit window1 window0 wdton wdcs2 wdcs1 wdcs0 wdstbyon wdtinit use of interval interrupt of watchdog timer 0 interval interrupt is not used. 1 interval interrupt is generated when 75% of the overflow time is reached. window1 window0 watchdog timer window open period note 2 0 0 setting prohibited 0 1 50% 1 0 75% 1 1 100% wdton operation control of watchdog timer counter 0 counter operation disabled (counting stopped after reset) 1 counter operation enabled (counting started after reset) wdcs2 wdcs1 wdcs0 watc hdog timer overflow time (f il = 33 khz (max.)) 0 0 0 2 7 /f il (3.88 ms) 0 0 1 2 8 /f il (7.76 ms) 0 1 0 2 9 /f il (15.52 ms) 0 1 1 2 10 /f il (31.03 ms) 1 0 0 2 12 /f il (124.12 ms) 1 0 1 2 14 /f il (496.48 ms) 1 1 0 2 15 /f il (992.97 ms) 1 1 1 2 17 /f il (3971.88 ms)
78k0r/lx3 chapter 26 option byte r01uh0004ej0501 rev.5.01 831 jun 20, 2011 figure 26-1. format of user option byte (000c0h/010c0h) (2/2) address: 000c0h/010c0h note 1 7 6 5 4 3 2 1 0 wdtinit window1 window0 wdton wdcs2 wdcs1 wdcs0 wdstbyon wdstbyon operation control of watc hdog timer counter (halt/stop mode) 0 counter operation stopped in halt/stop mode note 2 1 counter operation enabled in halt/stop mode notes 1. set the same value as 000c0h to 010c0h when t he boot swap operation is used because 000c0h is replaced by 010c0h. 2. the window open period is 100% when wdstbyon = 0, regardless the value of window1 and window0. caution the watchdog timer conti nues its operation during self-program ming of the flash memory and eeprom emulation. during processi ng, the interrupt acknowledge time is delayed. set the overflow time and window size taking th is delay into consideration. remark f il : internal low-speed oscillation clock frequency figure 26-2. format of user option byte (000c1h/010c1h) address: 000c1h/010c1h note 1 7 6 5 4 3 2 1 0 1 1 1 1 1 frqsel2 frqsel1 lvioff frqsel2 frqsel1 internal high-speed oscillator frequency 0 1 8 mhz/20 mhz note 2 1 0 1 mhz note 3 1 1 8 mhz other than the above setting prohibited lvioff setting of lvi on power application 0 lvi is on by default (lvi default start function enabled) upon reset release (upon power application) 1 lvi is off by default (lvi default start function stopped) upon reset release (upon power application) notes 1. set the same value as 000c1h to 010c1h when t he boot swap operation is used because 000c1h is replaced by 010c1h. 2. when 8 mhz or 20 mhz has been selected, the 8 mhz internal high-speed oscillator automatically starts oscillating after reset release. to use the 20 mhz internal high-speed oscillator to operate the microcontroller, oscillation is started by setting bit 0 (dscon) of the 20 mhz internal high-speed oscillation control register (dscctl) to 1 with v dd 2.7 v. the circuit cannot be changed to a 1 mhz internal high- speed oscillator while the microcontroller operates. 3. when 1 mhz has been selected, the microcontroller operates on the 1 mh z internal high-speed oscillator after reset release. the circuit cannot be changed to an 8 mhz or 20 mhz internal high-speed oscillator while the microcontroller operates. ( cautions are listed on the next page.)
78k0r/lx3 chapter 26 option byte r01uh0004ej0501 rev.5.01 832 jun 20, 2011 cautions 1. be sure to set bits 7 to 3 to ?1?. 2. even when the lvi default start function is u sed, if it is set to lvi operation prohibition by the software, it operates as follows: ? does not perform low-voltage detection during lvion = 0. ? if a reset is generated while lv ion = 0, lvion will be re-set to 1 when the cpu starts after reset release. there is a period wh en low-voltage detection cannot be performed normally, however, when a reset occurs due to wdt and illegal instruction execution. this is due to the fact that while the pulse width detected by lvi must be 200 s max., lvion = 1 is set upon reset o ccurrence, and the cpu starts opera ting without waiting for the lvi stabilization time. figure 26-3. format of option byte (000c2h/010c2h) address: 000c2h/010c2h note 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 note be sure to set ffh to 000c2h, as these addresses are re served areas. also set ffh to 010c2h when the boot swap operation is used because 000c2h is replaced by 010c2h. 26.3 format of on-chip debug option byte the format of on-chip debug option byte is shown below. figure 26-4. format of on-chip de bug option byte (000c3h/010c3h) address: 000c3h/010c3h note 7 6 5 4 3 2 1 0 ocdenset 0 0 0 0 1 0 ocdersd ocdenset ocdersd control of on-chip debug operation 0 0 disables on-chip debug operation. 0 1 setting prohibited 1 0 erases data of flash memory in case of failures in enabling on-chip debugging and authenticating on-chip debug security id. 1 1 does not erases data of flash memory in case of failures in enabling on-chip debugging and authenticating on-chip debug security id. note set the same value as 000c3h to 010c3h when the boot swap operation is used because 000c3h is replaced by 010c3h. caution bits 7 and 0 (ocdenset and ocdersd) can only be specified a value. be sure to set 000010b to bits 6 to 1. remark the value on bits 3 to 1 will be written over when t he on-chip debug function is in use and thus it will become unstable after the setting. however, be sure to set the default values (0, 1, and 0) to bits 3 to 1 at setting.
78k0r/lx3 chapter 26 option byte r01uh0004ej0501 rev.5.01 833 jun 20, 2011 26.4 setting of option byte the user option byte and on-chip debug option byte can be se t using the ra78k0r or pm+ linker option, in addition to describing to the source. when doing so, the contents set by using the linker option take pr ecedence, even if descriptions exist in the source, as mentioned below. see the ra78k0r assembler package user?s manual for how to set the linker option. a software description example of the option byte setting is shown below. opt cseg opt_byte db 36h ; does not use interval inte rrupt of watchdog timer, ; enables watchdog timer operation, ; window open period of watchdog timer is 50%, ; overflow time of watchdog timer is 2 10 /f il , ; stops watchdog timer operation during halt/stop mode db 0fbh ; select 8 mhz or 20 mhz for internal high-speed oscillator ; stops lvi default start function db 0ffh ; reserved area db 85h ; enables on-chip debug operation, does not erase flash memory ; data when security id authorization fails when the boot swap function is used during self programmi ng, 000c0h to 000c3h is switched to 010c0h to 010c3h. describe to 010c0h to 010c3h, therefore, the same values as 000c0h to 000c3h as follows. opt2 cseg at 010c0h db 36h ; does not use interval interrupt of watchdog timer, ; enables watchdog timer operation, ; window open period of watchdog timer is 50%, ; overflow time of watchdog timer is 2 10 /f il , ; stops watchdog timer operation during halt/stop mode db 0fbh ; select 8 mhz or 20 mhz for internal high-speed oscillator ; stops lvi default start function db 0ffh ; reserved area db 85h ; enables on-chip debug operation, does not erase flash memory ; data when security id authorization fails caution to specify the option byte by using assembl y language, use opt_byte as the relocation attribute name of the cseg pseudo instruct ion. to specify the option byte to 010c0h to 010c3h in order to use the boot swap function, use the relocation attribute at to specify an absolute address.
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 834 jun 20, 2011 chapter 27 flash memory the 78k0r/lx3 microcontrollers incorporate the flash me mory to which a program can be written, erased, and overwritten while mounted on the board. 27.1 writing with flash memory programmer data can be written to the flash memory on-board or o ff-board, by using a dedicated flash memory programmer. (1) on-board programming the contents of the flash memory can be rewritten afte r the 78k0r/lx3 microcontrollers have been mounted on the target system. the connectors that connect the dedicated flash memory progr ammer must be mounted on the target system. (2) off-board programming data can be written to the flash memory with a dedica ted program adapter (fa series) before the 78k0r/lx3 microcontrollers are mounted on the target system. remark the fa series is a product of na ito densei machida mfg. co., ltd. 27.2 programming environment the environment required for writing a pr ogram to the flash memory of the 78k 0r/lx3 microcontrollers are illustrated below. figure 27-1. environment for wr iting program to flash memory rs-232c usb 78k0r/lx3 microcontrollers flmd0 v dd v ss reset tool0 (dedicated single-line uart) host machine dedicated flash memory programmer pg-fp5 start power pa s s busy ng a host machine that controls the dedicated flash memory programmer is necessary. to interface between the dedicated flash memory programm er and the 78k0r/lx3 microcontrollers, the tool0 pin is used for manipulation such as writing and erasing via a dedica ted single-line uart. to writ e the flash memory off-board, a dedicated program adapter (fa series) is necessary.
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 835 jun 20, 2011 27.3 communication mode communication between the dedicated flash memory programme r and the 78k0r/lx3 microcontrollers is established by serial communication using the tool0 pin via a dedica ted single-line uart of the 78k0r/lx3 microcontrollers. transfer rate: 115,200 bps to 1,000,000 bps figure 27-2. communication with de dicated flash memory programmer v dd /ev dd v ss /ev ss reset tool0 flmd0 flmd0 v dd gnd /reset si/rxd so/txd dedicated flash memory programmer 78k0r/lx3 microcontrollers pg-fp5 start power pass busy ng when using the flashpro5 as the dedicated flash memory programmer, the flashpro5 gen erates the following signals for the 78k0r/lx3 microcontrollers. for details, refer to the user?s manual for the flashpro5. table 27-1. pin connection flashpro5 78k0r/lx3 microcontrollers connection signal name i/o pin function pin name flmd0 output mode signal flmd0 v dd i/o v dd voltage generation/power monitoring v dd , ev dd , av dd0 , av dd1 gnd ? ground v ss , ev ss , av ss clk output clock output ? /reset output reset signal reset si/rxd input receive signal tool0 so/txd output transmit signal sck output transfer clock ? remark : be sure to connect the pin. : the pin does not have to be connected.
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 836 jun 20, 2011 examples of the recommended connection ( pd78f1508a) when using the adapter for flash memory writing are shown below. figure 27-3. example of wiring ad apter for flash memory writing ( pd78f1508a) v dd (2.7 to 5.5 v) gnd 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 si/rxd notes 1, 2 so/txd note 2 sck clk /reset flmd0 writer interface gnd vdd vdd2 notes 1. this pin is not required to be connected when using pg-fp5 or fl-pr5. 2. connect si/rxd or so/txd when using qb-mini2.
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 837 jun 20, 2011 27.4 connection of pins on board to write the flash memory on-board, connectors that connect the dedicate d flash memory programmer must be provided on the target system. first provide a function that selects the normal operation mode or flash memory programming mode on the board. when the flash memory programming mode is set, all the pi ns not used for programming t he flash memory are in the same status as immediately after reset. therefore, if the external device does not recognize the state immediately after reset, the pins must be handled as described below. 27.4.1 flmd0 pin (1) in flash memory programming mode directly connect this pin to a flash memory programmer when data is written by the flash memory programmer. this supplies a writing voltage of the v dd level to the flmd0 pin. the flmd0 pin does not have to be pulled down externally becaus e it is internally pulled down by reset. to pull it down externally, use a resistor of 1 k to 200 k . (2) in normal operation mode it is recommended to leave this pin open during normal operation. the flmd0 pin must always be kept at the v ss level before reset release but does not have to be pulled down externally because it is internally pulled down by reset. however, pulling it down must be kept selected (i.e., flmdpup = ?0?, default value) by using bit 7 (flmdpup) of the background event cont rol register (bectl) (see 27.5 (1) back ground event control register ). to pull it down externally, use a resistor of 200 k or smaller. self programming and the rewr iting of flash memory with the programmer can be prohibited using hardware, by directly connecting this pin to the v ss pin. (3) in self programming mode it is recommended to leave this pin open when using the self programming function. to pull it down externally, use a resistor of 100 k to 200 k . in the self programming mode, the setting is swit ched to pull up in the self programming library. figure 27-4. flmd0 pin connection example 78k0r/lx3 microcontrollers flmd0 dedicated flash memory programmer connection pin
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 838 jun 20, 2011 27.4.2 tool0 pin in the flash memory programming mode, connect this pin dire ctly to the dedicated flash memory programmer or pull it up by connecting it to ev dd via an external resistor. when on-chip debugging is enabled in the normal operation mode, pull this pin up by connecting it to v dd via an external resistor, and be sure to keep inputting the v dd level to the tool0 pin before reset is released (pulling down this pin is prohibited). remark the sau and iica pins are not used for communi cation between the 78k0r/lx3 microcontrollers and dedicated flash memory programmer, because single-line uart is used. 27.4.3 reset pin signal conflict will occur if the reset signal of the dedic ated flash memory programmer is connected to the reset pin that is connected to the reset signal gener ator on the board. to prevent this conf lict, isolate the connection with the reset signal generator. the flash memory will not be correctly pr ogrammed if the reset signal is input from the user system while the flash memory programming mode is set . do not input any signal other than the reset signal of the dedicated flash memory programmer. figure 27-5. signal conflict (reset pin) input pin dedicated flash memory programmer connection pin another device signal conflict output pin in the flash memory programming mode, a signal output by another device will conflict with the signal output by the dedicated flash memory programmer. therefore, isolate the signal of another device. 78k0r/lx3 microcontrollers 27.4.4 port pins when the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. if external devi ces connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to v dd or v ss via a resistor. 27.4.5 regc pin connect the regc pin to gnd via a capacitor (0.47 to 1 f) in the same manner as during normal operation. also, use a capacitor with good characteristics, si nce it is used to stabilize internal voltage. 27.4.6 x1 and x2 pins connect x1 and x2 in the same status as in the normal operation mode. remark in the flash memory programming mode, the internal high-speed oscillation clock (f ih ) is used.
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 839 jun 20, 2011 27.4.7 power supply to use the supply voltage output of t he flash memory programmer, connect the v dd pin to v dd of the flash memory programmer, and the v ss pin to gnd of the flash memory programmer. to use the on-board supply voltage, connect in compliance with the normal operation mode. however, when using the on-board suppl y voltage, be sure to connect the v dd and v ss pins to v dd and gnd of the flash memory programmer to use the power moni tor function with the flash memory programmer. supply the same other power supplies (ev dd , ev ss , av dd0 , av dd1 , and av ss ) as those in the normal operation mode. 27.5 registers controlling flash memory (1) background event control register (bectl) even if the flmd0 pin is not controlled externally, it can be controlled by softw are with the bectl register to set the self-programming mode. however, depending on the processing of the flmd0 pin, it may not be possible to set the self-programming mode by software. when using bectl, leaving the flmd0 pin open is recommended. when pulling it down externally, use a resistor with a resistance of 100 k or more. in addition, in the normal operation mode, use bectl with the pull down selection. in the self-programming mode, the setti ng is switched to pull up in the self- programming library. the bectl register is set by a 1-bit or 8-bit memory manipula tion instruction. reset input sets this register to 00h. figure 27-6. format of background event control register (bectl) address: fffbeh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 bectl flmdpup 0 0 0 0 0 0 0 flmdpup software control of flmd0 pin 0 selects pull-down 1 selects pull-up
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 840 jun 20, 2011 27.6 programming method 27.6.1 controlling flash memory the following figure illustrates the proc edure to manipulate the flash memory. figure 27-7. flash memory manipulation procedure start manipulate flash memory end? yes controlling flmd0 pin and reset pin no end flash memory programming mode is set 27.6.2 flash memory programming mode to rewrite the contents of the flash memory by using the dedicated fl ash memory programmer, set the 78k0r/lx3 microcontrollers in the flash memory programming mode. to set the mode, set the flmd0 pin and tool0 pin to v dd and clear the reset signal. change the mode by using a jumper when writing the flash memory on-board. figure 27-8. flash memory programming mode v dd reset 5.5 v 0 v v dd 0 v flmd0 v dd 0 v tool0 v dd 0 v flash memory programming mode
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 841 jun 20, 2011 table 27-2. relationship between flmd0 pi n and operation mode after reset release flmd0 operation mode 0 normal operation mode v dd flash memory programming mode 27.6.3 selecting communication mode communication mode of the 78k0r/lx3 microcontrollers as follows. table 27-3. communication modes standard setting note 1 communication mode port speed frequency multiply rate pins used 1-line mode (dedicated single-line uart) uart-ch0 1 mbps note 2 ? ? tool0 notes 1. selection items for standard settings on gu i of the flash memory programmer. 2. because factors other than the baud rate error, such as the signal waveform slew, also affect uart communication, thoroughly evaluate the slew as well as the baud rate error. 27.6.4 communication commands the 78k0r/lx3 microcontrollers communicate with the dedic ated flash memory programmer by using commands. the signals sent from the flash memory programmer to the 78k 0r/lx3 microcontrollers are called commands, and the signals sent from the 78k0r/lx3 microcontrollers to the ded icated flash memory programmer are called response. figure 27-9. communication commands command response dedicated flash memory programmer pg-fp5 start power pass busy ng 78k0r/lx3 microcontrollers the flash memory control commands of the 78k0r/lx3 microcontrollers are listed in the table below. all these commands are issued from the programmer, and the 78k0r/lx3 microcontrollers perform processing corresponding to the respective commands.
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 842 jun 20, 2011 table 27-4. flash memory control commands classification command name function verify verify compares the contents of a specified area of the flash memory with data transmitted from the programmer. chip erase erases the entire flash memory. erase block erase erases a specified area in the flash memory. blank check block blank check checks if a specified block in the flash memory has been correctly erased. write programming writes data to a sp ecified area in the flash memory. silicon signature gets 78k0r/lx3 microcontrollers information (such as the part number and flash memory configuration). version get gets the 78k0r/lx3 mi crocontrollers firmware version. getting information checksum gets the checksum data for a specified area. security security set sets security information. reset used to detect synchronization status of communication. others baud rate set sets baud rate when uart communication mode is selected. the 78k0r/lx3 microcontrollers return a response for the command issued by the dedicated flash memory programmer. the response names sent from t he 78k0r/lx3 microcontrollers are listed below. table 27-5. response names response name function ack acknowledges command/data. nak acknowledges illegal command/data.
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 843 jun 20, 2011 27.7 security settings the 78k0r/lx3 microcontrollers support a security function t hat prohibits rewriting the us er program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. the operations shown below can be performed using the securi ty set command. the security setting is valid when the programming mode is set next. ? disabling batch erase (chip erase) execution of the block erase and batch erase (chip eras e) commands for entire blocks in the flash memory is prohibited by this setting during on-board/off-board programming. once execution of the batch erase (chip erase) command is prohibited, all of the prohibition settings (including prohibition of batch erase (chip erase)) can no longer be cancelled. caution after the security setting for th e batch erase is set, erasure cannot be performed for the device. in addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be writ ten, because the erase command is disabled. ? disabling block erase execution of the block erase command for a specific block in the flash memory is prohibited during on-board/off-board programming. however, blocks can be erased by means of self programming. ? disabling write execution of the write and block erase commands for entire blocks in the flash memory is prohibited during on- board/off-board programming. however, blocks can be written by means of self programming. ? disabling rewriting boot cluster 0 execution of the batch erase (chip erase) command, block erase command, and write command on boot cluster 0 (00000h to 00fffh) in the flash memo ry is prohibited by this setting. caution if a security setting that rewrites boot cluster 0 has been applied, boot cl uster 0 of that device will not be rewritten, and the entire flash memory of the device will not be erased in batch. the batch erase (chip erase), block erase, write commands, and rewriting boot cluster 0 are enabled by the default setting when the flash memory is shipped. security can be set by on-board/off-board programming and self programming. each security setting can be used in combination. all the security settings are cleared by exec uting the batch erase (chip erase) command. table 27-6 shows the relationship between the erase and write commands when the 78k0r/lx3 microcontrollers security function is enabled. remark to prohibit writing and erasing during self-progra mming, use the flash sealed window function (see 27.8.2 for detail).
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 844 jun 20, 2011 table 27-6. relationship between en abling security function and command (1) during on-board/off-board programming executed command valid security batch erase (chip erase) block erase write prohibition of batch erase (c hip erase) cannot be erased in batch can be performed note . prohibition of block erase can be performed. prohibition of writing can be erased in batch. blocks cannot be erased. cannot be performed. prohibition of rewriting boot cluster 0 cannot be erased in batch boot cluster 0 cannot be erased. boot cluster 0 cannot be written. note confirm that no data has been wri tten to the write area. because dat a cannot be erased after batch erase (chip erase) is prohibited, do not wr ite data if the data has not been erased. (2) during self programming executed command valid security block erase write prohibition of batch erase (chip erase) prohibition of block erase prohibition of writing blocks can be erased. can be performed. prohibition of rewriting boot cluster 0 boot cluster 0 cannot be erased. boot cluster 0 cannot be written. remark to prohibit writing and erasing during self-progra mming, use the flash sealed window function (see 27.8.2 for detail). table 27-7. setting security in each programming mode (1) on-board/off-board programming security security setting how to disable security setting prohibition of batch erase (chip er ase) cannot be disabled after set. prohibition of block erase prohibition of writing execute batch erase (chip erase) command prohibition of rewriting boot cluster 0 set via gui of dedicated flash memory programmer, etc. cannot be disabled after set. (2) self programming security security setting how to disable security setting prohibition of batch erase (chip er ase) cannot be disabled after set. prohibition of block erase prohibition of writing prohibition of rewriting boot cluster 0 set by using information library. execute batch erase (chip erase) command during on-board/off-board programming (cannot be disabled during self programming)
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 845 jun 20, 2011 27.8 flash memory programming by self-programming the 78k0r/lx3 microcontrollers support a self-programming f unction that can be used to re write the flash memory via a user program. because this function allows a user applic ation to rewrite the flash me mory by using the 78k0r/lx3 microcontrollers self-programming library, it c an be used to upgrade the program in the field. if an interrupt occurs during self-programming, self-progr amming can be temporarily stopped and interrupt servicing can be executed. if an unmasked interrupt request is generated in t he ei state, the request br anches directly from the self-programming library to the interrupt routine. after the self-programming m ode is later restored, self-programming can be resumed. however, the interrupt response time is different from that of the normal operation mode. cautions 1. the self-programming f unction cannot be used when the cp u operates with the subsystem clock. 2. in the self-programming mode, call the self-programming start library (flashstart). 3. to prohibit an interrupt during self-progra mming, in the same way as in the normal operation mode, execute the self-programming library in the stat e where the ie flag is cleared (0) by the di instruction. to enable an inte rrupt, clear (0) the interrupt mask flag to accept in the state where the ie flag is set (1) by the ei instructio n, and then execute the self-programming library. 4. in low-power-consumption mode, use the regulator with f clk fixed to 1 mhz when executing self programming. for details of the low-power-consumption mode, see chapter 25 regulator. 5. disable dma operation (denn = 0) duri ng the execution of self programming library functions.
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 846 jun 20, 2011 the following figure illustrates a flow of rewriting t he flash memory by using a self programming library. figure 27-10. flow of self programming (rewriting flash memory) flashstart flashenv checkflmd flashblockblankcheck yes no flashblockerase flashwordwrite flashblockverify flashend yes no no flashblockerase flashwordwrite flashblockverify yes start of self programming normal completion setting operating environment normal completion? end of self programming normal completion? normal completion? error
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 847 jun 20, 2011 27.8.1 boot swap function if rewriting the boot area failed by temporary power failure or other reasons, restarting a program by resetting or overwriting is disabled due to dat a destruction in the boot area. the boot swap function is used to avoid this problem. before erasing boot cluster 0 note , which is a boot program area, by self-pro gramming, write a new boot program to boot cluster 1 in advance. when the program has been correctly wr itten to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmware of the 78k0r/lx3 microcontrollers, so that boot cluster 1 is used as a boot area. after that, erase or writ e the original boot program area, boot cluster 0. as a result, even if a power failure occurs while the boot programming area is being rewri tten, the program is executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next. note a boot cluster is a 4 kb area and boot clusters 0 and 1 are swapped by the boot swap function. figure 27-11. boot swap function boot program (boot cluster 0) new boot program (boot cluster 1) user program self-programming to boot cluster 1 self-programming to boot cluster 0 execution of boot swap by firmware user program boot program (boot cluster 0) user program new user program (boot cluster 0) new boot program (boot cluster 1) user program new boot program (boot cluster 1) boot program (boot cluster 0) user program xxxxxh 02000h 00000h 01000h boot boot boot boot in an example of above figure, it is as follows. boot cluster 0: boot program area before boot swap boot cluster 1: boot program area after boot swap
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 848 jun 20, 2011 figure 27-12. example of executing boot swapping 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 boot cluster 1 booted by boot cluster 0 block number erasing block 4 boot cluster 0 program 01000h 00000h boot program program program program boot program boot program boot program program program program boot program boot program boot program boot program boot program boot program boot program boot program program program program boot program boot program boot program boot program boot program boot program boot program boot program erasing block 5 erasing block 6 erasing block 7 boot program boot program boot program boot program boot program boot program boot program boot program boot program boot program boot program boot program boot program boot program booted by boot cluster 1 01000h 00000h erasing block 6 erasing block 7 erasing block 4 erasing block 5 boot swap writing blocks 4 to 7 writing blocks 4 to 7 01000h 00000h new boot program new program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program new program new program new program
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 849 jun 20, 2011 27.8.2 flash shield window function the flash shield window function is provided as one of the security functions for self programming. it disables writing to and erasing areas outside the range specified as a window only during self programming. the window range can be set by specifying the start and en d blocks. the window range can be set or changed during both on-board/off-board programming and self programming. writing to and erasing areas outside the window range ar e disabled during self programming. during on-board/off- board programming, however, areas outside the range s pecified as a window can be written and erased. figure27-13. flash shield window setting example (target devices: pd78f1500a, start block: 04h, end block: 06h) block 00h block 01h block 02h block 03h block 05h block 06h (end block) block 04h (start block) block 3fh block 3eh : on-board/off-board programming : self programming : on-board/off-board programming : self programming : on-board/off-board programming : self programming flash memory area flash shield range methods by which writing can be performed window range flash shield range 0ffffh 01c00h 01bffh 01000h 00fffh 00000h caution if the rewrite-prohibited area of the boot cl uster 0 overlaps with the flash shield window range, prohibition to rewrite the bo ot cluster 0 takes priority. table 27-8. relationship between flash shield wi ndow function setting/change methods and commands execution commands programming conditions window range setting/change methods block erase write self-programming specify the starting and ending blocks by the set information library. block erasing is enabled only within the window range. writing is enabled only within the range of window range. on-board/off-board programming specify the starting and ending blocks on gui of dedicated flash memory programmer, etc. block erasing is enabled also outside the window range. writing is enabled also outside the window range. remark see 27.7 security settings to prohibit writing/erasing during on-board/off-board programming.
78k0r/lx3 chapter 27 flash memory r01uh0004ej0501 rev.5.01 850 jun 20, 2011 27.9 creating rom code to place order for previously written product before placing an order with renesas electronics for a previ ously written product, the rom code for the order must be created. to create the rom code, use the hex co nsolidation utility (hereafter abbrevia ted to hcu) on the finished programs (hex files) and optional data (such as security settings for flash memory programs). the hcu is a software tool that includes functions required for creating rom code. the hcu can be downloaded at t he renesas electronics website. (1) website http://www2.renesas.com/micro/en/ods/ click version-up service. (2) downloading the hcu to download the hcu, click software for previ ously written flash products and then hcu_gui. remark for details about how to install and use the hcu, s ee the materials (the user?s manual) that comes with the hcu at the above website. 27.9.1 procedure for using ro m code to place an order use the hcu to create the rom code by following the pr ocedure below, and then place your order with renesas electronics. for details, see the rom code ordering method information (c10302j). customer renesas electronics decide which product to order. renesas electronics processes the product name and number and creates a record of the transaction. create the rom code note check the rom order details and generate the required data. renesas electronics processes the rom code. note use the hcu to create the rom code for the order. send the order information. renesas electronics sends the order number and other order-related information. send the data required for the rom order.
78k0r/lx3 chapter 28 on-chip debug function r01uh0004ej0501 rev.5.01 851 jun 20, 2011 chapter 28 on-chip debug function 28.1 connecting qb-mini2 to 78k0r/lx3 microcontrollers the 78k0r/lx3 microcontrollers use the v dd , flmd0, reset, tool0, tool1 note 1 , and v ss pins to communicate with the host machine via an on-chip debug emulator (qb-mini2). caution the 78k0r/lx3 microcontrollers have an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug f unction in products designa ted for mass production, because the guarant eed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefor e cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. figure 28-1. connection example of qb-mini2 and 78k0r/lx3 microcontrollers v dd flmd0 tool0 reset_in clk_in rxd note 2 flmd0 reset v dd reset_out qb-mini2 target connector gnd tool1 note 1 v ss ev dd txd note 2 78k0r/lx3 microcontrollers target reset notes 1. connection is not required for communication in 1-line mode but required for communication in 2-line mode. at this time, perform necessary connections according to table 2-2 connection of unused pins since tool1 is an unused pin when qb-mini2 is unconnected. 2. connecting the dotted line is not necessary sinc e rxd and txd are shorted within qb-min2. when using the other flash memory programmer, rxd and txd may not be shorted within the programmer. in this case, they must be shorted on the target system. remark the flmd0 pin is recommended to be open for self-programming in on-chip debugging. to pull down externally, use a resistor of 100 k or more. 1-line mode (single line uart) using the tool0 pin or 2-li ne mode using the tool0 and tool1 pins is used for serial communication for flash memory programming, 1-line mode is used. 1-line mode or 2-line mode is used for on-chip debugging. table 28-1 lists the differences between 1-line mode and 2-line mode.
78k0r/lx3 chapter 28 on-chip debug function r01uh0004ej0501 rev.5.01 852 jun 20, 2011 table 28-1. lists the differences be tween 1-line mode and 2-line mode. communicat ion mode flash memory programming function debugging function 1-line mode available ? pseudo real-time ram monitor (rrm) function not supported. ? dmm function (rewriting memory in run) not supported. ? the debugger speed is two to four times slower than 2-line mode. 2-line mode none ? pseudo real-time ram monitor (rrm) function supported ? dmm function (rewriting memory in run) supported remark 2-line mode is not used for flash programming, however, even if tool1 pin is conn ected with clk_in of qb- mini2, writing is performed normally with no problem. 28.2 on-chip debug security id the 78k0r/lx3 microcontrollers have an on-chip debug opera tion control bit in the flash memory at 000c3h (see chapter 26 option byte ) and an on-chip debug security id setting area at 000c4h to 000cdh, to prevent third parties from reading memory content. when the boot swap function is used, also set a value that is the same as that of 010c3h and 010c4h to 010cdh in advance, because 000c3h, 000c4h to 000cdh and 010c3h, and 010c4h to 010cdh are switched. for details on the on-chip debug security id, refer to the qb-mini2 on-chip debug emulator with programming function user?s manual (u18371e) . table 28-2. on-chip debug security id address on-chip debug security id 000c4h to 000cdh 010c4h to 010cdh any id code of 10 bytes 28.3 securing of user resources to perform communication between the 78k0r/lx3 microcontro llers and qb-mini2, as well as each debug function, the securing of memory space must be done beforehand. if renesas electronics assembler ra78k0r or compiler cc78k0r is used, the items can be set by using linker options. (1) securement of memory space the shaded portions in figure 28-2 are the areas rese rved for placing the debug monitor program, so user programs or data cannot be allocated in these spaces. when using the on-chip debug function, these spaces must be secured so as not to be used by the user program. moreover, this area must not be rewritten by the user program.
78k0r/lx3 chapter 28 on-chip debug function r01uh0004ej0501 rev.5.01 853 jun 20, 2011 figure 28-2. memory spaces where de bug monitor programs are allocated (1 kb) : area used for on-chip debugging note 1 note 2 internal rom use prohibited internal ram internal rom area boot cruster 1 debug monitor area (10 bytes) debug monitor area (2 bytes) debug monitor area (2 bytes) security id area (10 bytes) debug monitor area (10 bytes) security id area (10 bytes) on-chip debug option byte area (1 byte) on-chip debug option byte area (1 byte) note 2 stack area for debugging (6 bytes) note 3 02000h 010d8h 010ceh 010c4h 010c3h 01002h 01000h 000d8h 000ceh 000c4h 000c3h 00002h 00000h internal ram area boot cruster 0 notes 1. address differs depending on products as follows. products internal rom address pd78f1500a, 78f1503a, 78f1506a, 78f1510a, 78f1513a, 78f1516a 64 kb 0fc00h to 0ffffh pd78f1501a, 78f1504a, 78f1507a 96 kb 17c00h to 17fffh pd78f1502a, 78f1505a, 78f1508a, 78f1512a, 78f1515a, 78f1518a 128 kb 1fc00h to 1ffffh 2. in debugging, reset vector is rewritten to address allocated to a monitor program. 3. since this area is allocated immediately before the st ack area, the address of this area varies depending on the stack increase and decrease. that is, 6 ex tra bytes are consumed for the stack area used. for details of the way to secure of the memory space, refer to the qb-mini2 on-chip debug emulator with programming function u ser?s manual (u18371e) .
78k0r/lx3 chapter 29 bcd correction circuit r01uh0004ej0501 rev.5.01 854 jun 20, 2011 chapter 29 bcd correction circuit 29.1 bcd correction circuit function the bcd correction circuit is mounted onto all 78k0r/lx3 microcontroller products. the result of addition/subtraction of the bcd (binary-coded decimal) code and bcd code can be obtained as bcd code with this circuit. the decimal correction operation result is obtained by performing addition/subt raction having the a register as the operand and then adding/ subtracting the bcdadj register. 29.2 registers used by bcd correction circuit the bcd correction circuit uses the following registers. ? bcd correction result register (bcdadj) (1) bcd correction result register (bcdadj) the bcdadj register stores correction values for obt aining the add/subtract re sult as bcd code through add/subtract instructions using t he a register as the operand. the value read from the bcdadj register varies depending on the value of the a register when it is read and those of the cy and ac flags. bcdadj is read by an 8-bit memory manipulation instruction. reset input sets this register to undefined. figure 29-1. format of bcd correct ion result register (bcdadj) address: f00feh after reset: undefined r symbol 7 6 5 4 3 2 1 0 bcdadj
78k0r/lx3 chapter 29 bcd correction circuit r01uh0004ej0501 rev.5.01 855 jun 20, 2011 29.3 bcd correction circuit operation the basic operation of the bcd correction circuit is as follows. (1) addition: calculating the result of adding a bcd code value and another bcd code value by using a bcd code value <1> the bcd code value to which addition is performed is stored in the a register. <2> by adding the value of the a r egister and the second operand (value of one more bcd code to be added) as are in binary, the binary operation result is stored in the a register and the correctio n value is stored in the bcdadj register. <3> decimal correction is performed by adding in binary the value of the a register (add ition result in binary) and the bcdadj register (correction value), and the correctio n result is stored in the a register and cy register. caution the value read from the bcdadj register varies depending on the value of the a register when it is read and those of the cy and ac flags. therefore, execute the instruction <3> after the instruction <2> inst ead of executing any other in structions. to perform bcd correction in the interrupt enabled state, sa ving and restoring the a register is required within the interrupt function. psw (cy flag and ac flag) is restored by the reti instruction. an example is shown below. examples 1: 99 + 89 = 188 instruction a register cy register ac flag bcdadj register mov a, #99h ; <1> 99h ? ? ? add a, #89h ; <2> 22h 1 1 66h add a, !bcdadj ; <3> 88h 1 0 ? examples 2: 85 + 15 = 100 instruction a register cy register ac flag bcdadj register mov a, #85h ; <1> 85h ? ? ? add a, #15h ; <2> 9ah 0 0 66h add a, !bcdadj ; <3> 00h 1 1 ? examples 3: 80 + 80 = 160 instruction a register cy register ac flag bcdadj register mov a, #80h ; <1> 80h ? ? ? add a, #80h ; <2> 00h 1 0 60h add a, !bcdadj ; <3> 60h 1 0 ?
78k0r/lx3 chapter 29 bcd correction circuit r01uh0004ej0501 rev.5.01 856 jun 20, 2011 (2) subtraction: calculating the r esult of subtracting a bcd code valu e from another bcd code value by using a bcd code value <1> the bcd code value from which subtracti on is performed is stored in the a register. <2> by subtracting the value of the second operand (value of bcd code to be subtracted) from the a register as is in binary, the calculation result in binary is stored in the a register, and the correct ion value is stored in the bcdadj register. <3> decimal correction is performed by subtracting the value of the bcdadj register (co rrection value) from the a register (subtraction result in binary) in binary, and t he correction result is stored in the a register and cy register. caution the value read from the bcdadj register varies depending on the value of the a register when it is read and those of the cy and ac flags. therefore, execute the instruction <3> after the instruction <2> inst ead of executing any other in structions. to perform bcd correction in the interrupt enabled state, sa ving and restoring the a register is required within the interrupt function. psw (cy flag and ac flag) is restored by the reti instruction. an example is shown below. example: 91 ? 52 = 39 instruction a register cy register ac flag bcdadj register mov a, #91h ; <1> 91h ? ? ? sub a, #52h ; <2> 3fh 0 1 06h sub a, !bcdadj ; <3> 39h 0 0 ?
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 857 jun 20, 2011 chapter 30 instruction set this chapter lists the instructions in the 78k0r microcontroller instruction set. for details of each operation and operation code, refer to the separate document 78k0r microcontrollers instru ctions user?s manual (u17792e) . remark the shaded parts of the tables in table 30-5 operation list indicate the operation or instruction format that is newly added for the 78k0r microcontrollers. 30.1 conventions used in operation list 30.1.1 operand identifier s and specification methods operands are described in the ?operand? co lumn of each instruction in accordance with the descripti on method of the instruction operand identifier (refer to the assembler specifications for details). when there are two or more description methods, select one of them. alphabetic letters in capitals and the symbols, #, !, !!, $, $!, [ ], and es: are keywords and are described as they are. ea ch symbol has the following meaning. ? #: immediate data specification ? !: 16-bit absolute address specification ? !!: 20-bit absolute address specification ? $: 8-bit relative address specification ? $!: 16-bit relative address specification ? [ ]: indirect address specification ? es: extension address specification in the case of immediate data, describe an appropriate num eric value or a label. when using a label, be sure to describe the #, !, !!, $, $!, [ ], and es: symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1 , r2, etc.) can be used for description. table 30-1. operand identifi ers and specification methods identifier description method r rp sfr sfrp x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special-function register symbol (sfr symbol) special-function register sy mbols (16-bit manipulatable sf r symbol. even addresses only note ) saddr saddrp ffe20h to fff1fh immediate data or labels ffe20h to ff1fh immediate data or labels (even addresses only note ) addr20 addr16 addr5 00000h to fffffh immediate data or labels 0000h to ffffh immediate data or labels (only ev en addresses for 16-bit data transfer instructions note ) 0080h to 00bfh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label rbn rb0 to rb3 note bit 0 = 0 when an odd address is specified.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 858 jun 20, 2011 30.1.2 description of operation column the operation when the instruction is exec uted is shown in the ?operation? colu mn using the following symbols. table 30-2. symbols in ?operation? column symbol function a a register; 8-bit accumulator x x register b b register c c register d d register e e register h h register l l register es es register cs cs register ax ax register pair; 16-bit accumulator bc bc register pair de de register pair hl hl register pair pc program counter sp stack pointer psw program status word cy carry flag ac auxiliary carry flag z zero flag rbs register bank select flag ie interrupt request enable flag () memory contents indicated by address or register contents in parentheses x h , x l x s , x h , x l 16-bit registers: x h = higher 8 bits, x l = lower 8 bits 20-bit registers: x s = (bits 19 to 16), x h = (bits 15 to 8), x l = (bits 7 to 0) logical product (and) logical sum (or) exclusive logical sum (exclusive or) ? inverted data addr5 16-bit immediate data (even addresses only in 0080h to 00bfh) addr16 16-bit immediate data addr20 20-bit immediate data jdisp8 signed 8-bit data (displacement value) jdisp16 signed 16-bit data (displacement value)
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 859 jun 20, 2011 30.1.3 description of flag operation column the change of the flag value when the instru ction is executed is shown in the ?flag? column using the following symbols. table 30-3. symbols in ?flag? column symbol change of flag value (blank) 0 1 r unchanged cleared to 0 set to 1 set/cleared according to the result previously saved value is restored 30.1.4 prefix instruction instructions with ?es:? have a prefix oper ation code as a prefix to extend the accessible data area to the 1 mb space (00000h to fffffh), by adding the es register value to the 64 kb space from f0000h to fffffh. when a prefix operation code is attached as a prefix to the target instruct ion, only one instruction immediately after the prefix operation code is executed as the addresses wit h the es register value added. table 30-4. use example of prefix operation code opcode instruction 1 2 3 4 5 mov !addr16, #byte cfh !addr16 #byte ? mov es:!addr16, #byte 11h cfh !addr16 #byte mov a, [hl] 8bh ? ? ? ? mov a, es:[hl] 11h 8bh ? ? ? caution set the es register value with mov es, a, etc., before executing th e prefix instruction.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 860 jun 20, 2011 30.2 operation list table 30-5. operation list (1/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy r, #byte 2 1 ? r byte saddr, #byte 3 1 ? (saddr) byte sfr, #byte 3 1 ? sfr byte !addr16, #byte 4 1 ? (addr16) byte a, r note 3 1 1 ? a r r, a note 3 1 1 ? r a a, saddr 2 1 ? a (saddr) saddr, a 2 1 ? (saddr) a a, sfr 2 1 ? a sfr sfr, a 2 1 ? sfr a a, !addr16 3 1 4 a (addr16) !addr16, a 3 1 ? (addr16) a psw, #byte 3 3 ? psw byte a, psw 2 1 ? a psw psw, a 2 3 ? psw a es, #byte 2 1 ? es byte es, saddr 3 1 ? es (saddr) a, es 2 1 ? a es es, a 2 1 ? es a cs, #byte 3 1 ? cs byte a, cs 2 1 ? a cs cs, a 2 1 ? cs a a, [de] 1 1 4 a (de) [de], a 1 1 ? (de) a [de + byte], #byte 3 1 ? (de + byte) byte a, [de + byte] 2 1 4 a (de + byte) [de + byte], a 2 1 ? (de + byte) a a, [hl] 1 1 4 a (hl) [hl], a 1 1 ? (hl) a 8-bit data transfer mov [hl + byte], #byte 3 1 ? (hl + byte) byte notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 861 jun 20, 2011 table 30-5. operation list (2/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, [hl + byte] 2 1 4 a (hl + byte) [hl + byte], a 2 1 ? (hl + byte) a a, [hl + b] 2 1 4 a (hl + b) [hl + b], a 2 1 ? (hl + b) a a, [hl + c] 2 1 4 a (hl + c) [hl + c], a 2 1 ? (hl + c) a word[b], #byte 4 1 ? (b + word) byte a, word[b] 3 1 4 a (b + word) word[b], a 3 1 ? (b + word) a word[c], #byte 4 1 ? (c + word) byte a, word[c] 3 1 4 a (c + word) word[c], a 3 1 ? (c + word) a word[bc], #byte 4 1 ? (bc + word) byte a, word[bc] 3 1 4 a (bc + word) word[bc], a 3 1 ? (bc + word) a [sp + byte], #byte 3 1 ? (sp + byte) byte a, [sp + byte] 2 1 ? a (sp + byte) [sp + byte], a 2 1 ? (sp + byte) a b, saddr 2 1 ? b (saddr) b, !addr16 3 1 4 b (addr16) c, saddr 2 1 ? c (saddr) c, !addr16 3 1 4 c (addr16) x, saddr 2 1 ? x (saddr) x, !addr16 3 1 4 x (addr16) es:!addr16, #byte 5 2 ? (es, addr16) byte a, es:!addr16 4 2 5 a (es, addr16) es:!addr16, a 4 2 ? (es, addr16) a a, es:[de] 2 2 5 a (es, de) es:[de], a 2 2 ? (es, de) a es:[de + byte],#byte 4 2 ? ((es, de) + byte) byte a, es:[de + byte] 3 2 5 a ((es, de) + byte) 8-bit data transfer mov es:[de + byte], a 3 2 ? ((es, de) + byte) a notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 862 jun 20, 2011 table 30-5. operation list (3/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, es:[hl] 2 2 5 a (es, hl) es:[hl], a 2 2 ? (es, hl) a es:[hl + byte],#byte 4 2 ? ((es, hl) + byte) byte a, es:[hl + byte] 3 2 5 a ((es, hl) + byte) es:[hl + byte], a 3 2 ? ((es, hl) + byte) a a, es:[hl + b] 3 2 5 a ((es, hl) + b) es:[hl + b], a 3 2 ? ((es, hl) + b) a a, es:[hl + c] 3 2 5 a ((es, hl) + c) es:[hl + c], a 3 2 ? ((es, hl) + c) a es:word[b], #byte 5 2 ? ((es, b) + word) byte a, es:word[b] 4 2 5 a ((es, b) + word) es:word[b], a 4 2 ? ((es, b) + word) a es:word[c], #byte 5 2 ? ((es, c) + word) byte a, es:word[c] 4 2 5 a ((es, c) + word) es:word[c], a 4 2 ? ((es, c) + word) a es:word[bc], #byte 5 2 ? ((es, bc) + word) byte a, es:word[bc] 4 2 5 a ((es, bc) + word) es:word[bc], a 4 2 ? ((es, bc) + word) a b, es:!addr16 4 2 5 b (es, addr16) c, es:!addr16 4 2 5 c (es, addr16) mov x, es:!addr16 4 2 5 x (es, addr16) a, r note 3 1 (r = x) 2 (other than r = x) 1 ? a r a, saddr 3 2 ? a (saddr) a, sfr 3 2 ? a sfr a, !addr16 4 2 ? a (addr16) a, [de] 2 2 ? a (de) a, [de + byte] 3 2 ? a (de + byte) a, [hl] 2 2 ? a (hl) a, [hl + byte] 3 2 ? a (hl + byte) a, [hl + b] 2 2 ? a (hl + b) 8-bit data transfer xch a, [hl + c] 2 2 ? a (hl + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 863 jun 20, 2011 table 30-5. operation list (4/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, es:!addr16 5 3 ? a (es, addr16) a, es:[de] 3 3 ? a (es, de) a, es:[de + byte] 4 3 ? a ((es, de) + byte) a, es:[hl] 3 3 ? a (es, hl) a, es:[hl + byte] 4 3 ? a ((es, hl) + byte) a, es:[hl + b] 3 3 ? a ((es, hl) + b) xch a, es:[hl + c] 3 3 ? a ((es, hl) + c) a 1 1 ? a 01h x 1 1 ? x 01h b 1 1 ? b 01h c 1 1 ? c 01h saddr 2 1 ? (saddr) 01h !addr16 3 1 ? (addr16) 01h oneb es:!addr16 4 2 ? (es, addr16) 01h a 1 1 ? a 00h x 1 1 ? x 00h b 1 1 ? b 00h c 1 1 ? c 00h saddr 2 1 ? (saddr) 00h !addr16 3 1 ? (addr16) 00h clrb es:!addr16 4 2 ? (es,addr16) 00h [hl + byte], x 3 1 ? (hl + byte) x 8-bit data transfer movs es:[hl + byte], x 4 2 ? (es, hl + byte) x rp, #word 3 1 ? rp word saddrp, #word 4 1 ? (saddrp) word sfrp, #word 4 1 ? sfrp word ax, saddrp 2 1 ? ax (saddrp) saddrp, ax 2 1 ? (saddrp) ax ax, sfrp 2 1 ? ax sfrp sfrp, ax 2 1 ? sfrp ax ax, rp note 3 1 1 ? ax rp 16-bit data transfer movw rp, ax note 3 1 1 ? rp ax notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except rp = ax remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 864 jun 20, 2011 table 30-5. operation list (5/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy ax, !addr16 3 1 4 ax (addr16) !addr16, ax 3 1 ? (addr16) ax ax, [de] 1 1 4 ax (de) [de], ax 1 1 ? (de) ax ax, [de + byte] 2 1 4 ax (de + byte) [de + byte], ax 2 1 ? (de + byte) ax ax, [hl] 1 1 4 ax (hl) [hl], ax 1 1 ? (hl) ax ax, [hl + byte] 2 1 4 ax (hl + byte) [hl + byte], ax 2 1 ? (hl + byte) ax ax, word[b] 3 1 4 ax (b + word) word[b], ax 3 1 ? (b + word) ax ax, word[c] 3 1 4 ax (c + word) word[c], ax 3 1 ? (c + word) ax ax, word[bc] 3 1 4 ax (bc + word) word[bc], ax 3 1 ? (bc + word) ax ax, [sp + byte] 2 1 ? ax (sp + byte) [sp + byte], ax 2 1 ? (sp + byte) ax bc, saddrp 2 1 ? bc (saddrp) bc, !addr16 3 1 4 bc (addr16) de, saddrp 2 1 ? de (saddrp) de, !addr16 3 1 4 de (addr16) hl, saddrp 2 1 ? hl (saddrp) hl, !addr16 3 1 4 hl (addr16) ax, es:!addr16 4 2 5 ax (es, addr16) es:!addr16, ax 4 2 ? (es, addr16) ax ax, es:[de] 2 2 5 ax (es, de) es:[de], ax 2 2 ? (es, de) ax ax, es:[de + byte] 3 2 5 ax ((es, de) + byte) es:[de + byte], ax 3 2 ? ((es, de) + byte) ax ax, es:[hl] 2 2 5 ax (es, hl) 16-bit data transfer movw es:[hl], ax 2 2 ? (es, hl) ax notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 865 jun 20, 2011 table 30-5. operation list (6/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy ax, es:[hl + byte] 3 2 5 ax ((es, hl) + byte) es:[hl + byte], ax 3 2 ? ((es, hl) + byte) ax ax, es:word[b] 4 2 5 ax ((es, b) + word) es:word[b], ax 4 2 ? ((es, b) + word) ax ax, es:word[c] 4 2 5 ax ((es, c) + word) es:word[c], ax 4 2 ? ((es, c) + word) ax ax, es:word[bc] 4 2 5 ax ((es, bc) + word) es:word[bc], ax 4 2 ? ((es, bc) + word) ax bc, es:!addr16 4 2 5 bc (es, addr16) de, es:!addr16 4 2 5 de (es, addr16) movw hl, es:!addr16 4 2 5 hl (es, addr16) xchw ax, rp note 3 1 1 ? ax rp ax 1 1 ? ax 0001h onew bc 1 1 ? bc 0001h ax 1 1 ? ax 0000h 16-bit data transfer clrw bc 1 1 ? bc 0000h a, #byte 2 1 ? a, cy a + byte saddr, #byte 3 2 ? (saddr), cy (saddr) + byte a, r note 4 2 1 ? a, cy a + r r, a 2 1 ? r, cy r + a a, saddr 2 1 ? a, cy a + (saddr) a, !addr16 3 1 4 a, cy a + (addr16) a, [hl] 1 1 4 a, cy a + (hl) a, [hl + byte] 2 1 4 a, cy a + (hl + byte) a, [hl + b] 2 1 4 a, cy a + (hl + b) a, [hl + c] 2 1 4 a, cy a + (hl + c) a, es:!addr16 4 2 5 a, cy a + (es, addr16) a, es:[hl] 2 2 5 a,cy a + (es, hl) a, es:[hl + byte] 3 2 5 a,cy a + ((es, hl) + byte) a, es:[hl + b] 3 2 5 a,cy a + ((es, hl) + b) 8-bit operation add a, es:[hl + c] 3 2 5 a,cy a + ((es, hl) + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except rp = ax 4. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 866 jun 20, 2011 table 30-5. operation list (7/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, #byte 2 1 ? a, cy a + byte + cy saddr, #byte 3 2 ? (saddr), cy (saddr) + byte + cy a, r note 3 2 1 ? a, cy a + r + cy r, a 2 1 ? r, cy r + a + cy a, saddr 2 1 ? a, cy a + (saddr) + cy a, !addr16 3 1 4 a, cy a + (addr16) + cy a, [hl] 1 1 4 a, cy a + (hl) + cy a, [hl + byte] 2 1 4 a, cy a + (hl + byte) + cy a, [hl + b] 2 1 4 a, cy a + (hl + b) + cy a, [hl + c] 2 1 4 a, cy a + (hl + c) + cy a, es:!addr16 4 2 5 a, cy a + (es, addr16) + cy a, es:[hl] 2 2 5 a, cy a + (es, hl) + cy a, es:[hl + byte] 3 2 5 a, cy a + ((es, hl) + byte) + cy a, es:[hl + b] 3 2 5 a, cy a + ((es, hl) + b) + cy addc a, es:[hl + c] 3 2 5 a, cy a + ((es, hl) + c) + cy a, #byte 2 1 ? a, cy a ? byte saddr, #byte 3 2 ? (saddr), cy (saddr) ? byte a, r note 3 2 1 ? a, cy a ? r r, a 2 1 ? r, cy r ? a a, saddr 2 1 ? a, cy a ? (saddr) a, !addr16 3 1 4 a, cy a ? (addr16) a, [hl] 1 1 4 a, cy a ? (hl) a, [hl + byte] 2 1 4 a, cy a ? (hl + byte) a, [hl + b] 2 1 4 a, cy a ? (hl + b) a, [hl + c] 2 1 4 a, cy a ? (hl + c) a, es:!addr16 4 2 5 a, cy a ? (es:addr16) a, es:[hl] 2 2 5 a, cy a ? (es:hl) a, es:[hl + byte] 3 2 5 a, cy a ? ((es:hl) + byte) a, es:[hl + b] 3 2 5 a, cy a ? ((es:hl) + b) 8-bit operation sub a, es:[hl + c] 3 2 5 a, cy a ? ((es:hl) + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 867 jun 20, 2011 table 30-5. operation list (8/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, #byte 2 1 ? a, cy a ? byte ? cy saddr, #byte 3 2 ? (saddr), cy (saddr) ? byte ? cy a, r note 3 2 1 ? a, cy a ? r ? cy r, a 2 1 ? r, cy r ? a ? cy a, saddr 2 1 ? a, cy a ? (saddr) ? cy a, !addr16 3 1 4 a, cy a ? (addr16) ? cy a, [hl] 1 1 4 a, cy a ? (hl) ? cy a, [hl + byte] 2 1 4 a, cy a ? (hl + byte) ? cy a, [hl + b] 2 1 4 a, cy a ? (hl + b) ? cy a, [hl + c] 2 1 4 a, cy a ? (hl + c) ? cy a, es:!addr16 4 2 5 a, cy a ? (es:addr16) ? cy a, es:[hl] 2 2 5 a, cy a ? (es:hl) ? cy a, es:[hl + byte] 3 2 5 a, cy a ? ((es:hl) + byte) ? cy a, es:[hl + b] 3 2 5 a, cy a ? ((es:hl) + b) ? cy subc a, es:[hl + c] 3 2 5 a, cy a ? ((es:hl) + c) ? cy a, #byte 2 1 ? a a byte saddr, #byte 3 2 ? (saddr) (saddr) byte a, r note 3 2 1 ? a a r r, a 2 1 ? r r a a, saddr 2 1 ? a a (saddr) a, !addr16 3 1 4 a a (addr16) a, [hl] 1 1 4 a a (hl) a, [hl + byte] 2 1 4 a a (hl + byte) a, [hl + b] 2 1 4 a a (hl + b) a, [hl + c] 2 1 4 a a (hl + c) a, es:!addr16 4 2 5 a a (es:addr16) a, es:[hl] 2 2 5 a a (es:hl) a, es:[hl + byte] 3 2 5 a a ((es:hl) + byte) a, es:[hl + b] 3 2 5 a a ((es:hl) + b) 8-bit operation and a, es:[hl + c] 3 2 5 a a ((es:hl) + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 868 jun 20, 2011 table 30-5. operation list (9/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, #byte 2 1 ? a a byte saddr, #byte 3 2 ? (saddr) (saddr) byte a, r note 3 2 1 ? a a r r, a 2 1 ? r r a a, saddr 2 1 ? a a (saddr) a, !addr16 3 1 4 a a (addr16) a, [hl] 1 1 4 a a (hl) a, [hl + byte] 2 1 4 a a (hl + byte) a, [hl + b] 2 1 4 a a (hl + b) a, [hl + c] 2 1 4 a a (hl + c) a, es:!addr16 4 2 5 a a (es:addr16) a, es:[hl] 2 2 5 a a (es:hl) a, es:[hl + byte] 3 2 5 a a ((es:hl) + byte) a, es:[hl + b] 3 2 5 a a ((es:hl) + b) or a, es:[hl + c] 3 2 5 a a ((es:hl) + c) a, #byte 2 1 ? a a byte saddr, #byte 3 2 ? (saddr) (saddr) byte a, r note 3 2 1 ? a a r r, a 2 1 ? r r a a, saddr 2 1 ? a a (saddr) a, !addr16 3 1 4 a a (addr16) a, [hl] 1 1 4 a a (hl) a, [hl + byte] 2 1 4 a a (hl + byte) a, [hl + b] 2 1 4 a a (hl + b) a, [hl + c] 2 1 4 a a (hl + c) a, es:!addr16 4 2 5 a a (es:addr16) a, es:[hl] 2 2 5 a a (es:hl) a, es:[hl + byte] 3 2 5 a a ((es:hl) + byte) a, es:[hl + b] 3 2 5 a a ((es:hl) + b) 8-bit operation xor a, es:[hl + c] 3 2 5 a a ((es:hl) + c) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 869 jun 20, 2011 table 30-5. operation list (10/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy a, #byte 2 1 ? a ? byte saddr, #byte 3 1 ? (saddr) ? byte a, r note 3 2 1 ? a ? r r, a 2 1 ? r ? a a, saddr 2 1 ? a ? (saddr) a, !addr16 3 1 4 a ? (addr16) a, [hl] 1 1 4 a ? (hl) a, [hl + byte] 2 1 4 a ? (hl + byte) a, [hl + b] 2 1 4 a ? (hl + b) a, [hl + c] 2 1 4 a ? (hl + c) !addr16, #byte 4 1 4 (addr16) ? byte a, es:!addr16 4 2 5 a ? (es:addr16) a, es:[hl] 2 2 5 a ? (es:hl) a, es:[hl + byte] 3 2 5 a ? ((es:hl) + byte) a, es:[hl + b] 3 2 5 a ? ((es:hl) + b) a, es:[hl + c] 3 2 5 a ? ((es:hl) + c) cmp es:!addr16, #byte 5 2 5 (es:addr16) ? byte a 1 1 ? a ? 00h x 1 1 ? x ? 00h b 1 1 ? b ? 00h c 1 1 ? c ? 00h saddr 2 1 ? (saddr) ? 00h !addr16 3 1 4 (addr16) ? 00h cmp0 es:!addr16 4 2 5 (es:addr16) ? 00h x, [hl + byte] 3 1 4 x ? (hl + byte) 8-bit operation cmps x, es:[hl + byte] 4 2 5 x ? ((es:hl) + byte) notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 870 jun 20, 2011 table 30-5. operation list (11/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy ax, #word 3 1 ? ax, cy ax + word ax, ax 1 1 ? ax, cy ax + ax ax, bc 1 1 ? ax, cy ax + bc ax, de 1 1 ? ax, cy ax + de ax, hl 1 1 ? ax, cy ax + hl ax, saddrp 2 1 ? ax, cy ax + (saddrp) ax, !addr16 3 1 4 ax, cy ax + (addr16) ax, [hl+byte] 3 1 4 ax, cy ax + (hl + byte) ax, es:!addr16 4 2 5 ax, cy ax + (es:addr16) addw ax, es: [hl+byte] 4 2 5 ax, cy ax + ((es:hl) + byte) ax, #word 3 1 ? ax, cy ax ? word ax, bc 1 1 ? ax, cy ax ? bc ax, de 1 1 ? ax, cy ax ? de ax, hl 1 1 ? ax, cy ax ? hl ax, saddrp 2 1 ? ax, cy ax ? (saddrp) ax, !addr16 3 1 4 ax, cy ax ? (addr16) ax, [hl+byte] 3 1 4 ax, cy ax ? (hl + byte) ax, es:!addr16 4 2 5 ax, cy ax ? (es:addr16) subw ax, es: [hl+byte] 4 2 5 ax, cy ax ? ((es:hl) + byte) ax, #word 3 1 ? ax ? word ax, bc 1 1 ? ax ? bc ax, de 1 1 ? ax ? de ax, hl 1 1 ? ax ? hl ax, saddrp 2 1 ? ax ? (saddrp) ax, !addr16 3 1 4 ax ? (addr16) ax, [hl+byte] 3 1 4 ax ? (hl + byte) ax, es:!addr16 4 2 5 ax ? (es:addr16) 16-bit operation cmpw ax, es: [hl+byte] 4 2 5 ax ? ((es:hl) + byte) multiply mulu x 1 1 ? ax a x notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 871 jun 20, 2011 table 30-5. operation list (12/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy r 1 1 ? r r + 1 saddr 2 2 ? (saddr) (saddr) + 1 !addr16 3 2 ? (addr16) (addr16) + 1 [hl+byte] 3 2 ? (hl+byte) (hl+byte) + 1 es:!addr16 4 3 ? (es, addr16) (es, addr16) + 1 inc es: [hl+byte] 4 3 ? ((es:hl) + byte) ((es:hl) + byte) + 1 r 1 1 ? r r ? 1 saddr 2 2 ? (saddr) (saddr) ? 1 !addr16 3 2 ? (addr16) (addr16) ? 1 [hl+byte] 3 2 ? (hl+byte) (hl+byte) ? 1 es:!addr16 4 3 ? (es, addr16) (es, addr16) ? 1 dec es: [hl+byte] 4 3 ? ((es:hl) + byte) ((es:hl) + byte) ? 1 rp 1 1 ? rp rp + 1 saddrp 2 2 ? (saddrp) (saddrp) + 1 !addr16 3 2 ? (addr16) (addr16) + 1 [hl+byte] 3 2 ? (hl+byte) (hl+byte) + 1 es:!addr16 4 3 ? (es, addr16) (es, addr16) + 1 incw es: [hl+byte] 4 3 ? ((es:hl) + byte) ((es:hl) + byte) + 1 rp 1 1 ? rp rp ? 1 saddrp 2 2 ? (saddrp) (saddrp) ? 1 !addr16 3 2 ? (addr16) (addr16) ? 1 [hl+byte] 3 2 ? (hl+byte) (hl+byte) ? 1 es:!addr16 4 3 ? (es, addr16) (es, addr16) ? 1 increment/ decrement decw es: [hl+byte] 4 3 ? ((es:hl) + byte) ((es:hl) + byte) ? 1 shr a, cnt 2 1 ? (cy a 0 , a m ? 1 a m , a 7 0) cnt shrw ax, cnt 2 1 ? (cy ax 0 , ax m ? 1 ax m , ax 15 0) cnt a, cnt 2 1 ? (cy a 7 , a m a m ? 1 , a 0 0) cnt b, cnt 2 1 ? (cy b 7 , b m b m ? 1 , b 0 0) cnt shl c, cnt 2 1 ? (cy c 7 , c m c m ? 1 , c 0 0) cnt ax, cnt 2 1 ? (cy ax 15 , ax m ax m ? 1 , ax 0 0) cnt shlw bc, cnt 2 1 ? (cy bc 15 , bc m bc m ? 1 , bc 0 0) cnt sar a, cnt 2 1 ? (cy a 0 , a m ? 1 a m , a 7 a 7 ) cnt shift sarw ax, cnt 2 1 ? (cy ax 0 , ax m ? 1 ax m , ax 15 ax 15 ) cnt notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. 3. cnt indicates the bit shift count.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 872 jun 20, 2011 table 30-5. operation list (13/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy ror a, 1 2 1 ? (cy, a 7 a 0 , a m ? 1 a m ) 1 rol a, 1 2 1 ? (cy, a 0 a 7 , a m + 1 a m ) 1 rorc a, 1 2 1 ? (cy a 0 , a 7 cy, a m ? 1 a m ) 1 rolc a, 1 2 1 ? (cy a 7 , a 0 cy, a m + 1 a m ) 1 ax,1 2 1 ? (cy ax 15 , ax 0 cy, ax m + 1 ax m ) 1 rotate rolwc bc,1 2 1 ? (cy bc 15 , bc 0 cy, bc m + 1 bc m ) 1 cy, saddr.bit 3 1 ? cy (saddr).bit cy, sfr.bit 3 1 ? cy sfr.bit cy, a.bit 2 1 ? cy a.bit cy, psw.bit 3 1 ? cy psw.bit cy,[hl].bit 2 1 4 cy (hl).bit saddr.bit, cy 3 2 ? (saddr).bit cy sfr.bit, cy 3 2 ? sfr.bit cy a.bit, cy 2 1 ? a.bit cy psw.bit, cy 3 4 ? psw.bit cy [hl].bit, cy 2 2 ? (hl).bit cy cy, es:[hl].bit 3 2 5 cy (es, hl).bit mov1 es:[hl].bit, cy 3 3 ? (es, hl).bit cy cy, saddr.bit 3 1 ? cy cy (saddr).bit cy, sfr.bit 3 1 ? cy cy sfr.bit cy, a.bit 2 1 ? cy cy a.bit cy, psw.bit 3 1 ? cy cy psw.bit cy,[hl].bit 2 1 4 cy cy (hl).bit and1 cy, es:[hl].bit 3 2 5 cy cy (es, hl).bit cy, saddr.bit 3 1 ? cy cy (saddr).bit cy, sfr.bit 3 1 ? cy cy sfr.bit cy, a.bit 2 1 ? cy cy a.bit cy, psw.bit 3 1 ? cy cy psw.bit cy, [hl].bit 2 1 4 cy cy (hl).bit bit manipulate or1 cy, es:[hl].bit 3 2 5 cy cy (es, hl).bit notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 873 jun 20, 2011 table 30-5. operation list (14/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy cy, saddr.bit 3 1 ? cy cy (saddr).bit cy, sfr.bit 3 1 ? cy cy sfr.bit cy, a.bit 2 1 ? cy cy a.bit cy, psw.bit 3 1 ? cy cy psw.bit cy, [hl].bit 2 1 4 cy cy (hl).bit xor1 cy, es:[hl].bit 3 2 5 cy cy (es, hl).bit saddr.bit 3 2 ? (saddr).bit 1 sfr.bit 3 2 ? sfr.bit 1 a.bit 2 1 ? a.bit 1 !addr16.bit 4 2 ? (addr16).bit 1 psw.bit 3 4 ? psw.bit 1 [hl].bit 2 2 ? (hl).bit 1 es:!addr16.bit 5 3 ? (es, addr16).bit 1 set1 es:[hl].bit 3 3 ? (es, hl).bit 1 saddr.bit 3 2 ? (saddr.bit) 0 sfr.bit 3 2 ? sfr.bit 0 a.bit 2 1 ? a.bit 0 !addr16.bit 4 2 ? (addr16).bit 0 psw.bit 3 4 ? psw.bit 0 [hl].bit 2 2 ? (hl).bit 0 es:!addr16.bit 5 3 ? (es, addr16).bit 0 clr1 es:[hl].bit 3 3 ? (es, hl).bit 0 set1 cy 2 1 ? cy 1 1 clr1 cy 2 1 ? cy 0 0 bit manipulate not1 cy 2 1 ? cy cy notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 874 jun 20, 2011 table 30-5. operation list (15/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy rp 2 3 ? (sp ? 2) (pc + 2) s , (sp ? 3) (pc + 2) h , (sp ? 4) (pc + 2) l , pc cs, rp, sp sp ? 4 $!addr20 3 3 ? (sp ? 2) (pc + 3) s , (sp ? 3) (pc + 3) h , (sp ? 4) (pc + 3) l , pc pc + 3 + jdisp16, sp sp ? 4 !addr16 3 3 ? (sp ? 2) (pc + 3) s , (sp ? 3) (pc + 3) h , (sp ? 4) (pc + 3) l , pc 0000, addr16, sp sp ? 4 call !!addr20 4 3 ? (sp ? 2) (pc + 4) s , (sp ? 3) (pc + 4) h , (sp ? 4) (pc + 4) l , pc addr20, sp sp ? 4 callt [addr5] 2 5 ? (sp ? 2) (pc + 2) s , (sp ? 3) (pc + 2) h , (sp ? 4) (pc + 2) l , pc s 0000, pc h (0000, addr5 + 1), pc l (0000, addr5), sp sp ? 4 brk ? 2 5 ? (sp ? 1) psw, (sp ? 2) (pc + 2) s , (sp ? 3) (pc + 2) h , (sp ? 4) (pc + 2) l , pc s 0000, pc h (0007fh), pc l (0007eh), sp sp ? 4, ie 0 ret ? 1 6 ? pc l (sp), pc h (sp + 1), pc s (sp + 2), sp sp + 4 reti ? 2 6 ? pc l (sp), pc h (sp + 1), pc s (sp + 2), psw (sp + 3), sp sp + 4 r r r call/ return retb ? 2 6 ? pc l (sp), pc h (sp + 1), pc s (sp + 2), psw (sp + 3), sp sp + 4 r r r notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 875 jun 20, 2011 table 30-5. operation list (16/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy psw 2 1 ? (sp ? 1) psw, (sp ? 2) 00h, sp sp ? 2 push rp 1 1 ? (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 2 3 ? psw (sp + 1), sp sp + 2 r r r pop rp 1 1 ? rp l (sp), rp h (sp + 1), sp sp + 2 sp, #word 4 1 ? sp word sp, ax 2 1 ? sp ax ax, sp 2 1 ? ax sp hl, sp 3 1 ? hl sp bc, sp 3 1 ? bc sp movw de, sp 3 1 ? de sp addw sp, #byte 2 1 ? sp sp + byte stack manipulate subw sp, #byte 2 1 ? sp sp ? byte ax 2 3 ? pc cs, ax $addr20 2 3 ? pc pc + 2 + jdisp8 $!addr20 3 3 ? pc pc + 3 + jdisp16 !addr16 3 3 ? pc 0000, addr16 unconditio nal branch br !!addr20 4 3 ? pc addr20 bc $addr20 2 2/4 note 3 ? pc pc + 2 + jdisp8 if cy = 1 bnc $addr20 2 2/4 note 3 ? pc pc + 2 + jdisp8 if cy = 0 bz $addr20 2 2/4 note 3 ? pc pc + 2 + jdisp8 if z = 1 bnz $addr20 2 2/4 note 3 ? pc pc + 2 + jdisp8 if z = 0 bh $addr20 3 2/4 note 3 ? pc pc+3+jdisp8 if (z cy)=0 bnh $addr20 3 2/4 note 3 ? pc pc+3+jdisp8 if (z cy)=1 saddr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if (saddr).bit = 1 sfr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr20 3 3/5 note 3 ? pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if psw.bit = 1 [hl].bit, $addr20 3 3/5 note 3 6/7 pc pc + 3 + jdisp8 if (hl).bit = 1 conditional branch bt es:[hl].bit, $addr20 4 4/6 note 3 7/8 pc pc + 4 + jdisp8 if (es, hl).bit = 1 notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. this indicates the number of clocks ?when condition is not met/when condition is met?. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area.
78k0r/lx3 chapter 30 instruction set r01uh0004ej0501 rev.5.01 876 jun 20, 2011 table 30-5. operation list (17/17) clocks flag instruction group mnemonic operands bytes note 1 note 2 operation z ac cy saddr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if (saddr).bit = 0 sfr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr20 3 3/5 note 3 ? pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if psw.bit = 0 [hl].bit, $addr20 3 3/5 note 3 6/7 pc pc + 3 + jdisp8 if (hl).bit = 0 bf es:[hl].bit, $addr20 4 4/6 note 3 7/8 pc pc + 4 + jdisp8 if (es, hl).bit = 0 saddr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if (saddr).bit = 1 then reset (saddr).bit sfr.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr20 3 3/5 note 3 ? pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr20 4 3/5 note 3 ? pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit [hl].bit, $addr20 3 3/5 note 3 ? pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit condition al branch btclr es:[hl].bit, $addr20 4 4/6 note 3 ? pc pc + 4 + jdisp8 if (es, hl).bit = 1 then reset (es, hl).bit skc ? 2 1 ? next instruction skip if cy = 1 sknc ? 2 1 ? next instruction skip if cy = 0 skz ? 2 1 ? next instruction skip if z = 1 sknz ? 2 1 ? next instruction skip if z = 0 skh ? 2 1 ? next instruction skip if (z cy) = 0 conditional skip sknh ? 2 1 ? next instruction skip if (z cy) = 1 sel rbn 2 1 ? rbs[1:0] n nop ? 1 1 ? no operation ei ? 3 4 ? ie 1(enable interrupt) di ? 3 4 ? ie 0(disable interrupt) halt ? 2 3 ? set halt mode cpu control stop ? 2 3 ? set stop mode notes 1. when the internal ram area or sfr area is a ccessed, or for an instruction with no data access. 2. when the program memory area is accessed. 3. this indicates the number of clocks ?when condition is not met/when condition is met?. remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the system clock control register (ckc). 2. this number of clocks is for when the program is in the internal rom (flash memory) area. 3. n indicates the number of register banks (n = 0 to 3)
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 877 jun 20, 2011 chapter 31 electrical specifications cautions 1. the 78k0r/lx3 microcontrollers have an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug functi on in products designated for mass production, because the guaranteed number of re writable times of the flash memory may be exceeded when this function is used, and produc t reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 2. the pins mounted depend on the product. refer to 1.3 pin confi guration (top view) and chapter 2 pin functions. absolute maximum ratings (t a = 25 c) (1/3) parameter symbols conditions ratings unit v dd ? 0.5 to +6.5 v ev dd ? 0.5 to +6.5 v v ss ? 0.5 to +0.3 v ev ss ? 0.5 to +0.3 v av dd0 , av dd ? 0.5 to v dd +0.3 note 1 v av dd1, ev dd1 ? 0.5 to v dd +0.3 note 1 v supply voltage av ss ? 0.5 to +0.3 v regc pin input voltage v iregc regc ? 0.3 to +3.6 and ? 0.3 to v dd +0.3 note 2 v v i1 p00 to p02, p10 to p17, p30 to p34, p40, p41, p50 to p57, p70 to p77, p80 to p87, p90 to p97, p100 to p102, p120 to p124, p140 to p147, exclk, reset, flmd0 ? 0.3 to ev dd +0.3 and ? 0.3 to v dd +0.3 note 1 v v i2 p60, p61 (n-ch open-drain) ? 0.3 to +6.5 v pd78f150xa ? 0.3 to av dd0 +0.3 and ? 0.3 to v dd +0.3 note 1 v i3 p20 to p27, p150 to p152, p157 pd78f151xa ? 0.3 to av dd +0.3 and ? 0.3 to v dd +0.3 note 1 v pd78f150xa ? 0.3 to av dd1 +0.3 and ? 0.3 to v dd +0.3 note 1 input voltage v i4 p110, p111 pd78f151xa ? 0.3 to ev dd1 +0.3 and ? 0.3 to v dd +0.3 note 1 v notes 1. must be 6.5 v or lower. 2. connect the regc pin to vss via a capacitor (0.47 to 1 f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. caution product quality may suffer if the absolute maximum rating is exceeded even mo mentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage , and therefore the product must be used under conditions that ensure that the absolute maxi mum ratings are not exceeded. remark unless specified otherwise, the characte ristics of alternate-function pins ar e the same as those of port pins.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 878 jun 20, 2011 absolute maximum ratings (t a = 25 c) (2/3) parameter symbols conditions ratings unit v o1 p00 to p02, p10 to p17, p30 to p34, p40, p41, p50 to p57, p60, p61, p70 to p77, p80 to p87, p90 to p97, p100 to p102, p120, p130, p140 to p147 ? 0.3 to ev dd +0.3 v v o2 p20 to p27, p150 to p152, p157 ? 0.3 to av dd0 +0.3 v v o3 p110, p111 ? 0.3 to av dd1 +0.3 v external resistance division method, capacitor split method ? 0.3 to v dd +0.3 note v output voltage v o4 seg0 to seg53, com0 to com7 internal voltage boosting method ? 0.3 to v lc0 +0.3 note v ani0 to ani10, ani15, amp0+, amp1+, amp2+, amp0-, amp1-, amp2- ( pd78f150xa) ? 0.3 to av dd0 +0.3 and ? 0.3 to v dd +0.3 note v analog input voltage v ai ani0 to ani10, ani15 ( pd78f151xa) ? 0.3 to av dd +0.3 and ? 0.3 to v dd +0.3 note v v ao1 ano0, ano1 ? 0.3 to av dd1 +0.3 note v analog output voltage v ao2 amp0o, amp1o, amp2o ? 0.3 to av dd0 +0.3 note v av ref pd78f151xa ? 0.3 to av dd +0.3 note v av refp pd78f150xa ? 0.3 to av dd0 +0.3 note v analog input reference voltage av refm pd78f150xa ? 0.3 to av dd0 +0.3 note and av refm av refp v p00 to p02, p10-p17, p30 to p34, p40, p41, p70 to p77, p80 to p87, p120, p130 ? 10 ma per pin p50 to p57, p90 to p97, p100 to p102, p140 to p147 ? 10 ma p00 to p02, p10-p17, p30 to p34, p40, p41, p70 to p77, p80 to p87, p120, p130 ? 25 ma i oh1 total of all pins ? 50 ma p50 to p57, p90 to p97, p100 to p102, p140 to p147 ? 25 ma per pin ? 0.5 ma i oh2 total of all pins p20 to p27, p150 to p152, p157, p110, p111 ? 2 ma per pin ? 1 ma output current, high i oh3 total of all pins amp0o, amp1o, amp2o ? 3 ma note must be 6.5 v or lower. cautions 1. product quality may suffe r if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum rati ngs are rated values at wh ich the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. 2. the value of the current that can be run per pi n must satisfy the value of the current per pin and the total value of the currents of all pins. remark unless specified otherwise, the characte ristics of alternate-function pins ar e the same as those of port pins.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 879 jun 20, 2011 absolute maximum ratings (t a = 25 c) (3/3) parameter symbols conditions ratings unit p00 to p02, p10-p17, p30 to p34, p40, p41, p70 to p77, p80 to p87, p120, p130 30 ma p60, p61 30 ma per pin p50 to p57, p90 to p97, p100 to p102, p140 to p147 10 ma p00 to p02, p10-p17, p30 to p34, p40, p41, p70 to p77, p80 to p87, p120, p130 80 ma p60, p61 60 ma i ol1 total of all pins 165 ma p50 to p57, p90 to p97, p100 to p102, p140 to p147 25 ma per pin 1 ma i ol2 total of all pins p20 to p27, p150 to p152, p157, p110, p111 5 ma per pin 1 ma output current, low i ol3 total of all pins amp0o, amp1o, amp2o 3 ma in normal operation mode operating ambient temperature t a in flash memory programming mode ? 40 to +85 c storage temperature t stg ? 65 to +150 c cautions 1. product quality may suffe r if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maxi mum ratings are not exceeded. 2. the value of the current that can be run per pin must satisfy the value of the current per pin and the total value of the currents of all pins. remark unless specified otherwise, the characte ristics of alternate-function pins ar e the same as those of port pins.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 880 jun 20, 2011 x1 oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 2.7 v v dd 5.5 v 2.0 20.0 ceramic resonator, crystal resonator c1 x2 x1 c2 v ss x1 clock oscillation frequency (f x ) note 1.8 v v dd < 2.7 v 2.0 5.0 mhz note indicates only oscillator characteri stics. refer to ac characterist ics for instruction execution time. cautions 1. when using the x1 oscilla tor, wire as follows in the area enclo sed by the broken lines in the above figures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. since the cpu is started by the internal high-speed oscillation cl ock after a reset release, check the x1 clock oscillation stabilization time using the oscillation stabilization time counter status register (ostc) by the user. dete rmine the oscillation stabilization time of the ostc register and oscillation stabilization ti me select register (osts) after sufficiently evaluati ng the oscillation stabilization time with the resonator to be used. remark for the resonator selection and oscillator constant, cu stomers are requested to eit her evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. internal oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) oscillators parameters conditions min. typ. max. unit f ih1m low-power consumption mode 0.87 1 1.13 mhz 2.7 v v dd 5.5 v 7.856 8 8.144 mhz 1.8 v v dd < 2.7 v, t a = ? 20 to +70 c 7.848 8 8.152 mhz f ih8m 1.8 v v dd < 2.7 v 7.84 8 8.16 mhz internal high- speed oscillation clock frequency note f ih20m 2.7 v v dd 5.5 v 19.52 20 20.48 mhz 2.7 v v dd 5.5 v 27 30 33 khz normal power mode 1.8 v v dd < 2.7 v 25.5 30 34.5 khz internal low-speed oscillation clock frequency f il low-power consumption mode 25.5 30 34.5 khz note indicates only oscillator characteri stics. refer to ac characterist ics for instruction execution time.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 881 jun 20, 2011 xt1 oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = av ss = 0 v) resonator recommended circuit items conditions min. typ. max. unit crystal resonator xt1 xt2 c4 c3 rd v ss xt1 clock oscillation frequency (f xt ) note 32 32.768 35 khz note indicates only oscillator characteri stics. refer to ac characterist ics for instruction execution time. cautions 1. when using the xt1 osc illator, wire as follows in the area en closed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. the xt1 oscillator is designed as a low-amplit ude circuit for reducing pow er consumption, and is more prone to malfunction due to noise than the x1 oscillator. particular care is therefore required with the wiring method when the xt1 clock is used. remark for the resonator selection and oscillator constant, cu stomers are requested to eit her evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 882 jun 20, 2011 recommended oscillator circuit constants (1) x1 oscillation: ceramic res onator (amph = 0, rmc = 00h, t a = ? 40 to +85 c) recommended circuit constants oscillation voltage range manufacturer part number smd/ lead frequency (mhz) c1 (pf) c2 (pf) rd (k ) min. (v) max. (v) cstcc2m00g56-r0 smd 2.0 internal (47) internal (47) 0 cstcr4m00g55-r0 smd internal (39) internal (39) 0 cstls4m00g56-b0 lead 4.0 internal (47) internal (47) 0 cstcr4m19g55-r0 smd internal (39) internal (39) 0 cstls4m19g56-b0 lead 4.194 internal (47) internal (47) 0 cstcr4m91g55-r0 smd internal (39) internal (39) 0 cstls4m91g53-b0 lead 4.915 internal (15) internal (15) 0 cstcr5m00g55-r0 smd internal (39) internal (39) 0 cstls5m00g53-b0 lead 5.0 internal (15) internal (15) 0 cstcr6m00g53-r0 smd internal (15) internal (15) 0 cstls6m00g53-b0 lead 6.0 internal (15) internal (15) 0 cstce8m00g55-r0 smd internal (33) internal (33) 0 cstls8m00g53-b0 lead 8.0 internal (15) internal (15) 0 cstce8m38g55-r0 smd internal (33) internal (33) 0 cstls8m38g53-b0 lead 8.388 internal (15) internal (15) 0 cstce10m0g52-r0 smd internal (10) internal (10) 0 murata manufacturing co., ltd.. cstls10m0g53-b0 lead 10.0 internal (15) internal (15) 0 1.8 5.5 caution the oscillator constants s hown above are reference values base d on evaluation in a specific environment by the resonator manufacturer. if it is necessary to optimize the oscillator characteristics in the actual app lication, apply to the resonato r manufacturer for evaluation on the implementation circuit. the oscillation voltage a nd oscillation frequency only indicate the oscillator characteristic. use the 78k0r/ lx3 so that the internal opera tion conditions are within the specifications of the dc and ac characteristics.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 883 jun 20, 2011 (2) x1 oscillation: ceramic res onator (amph = 1, rmc = 00h, t a = ? 40 to +85 c) recommended circuit constants oscillation voltage range manufacturer part number smd/ lead frequency (mhz) c1 (pf) c2 (pf) rd (k ) min. (v) max. (v) cstce12m0g55-r0 smd 12.0 internal (33) internal (33) 0 cstce16m0v53-r0 smd internal (15) internal (15) 0 cstls16m0x51-b0 lead 16.0 internal (5) internal (5) 0 cstce20m0v53-r0 smd internal (15) internal (15) 0 murata manufacturing co., ltd.. cstls20m0x51-b0 lead 20.0 internal (5) internal (5) 0 1.8 5.5 (3) x1 oscillation: ceramic res onator (amph = 0, rmc = 5ah, t a = ? 40 to +85 c) recommended circuit constants oscillation voltage range manufacturer part number smd/ lead frequency (mhz) c1 (pf) c2 (pf) rd (k ) min. (v) max. (v) cstcc2m00g56-r0 smd 2.0 internal (47) internal (47) 0 cstcr4m00g55-r0 smd internal (39) internal (39) 0 cstls4m00g53-b0 lead 4.0 internal (15) internal (15) 0 cstcr4m19g55-r0 smd internal (39) internal (39) 0 cstls4m19g53-b0 lead 4.194 internal (15) internal (15) 0 cstcr4m91g53-r0 smd internal (15) internal (15) 0 cstls4m91g53-b0 lead 4.195 internal (15) internal (15) 0 cstcr5m00g53-r0 smd internal (15) internal (15) 0 murata manufacturing co., ltd.. cstls5m00g53-b0 lead 5.0 internal (15) internal (15) 0 1.8 5.5 dcrhtc(p)2.00ll 2.0 internal (30) internal (30) ? dcrhtc(p)4.00ll lead 4.0 internal (30) internal (30) ? decrhtc4.00 smd 4.0 internal (15) internal (15) ? toko, inc. dcrhtc(p)5.00ll lead 5.0 internal (30) internal (30) ? 1.8 5.5 caution the oscillator constants s hown above are reference values base d on evaluation in a specific environment by the resonator manufacturer. if it is necessary to optimize the oscillator characteristics in the actual app lication, apply to the resonato r manufacturer for evaluation on the implementation circuit. the oscillation voltage a nd oscillation frequency only indicate the oscillator characteristic. use the 78k0r/ lx3 so that the internal opera tion conditions are within the specifications of the dc and ac characteristics.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 884 jun 20, 2011 (4) xt1 oscillation: crystal resonator (t a = ? 40 to +85 c) oscillation voltage range recommended circuit constants manufacturer part number smd/ lead frequency (mhz) load capacitance cl (pf) xt1 oscllator oscillation mode note 1 c3 (pf) c4 (pf) rd (k ) min. (v) max. (v) ssp-t7-f 7.0 normal oscillation 10 10 0 6.0 low power consumption oscillation 9 8 0 ssp-t7-fl smd 3.7 ultra-low power consumption oscillation 4 3 0 vt-200-f 12.5 normal oscillation 20 20 0 6.0 low power consumption oscillation 9 8 0 seiko instruments inc. note 2 vt-200-fl lead 32.768 3.7 ultra-low power consumption oscillation 4 3 0 1.8 5.5 notes 1. set the xt1 oscillation mode by using bits amphs1 and amphs0 of the clock operation mode control register (cmc). 2. contact seiko instruments inc. (http://www.s ii-crystal.com) when using this resonator.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 885 jun 20, 2011 dc characteristics (1/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av dd0 v dd , 1.8 v av dd1 v dd , 1.8 v av dd v dd , 1.8 v ev dd1 = v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v ? 3.0 ma 2.7 v v dd < 4.0 v ? 1.0 ma per pin for p00 to p02, p10 to p17, p30 to p34, p40, p41, p70 to p77, p80 to p87, p120, p130 1.8 v v dd < 2.7 v ? 1.0 ma 4.0 v v dd 5.5 v ? 1.6 ma 2.7 v v dd < 4.0 v ? 0.45 ma per pin for p50 to p57, p90 to p97, p100 to p102, p140 to p147 1.8 v v dd < 2.7 v ? 0.45 ma 4.0 v v dd 5.5 v ? 20.0 ma 2.7 v v dd < 4.0 v ? 10.0 ma total of p00 to p02, p10 to p17, p30 to p34, p40, p41, p70 to p77, p80 to p87, p120, p130 (when duty = 70% note 2 ) 1.8 v v dd < 2.7 v ? 5.0 ma 4.0 v v dd 5.5 v ? 12.8 ma 2.7 v v dd < 4.0 v ? 3.6 ma total of p50 to p57, p90 to p97, p100 to p102, p140 to p147 (when duty = 70% note 2 ) 1.8 v v dd < 2.7 v ? 3.6 ma 4.0 v v dd 5.5 v ? 32.8 ma 2.7 v v dd < 4.0 v ? 13.6 ma i oh1 total of all pins (when duty = 60% note 2 ) 1.8 v v dd < 2.7 v ? 8.6 ma per pin for p20 to p27, p150 to p152, p157 ? 0.1 ma output current, high note 1 i oh2 per pin for p110, p111 ? 0.1 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from v dd pin to an output pin. 2. specification under conditions where the duty factor is 60% or 70%. the output current value that has changed the duty ratio can be calcul ated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) where n = 50% and i oh = ? 20.0 ma total output current of pins = ( ? 20.0 0.7)/(50 0.01) = ? 28.0 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. caution p10 to p15, p75, p77, p80 and p82 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characte ristics of alternate-function pins ar e the same as those of port pins.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 886 jun 20, 2011 dc characteristics (2/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av dd0 v dd , 1.8 v av dd1 v dd , 1.8 v av dd v dd , 1.8 v ev dd1 = v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 8.5 ma 2.7 v v dd < 4.0 v 1.0 ma per pin for p00 to p02, p12, p13, p16, p17, p30 to p34, p40, p41, p70 to p77, p80 to p87, p120, p130 1.8 v v dd < 2.7 v 0.5 ma 4.0 v v dd 5.5 v 8.5 ma 2.7 v v dd < 4.0 v 1.5 ma per pin for p10, p11, p14, p15 1.8 v v dd < 2.7 v 0.6 ma 4.0 v v dd 5.5 v 15.0 ma 2.7 v v dd < 4.0 v 3.0 ma per pin for p60, p61 1.8 v v dd < 2.7 v 2.0 ma 4.0 v v dd 5.5 v 1.8 ma 2.7 v v dd < 4.0 v 0.8 ma per pin for p50 to p57, p90 to p97, p100 to p102, p140 to p147 1.8 v v dd < 2.7 v 0.35 ma 4.0 v v dd 5.5 v 20.0 ma 2.7 v v dd < 4.0 v 15.0 ma total of p00 to p02, p10 to p17, p30 to p34, p40, p41, p70 to p77, p80 to p87, p120, p130 (when duty = 70% note 2 ) 1.8 v v dd < 2.7 v 9.0 ma 4.0 v v dd 5.5 v 30.0 ma 2.7 v v dd < 4.0 v 6.0 ma total of p60, p61 (when duty = 70% note 2 ) 1.8 v v dd < 2.7 v 4.0 ma 4.0 v v dd 5.5 v 14.4 ma 2.7 v v dd < 4.0 v 6.4 ma total of p50 to p57, p90 to p97, p100 to p102, p140 to p147 (when duty = 70% note 2 ) 1.8 v v dd < 2.7 v 2.8 ma 4.0 v v dd 5.5 v 64.4 ma 2.7 v v dd < 4.0 v 27.4 ma i ol1 total of all pins (when duty = 70% note 2 ) 1.8 v v dd < 2.7 v 15.8 ma per pin for p20 to p27, p150 to p152, p157 0.4 ma output current, low note 1 i ol2 per pin for p110, p111 0.4 ma notes 1 . value of current at which the devic e operation is guaranteed even if the current flow s from an output pin to v ss and av ss pin. 2. specification under conditions where the duty factor is 60% or 70%. the output current value that has changed the duty ratio can be calcul ated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) where n = 50% and i ol = 20.0 ma total output current of pins = (20.0 0.7)/(50 0.01) = 28.0 ma however, the current that is allowed to flow into one pin does not vary depending on the duty factor. a current higher than the absolute maximum rating must not flow into one pin. remark unless specified otherwise, the characte ristics of alternate-function pins ar e the same as those of port pins.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 887 jun 20, 2011 dc characteristics (3/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av dd0 v dd , 1.8 v av dd1 v dd , 1.8 v av dd v dd , 1.8 v ev dd1 = v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit v ih1 p00 to p02, p12, p13, p17, p41, p51, p54 to p57, p82, p83, p90 to p97, p100 to p102, p123, p124, p140 to p147 0.7v dd v dd v v ih2 p10, p11, p14 to p16, p30 to p34, p40, p50, p52, p53, p70 to p77, p80, p81, p84 to p87, p120 to p122, reset normal input buffer 0.8v dd v dd v ttl input buffer 4.0 v v dd 5.5 v 2.2 v dd v ttl input buffer 2.7 v v dd < 4.0 v 2.0 v dd v v ih3 p10, p11, p14, p15, p75, p76 ttl input buffer 1.8 v v dd < 2.7 v 1.6 v dd v pd78f150xa 0.7av dd0 av dd0 v v ih4 p20 to p27, p150 to p152, p157 pd78f151xa 0.7av dd av dd v pd78f150xa 0.7av dd1 av dd1 v v ih5 p110, p111 pd78f151xa 0.7ev dd1 ev dd1 v v ih6 p60, p61 0.7v dd 6.0 v input voltage, high v ih7 flmd0 0.9v dd note v dd v note must be 0.9v dd or higher when used in the flash memory programming mode. caution the maximum value of v ih of pins p10 to p15, p75, p77, p80 and p82 is v dd , even in the n-ch open- drain mode. remark unless specified otherwise, the characte ristics of alternate-function pins ar e the same as those of port pins.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 888 jun 20, 2011 dc characteristics (4/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av dd0 v dd , 1.8 v av dd1 v dd , 1.8 v av dd v dd , 1.8 v ev dd1 = v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit v il1 p00 to p02, p12, p13, p17, p41, p51, p54 to p57, p82, p83, p90 to p97, p100 to p102, p123, p124, p140 to p147 0 0.3v dd v v il2 p10, p11, p14 to p16, p30 to p34, p40, p50, p52, p53, p70 to p77, p80, p81, p84 to p87, p120 to p122, reset normal input buffer 0 0.2v dd v ttl input buffer 4.0 v v dd 5.5 v 0 0.8 v ttl input buffer 2.7 v v dd < 4.0 v 0 0.5 v v il3 p10, p11, p14, p15, p75, p76 ttl input buffer 1.8 v v dd < 2.7 v 0 0.2 v pd78f150xa 0 0.3av dd0 v v il4 p20 to p27, p150 to p152, p157 pd78f151xa 0 0.3av dd v pd78f150xa 0 0.3av dd1 v v il5 p110, p111 pd78f151xa 0 0.3ev dd1 v v il6 p60, p61 0 0.3v dd v input voltage, low v il7 flmd0 0 0.1v dd note v note when disabling writing of the flash memory, connect the flmd0 pin directly to v ss , and maintain a voltage less than 0.1v dd . remark unless specified otherwise, the characte ristics of alternate-function pins ar e the same as those of port pins.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 889 jun 20, 2011 dc characteristics (5/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av dd0 v dd , 1.8 v av dd1 v dd , 1.8 v av dd v dd , 1.8 v ev dd1 = v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, i oh1 = ? 3.0 ma v dd ? 0.7 v p00 to p02, p10 to p17, p30 to p34, p40, p41, p70 to p77, p80 to p87, p120, p130 1.8 v v dd 5.5 v, i oh1 = ? 1.0 ma v dd ? 0.5 v 4.0 v v dd 5.5 v, i oh1 = ? 1.6 ma v dd ? 0.7 v v oh1 p50 to p57, p90 to p97, p100 to p102, p140 to p147 1.8 v v dd 5.5 v, i oh1 = ? 0.45 ma v dd ? 0.5 v p20 to p27, p150 to p152, p157 ( pd78f150xa) i oh2 = ? 0.1 ma av dd0 ? 0.5 v p20 to p27, p150 to p152, p157 ( pd78f151xa) i oh2 = ? 0.1 ma av dd ? 0.5 v p110, p111 ( pd78f150xa) i oh2 = ? 0.1 ma av dd1 ? 0.5 v output voltage, high v oh2 p110, p111 ( pd78f151xa) i oh2 = ? 0.1 ma ev dd1 ? 0.5 v caution p10 to p15, p75, p77, p80 and p82 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characte ristics of alternate-function pins ar e the same as those of port pins.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 890 jun 20, 2011 dc characteristics (6/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av dd0 v dd , 1.8 v av dd1 v dd , 1.8 v av dd v dd , 1.8 v ev dd1 = v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v v dd 5.5 v, i ol1 = 1.0 ma 0.5 v p00 to p02, p12, p13, p16, p17, p30 to p34, p40, p41, p70 to p77, p80 to p87, p120, p130 1.8 v v dd 5.5 v, i ol1 = 0.5 ma 0.4 v 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v v dd 5.5 v, i ol1 = 1.5 ma 0.5 v p10, p11, p14, p15 1.8 v v dd 5.5 v, i ol1 = 0.6 ma 0.4 v 4.0 v v dd 5.5 v, i ol1 = 1.8 ma 0.7 v 2.7 v v dd 5.5 v, i ol1 = 0.8 ma 0.5 v v ol1 p50 to p57, p90 to p97, p100 to p102, p140 to p147 1.8 v v dd 5.5 v, i ol1 = 0.35 ma 0.4 v p20 to p27, p150 to p152, p157 ( pd78f150xa) av dd0 5.5 v, i ol2 = 0.4 ma 0.4 v p20 to p27, p150 to p152, p157 ( pd78f151xa) av dd 5.5 v, i ol2 = 0.4 ma 0.4 v p110, p111 ( pd78f150xa) av dd1 5.5 v, i ol2 = 0.4 ma 0.4 v v ol2 p110, p111 ( pd78f151xa) ev dd1 5.5 v, i ol2 = 0.4 ma 0.4 v 4.0 v v dd 5.5 v, i ol1 = 15.0 ma 2.0 v 4.0 v v dd 5.5 v, i ol1 = 5.0 ma 0.4 v 2.7 v v dd 5.5 v, i ol1 = 3.0 ma 0.4 v output voltage, low v ol3 p60, p61 1.8 v v dd 5.5 v, i ol1 = 2.0 ma 0.4 v caution p10 to p15, p75, p77, p80 and p82 do not output high level in n-ch open-drain mode. remark unless specified otherwise, the characte ristics of alternate-function pins ar e the same as those of port pins.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 891 jun 20, 2011 dc characteristics (7/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av dd0 v dd , 1.8 v av dd1 v dd , 1.8 v av dd v dd , 1.8 v ev dd1 = v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit i lih1 p00 to p02, p10 to p17, p30 to p34, p40, p41, p50 to p57, p60, p61, p70 to p77, p80 to p87, p90 to p97, p100 to p102, p120, p140 to p147, flmd0, reset v i = v dd 1 a p20 to p27, p150 to p152, p157 ( pd78f150xa) v i = av dd0 1 a p20 to p27, p150 to p152, p157 ( pd78f151xa) v i = av dd 1 a p110, p111 ( pd78f150xa) v i = av dd1 1 a i lih2 p110, p111 ( pd78f151xa) v i = ev dd1 1 a in input port 1 a input leakage current, high i lih3 p121 to p124 (x1, x2, xt1, xt2) v i = v dd in resonator connection 10 a i lil1 p00 to p02, p10 to p17, p30 to p34, p40, p41, p50 to p57, p60, p61, p70 to p77, p80 to p87, p90 to p97, p100 to p102, p120, p140 to p147, flmd0, reset v i = v ss ? 1 a p20 to p27, p150 to p152, p157 v i = v ss ? 1 a i lil2 p110, p111 v i = v ss ? 1 a in input port ? 1 a input leakage current, low i lil3 p121 to p124 (x1, x2, xt1, xt2) v i = v ss in resonator connection ? 10 a on-chip pll-up resistance r u p00 to p02, p10 to p17, p30 to p34, p40, p41, p50 to p57, p70 to p77, p80 to p87, p90 to p97, p100 to p102, p120, p140 to p147 v i = v ss , in input port 10 20 100 k flmd0 pin external pull- down resistance note r flmd0 when enabling the self-programming mode setting with software 100 k note it is recommended to leave the flmd0 pin open. if the pin is required to be pulled down externally, set r flmd0 to 100 k or more. 78k0r/lx3 microcontrollers flmd0 pin r flmd0 remark unless specified otherwise, the characte ristics of alternate-function pins ar e the same as those of port pins.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 892 jun 20, 2011 dc characteristics (8/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av dd0 v dd , 1.8 v av dd1 v dd , 1.8 v av dd v dd , 1.8 v ev dd1 = v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit square wave input 5.5 7.7 ma f mx = 20 mhz, v dd = 5.0 v note 2 resonator connection 5.8 8.0 ma square wave input 5.5 7.7 ma f mx = 20 mhz, v dd = 3.0 v note 2 resonator connection 5.8 8.0 ma square wave input 3.2 4.6 ma f mx = 10 mhz, v dd = 5.0 v notes 2, 3 resonator connection 3.3 4.7 ma square wave input 3.2 4.6 ma f mx = 10 mhz, v dd = 3.0 v notes 2, 3 resonator connection 3.3 4.7 ma square wave input 1.8 2.7 ma f mx = 5 mhz, v dd = 3.0 v notes 2, 3 resonator connection 1.9 2.8 ma square wave input 1.3 2.2 ma f mx = 5 mhz, v dd = 2.0 v notes 2, 3 resonator connection 1.3 2.2 ma v dd = 5.0 v 5.7 8.0 ma f ih = 20 mhz note 4 v dd = 3.0 v 5.7 8.0 ma v dd = 5.0 v 2.6 3.7 ma f ih = 8 mhz note 4 v dd = 3.0 v 2.6 3.7 ma f ih = 1 mhz , rmc = 5ah, osmc = 02h note 4 v dd = 3.0 v 190 354 a v dd = 5.0 v 3.9 8.4 a v dd = 3.0 v 3.9 8.4 a t a = ? 40 to +50 c v dd = 2.0 v 3.9 8.4 a v dd = 5.0 v 3.9 11.3 a v dd = 3.0 v 3.9 11.3 a t a = ? 40 to +70 c v dd = 2.0 v 3.9 11.3 a v dd = 5.0 v 3.9 14.6 a v dd = 3.0 v 3.9 14.6 a supply current i dd1 note 1 operating mode f sub = 32.768 khz, fsel = 0, sdiv = 1, amphs1 = 1 note 5 t a = ? 40 to +85 c v dd = 2.0 v 3.9 14.6 a notes 1. total current flowing into v dd , ev dd , av dd0 , av dd1 , av dd , ev dd1 , and v lc0 to v lc3 , including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss , and excluding the current flowing into the real- time counter, watchdog timer, lvi ci rcuit, a/d converter, d/a converter note 6 , operational amplifier note 6 , voltage reference note 6 , lcd controller/driver, i/o port, and on-chip pull-up/pull-down resistors. the maximum values include the peripheral operation current. 2. when internal high-speed oscillator and subsystem clock are stopped. 3. when amph (bit 0 of clock operation mode control regist er (cmc)) = 0 and flpc, fsel (bits 1, 0 of operation speed mode control register (osmc)) = 0, 0. 4. when high-speed system clock and subsystem clock are stopped. 5. when internal high-speed oscillation, and high-speed system clock are stopped. when watchdog timer is stopped. 6. dedicated to pd78f150xa remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : internal high-speed oscillation clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency)
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 893 jun 20, 2011 dc characteristics (9/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av dd0 v dd , 1.8 v av dd1 v dd , 1.8 v av dd v dd , 1.8 v ev dd1 = v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit square wave input 1.1 3.3 ma f mx = 20 mhz, v dd = 5.0 v note 2 resonator connection 1.4 3.6 ma square wave input 1.1 3.3 ma f mx = 20 mhz, v dd = 3.0 v note 2 resonator connection 1.4 3.6 ma square wave input 0.55 2.1 ma f mx = 10 mhz, v dd = 5.0 v notes 2, 3 resonator connection 0.65 2.2 ma square wave input 0.55 2.1 ma f mx = 10 mhz, v dd = 3.0 v notes 2, 3 resonator connection 0.65 2.2 ma square wave input 0.4 1.8 ma f mx = 5 mhz, v dd = 3.0 v notes 2, 3 resonator connection 0.45 1.8 ma square wave input 0.26 1.3 ma f mx = 5 mhz, v dd = 2.0 v notes 2, 3 resonator connection 0.31 1.4 ma v dd = 5.0 v 1.3 3.6 ma f ih = 20 mhz note 4 v dd = 3.0 v 1.3 3.6 ma v dd = 5.0 v 0.45 1.8 ma f ih = 8 mhz note 4 v dd = 3.0 v 0.45 1.8 ma f ih = 1 mhz , rmc = 5ah, osmc = 02h note 4 v dd = 3.0 v 45 153 a v dd = 5.0 v 0.9 3.6 a v dd = 3.0 v 0.9 3.6 a t a = ? 40 to +50 c v dd = 2.0 v 0.9 3.6 a v dd = 5.0 v 0.9 6.0 a v dd = 3.0 v 0.9 6.0 a t a = ? 40 to +70 c v dd = 2.0 v 0.9 6.0 a v dd = 5.0 v 0.9 8.8 a v dd = 3.0 v 0.9 8.8 a supply current i dd2 note 1 halt mode f sub = 32.768 khz, rtclpc = 1, fsel = 0, sdiv = 1, amphs1 = 1 note 5 t a = ? 40 to +85 c v dd = 2.0 v 0.9 8.8 a notes 1. total current flowing into v dd , ev dd , av dd0 , av dd1 , av dd , ev dd1 , and v lc0 to v lc3 , including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss , and excluding the current flowing into the real-time counter, watchdog timer, lvi circuit, a/d converter, d/a converter note 6 , operational amplifier note 6 , voltage reference note 6 , lcd controller/driver, i/o port, and on-chip pull- up/pull-down resistors. the maximum values include the peripheral operation current. during halt instruction execution by flash memory. 2. when internal high-speed oscillator and subsystem clock are stopped. 3. when amph (bit 0 of clock operation mode control regist er (cmc)) = 0 and flpc, fsel (bits 1, 0 of operation speed mode control register (osmc)) = 0, 0. 4. when high-speed system clock and subsystem clock are stopped. 5. when internal high-speed oscillation, and high-speed system clock are stopped. when watchdog timer is stopped. when real-time counter is operating. 6. dedicated to pd78f150xa remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : internal high-speed oscillation clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency)
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 894 jun 20, 2011 dc characteristics (10/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av dd0 v dd , 1.8 v av dd1 v dd , 1.8 v av dd v dd , 1.8 v ev dd1 = v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit t a = ? 40 to +50 c 0.37 2.8 a t a = ? 40 to +70 c 0.37 5.2 a supply current i dd3 note 1 stop mode t a = ? 40 to +85 c 0.37 7.9 a v dd = 3.0 v 0.2 1 a rtc operating current i rtc notes 2, 3 f sub = 32.768 khz v dd = 2.0 v 0.2 1 a watchdog timer operating current i wdt notes 3, 4 f il = 30 khz 0.31 0.35 a lvi operating current i lvi note 5 9 18 a av dd0 = 5.0 v 1.7 3.4 ma normal mode 1 av dd0 = 3.0 v 0.7 1.4 ma normal mode 2 av dd0 = 2.3 v 0.5 1.2 ma during conversion at maximum speed ( pd78f150xa) low voltage mode av dd0 = 1.8 v 0.3 0.8 ma av dd = 5.0 v 1.7 3.4 ma normal mode 1 av dd = 3.0 v 0.7 1.4 ma normal mode 2 av dd = 2.3 v 0.5 1.2 ma a/d converter operating current i adc note 6 during conversion at maximum speed ( pd78f151xa) low voltage mode av dd = 1.8 v 0.3 0.8 ma selecting reference potential = av dd1 0.3 0.8 ma selecting reference potential = v refout 0.3 0.8 ma d/a converter operating current i dac note 7, 9 50 pf per 1 channel, i souce = i sink = 0 ma selecting reference potential = av refp 0.3 note 8 0.8 note 8 ma notes 1. total current flowing into v dd , ev dd , av dd0 , av dd1 , av dd , ev dd1 , and v lc0 to v lc3 , including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss , and excluding the current flowing into the real-time counter, watchdog timer, lv i circuit, a/d converter, d/a converter, operational amplifier, voltage refere nce, lcd controller/driver, i/o port, and on-chip pull-up/pull-dow n resistors. the maximums values include the peripheral operati on current and stop leakage current. when subsystem clock is stopped. when watchdog timer is stopped. 2. current flowing only to the real-time counter (v dd pin) (excluding the operating cu rrent of the xt1 oscillator). the current value of the 78k0r/lx3 micr ocontrollers is the typ. value, the sum of the typ. values of either i dd1 or i dd2 , and i rtc , when the real-time counter operates in an operation mode or halt mode. the i dd1 and i dd2 max. values also include the real-time coun ter operating current. when the real-time counter operates during f clk = f subc , the typ. value of i dd2 includes the real-time counter operating current. 3. when internal high-speed oscillator a nd high-speed system clock are stopped. 4. current flowing only to the watchdog timer (v dd pin) (including the operating current of the 30 khz internal oscillator). the current value of the 78k 0r/lx3 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i wdt when f clk = f subc or when the watchdog timer operates in stop mode. 5. current flowing only to the lvi circuit (v dd pin). the current value of the 78k0r/lx3 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvi when the lvi circuit operates in t he operation mode, halt mode or stop mode. 6. current flowing only to the a/d converter (av dd0 or (av dd pin). the current value of the 78k0r/lx3 microcontrollers is the sum of i dd1 or i dd2 and i adc when the a/d converter operates in an operation mode or halt mode. 7. current flowing only to the d/a converter (av dd1 pin). the current value of the 78k0r/lx3 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i dac when the d/a converter operates in an operation mode, halt mode or stop mode. 8. not including the current flowing to reference potential side. 9. dedicated to pd78f150xa
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 895 jun 20, 2011 dc characteristics (11/11) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av dd0 v dd , 1.8 v av dd1 v dd , 1.8 v av dd v dd , 1.8 v ev dd1 = v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit av dd0 = 5.0 v oaimi = 0 250 335 a av dd0 = 3.0 v oaimi = 0 230 320 a operational amplifier operating current i amp note 1, 6 av dd0 = 2.3 v oaimi = 0 220 310 a av dd0 = 5.0 v 19 38 a av dd0 = 3.0 v vr output = 2.5 v 9.5 25 a voltage reference operating current 1 i vr1 note 2, 6 av dd0 = 3.0 v vr output = 2.0 v 9.5 25 a v dd = 5.0 v 10 40 a v dd = 3.0 v vr output = 2.5 v 10 40 a voltage reference operating current 2 i vr2 note 3, 6 v dd = 3.0 v vr output = 2.0 v 10 40 a v dd = 5.0 v 0.28 1.2 a i lcd1 notes 4, 5 external resistance division method f lcd = f sub , lcd panel not connected, lcd clock = 512 hz v dd = 3.0 v 0.2 1.2 a v lcd = 01h 1.39 4.7 a 1/3 bias v lcd = 0fh 0.94 3.1 a i lcd2 note4 internal voltage boosting method f lcd = f sub , lcd panel not connected, lcd clock = 512 hz 1/4 bias v lcd = 0ah 1.53 5.0 a v dd = 5.0 v 0.56 2.0 a lcd operating current i lcd3 note4 capacitor split method f lcd = f sub , lcd panel not connected, lcd clock = 512 hz v dd = 3.0 v 0.36 1.7 a notes 1. current flowing only to the operational amplifier (av dd0 pin). the current value of the 78k0r/lx3 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i amp when the operational amplifie r operates in an operation mode, halt mode or stop mode. 2. current flowing only to the voltage reference (av dd0 pin). the current value of the 78k0r/lx3 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i vr1 when the voltage reference circuit op erates in an oper ation mode, halt mode or stop mode. 3. current flowing only to the voltage reference or i nput gate voltage boost circuit for the a/d converter (v dd pin). the current value of the 78k0r/lx3 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i vr2 when the voltage reference or boost circuit operates in an operation mode, halt mode or stop mode. 4. current flowing only to the lcd controller/driver (v dd pin). the current value of the 78k0r/lx3 microcontrollers is the sum of the lcd operating current (i lcd1 , i lcd2 or i lcd3 ) to the supply current (i dd1 , or i dd2 ) when the lcd controller/driver operates in an operation mode or halt mode. 5. not including the current that flows through the lcd divider resistor. 6. dedicated to pd78f150xa
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 896 jun 20, 2011 ac characteristics (1) basic operation (1/6) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, 1.8 v av dd0 v dd , 1.8 v av dd1 v dd , 1.8 v av dd v dd , 1.8 v ev dd1 = v dd , v ss = ev ss = av ss = 0 v) items symbol conditions min. typ. max. unit 2.7 v v dd 5.5 v 0.05 8 s normal power mode, fsel = 1 1.8 v v dd < 2.7 v 0.2 8 s 2.7 v v dd 5.5 v 0.1 8 s normal power mode, fsel = 0 1.8 v v dd < 2.7 v 0.2 8 s main system clock (f main ) operation low consumption power mode 1 8 s sdiv = 1 57.2 61 62.5 s subsystem clock (f sub ) operation sdiv = 0 28.5 30.5 31.3 s 2.7 v v dd 5.5 v 0.05 1 s normal power mode, fsel = 1 1.8 v v dd < 2.7 v 0.2 1 s instruction cycle (minimum instruction execution time) t cy in the self programmin g mode low consumption power mode note 0.88 1 1.15 s 2.7 v v dd 5.5 v 2.0 20.0 mhz external main system clock frequency f ex 1.8 v v dd < 2.7 v 2.0 5.0 mhz 2.7 v v dd 5.5 v 24 ns external main system clock input high-level width, low-level width t exh , t exl 1.8 v v dd < 2.7 v 96 ns ti00 to ti07, ti10 to ti13 input high-level width, low-level width t tih , t til 2/f mck +10 ns 2.7 v v dd 5.5 v 10 mhz to00 to to07, to10 to to13 output frequency f to 1.8 v v dd < 2.7 v 5 mhz 2.7 v v dd 5.5 v 10 mhz pclbuz0, pclbuz1 output frequency f pcl 1.8 v v dd < 2.7 v 5 mhz interrupt input high-level width, low-level width t inth , t intl 1 s key return input low-level width t kr 250 ns reset low-level width t rsl 10 s note in low-power-consumption mode, use the regulator with f clk fixed to 1 mhz when executing self programming. remarks 1. f mck : timer array unit operation clock frequency (operation clock to be set by the cksmn bit of the tmrm n register. m: unit number (m = 0, 1), n: channel number (n = 0 to 7)) 2. for details on the normal power mode and low c onsumption power mode according to the regulator output voltage, refer to chapter 25 regulator .
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 897 jun 20, 2011 (1) basic operation (2/6) minimum instruction execution time during main system clock operation (fsel = 0, rmc = 00h) 8.0 4.0 1.0 0.2 0.25 0.1 0.125 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 supply voltage v dd [v] cycle time t cy [ s] 1.8 2.1 guaranteed range of main system clock operation (fsel = 0, rmc = 00h) the range enclosed in dotted lines applies when the internal high-speed oscillation clock (8mhz) is selected. remark fsel: bit 0 of the operation sp eed mode control register (osmc)
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 898 jun 20, 2011 (1) basic operation (3/6) minimum instruction execution time during main system clock operation (fsel = 1, rmc = 00h) 8.0 1.0 0.2 0.1 0.05 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 0.01 4.0 0.25 0.125 guaranteed range of main system clock operation (fsel = 1, rmc = 00h) the range enclosed in dotted lines applies when the internal high-speed oscillation clock (8mhz) is selected. supply voltage v dd [v] cycle time t cy [ s] 1.8 caution when v dd < 2.25 v and fsel = 1, it is prohi bited to release stop mode during f ex operation or f ih operation (this must not be perfo rmed even if the frequency is di vided. the stop mode may be released during f x operation.). remarks 1. fsel: bit 0 of the operation sp eed mode control register (osmc) 2. f x : x1 clock oscillation frequency f ih : internal high-speed oscillation clock frequency f ex : external main system clock frequency f main : main system clock frequency f sub : subsystem clock frequency f clk : cpu/peripheral hardware clock frequency
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 899 jun 20, 2011 (1) basic operation (4/6) minimum instruction execution time during main sy stem clock operation (fsel = 0, rmc = 5ah) 8.0 4.0 1.0 0.1 0.05 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 0.01 1.8 supply voltage v dd [v] cycle time t cy [ s] guaranteed range of main system clock operation (fsel = 0, rmc = 5ah) the range enclosed in dotted lines applies when the internal high-speed oscillation clock (8mhz) is selected. remarks 1. fsel: bit 0 of the operation sp eed mode control register (osmc) 2. the entire voltage range is 1 mhz (max.) when rmc is set to 5ah.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 900 jun 20, 2011 (1) basic operation (5/6) minimum instruction execution time duri ng self programming mode (rmc = 00h) 1.0 0.1 0.2 0.05 0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 0.01 2.7 1.8 0.25 0.125 2.0 cycle time t cy [ s] supply voltage v dd [v] guaranteed range of self programming mode (rmc = 00h) the range enclosed in dotted lines applies when the internal high-speed oscillation clock (8mhz) is selected. minimum instruction execution time duri ng self programming mode (rmc = 5ah) cycle time t cy [ s] supply voltage v dd [v] 1.0 0.1 0.2 0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 0.01 1.8 2.0 guaranteed range of self programming mode (rmc = 5ah) the dotted line indicates the minimum instruction execution time when the internal high-speed oscillation clock (8mhz) is selected. remark the self programming function cannot be used wh en the cpu operates with the subsystem clock.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 901 jun 20, 2011 (1) basic operation (6/6) ac timing test points v ih v il test points v ih v il external main system clock timing exclk 0.8v dd (min.) 0.2v dd (max.) 1/f ex t exl t exh ti timing ti01 to ti07, ti10 to ti13 t til t tih interrupt request input timing intp0 to intp11 t intl t inth key interrupt input timing kr0 to kr7 t kr reset input timing reset t rsl
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 902 jun 20, 2011 (2) serial interface: se rial array unit (1/18) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = avss = 0 v) (a) during communication at same potential (uart mode) (dedicat ed baud rate ge nerator output) parameter symbol conditions min. typ. max. unit f mck /6 bps transfer rate f clk = 20 mhz, f mck = f clk 3.3 mbps uart mode connection diagram (duri ng communication at same potential) 78k0r/lx3 microcontrollers user's device txdq rxdq rx tx uart mode bit width (dur ing communication at same potential) (reference) baud rate error tolerance high-/low-bit width 1/transfer rate txdq rxdq caution select the normal input buffer for rxdq and th e normal output mode for txdq by using the pimg and pomx registers. remarks 1. q: uart number (q = 0 to 3), g: pim number (g = 1, 7), x: pom number (x = 1, 7, 8) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of t he smrmn register. m: unit number (m = 0, 1), n: channel number (n = 0, 2))
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 903 jun 20, 2011 (2) serial interface: se rial array unit (2/18) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = avss = 0 v) (b) during communication at same pot ential (csi mode) (master mode, sckp... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd = ev dd 5.5 v 200 note 1 ns 2.7 v v dd = ev dd < 4.0 v 300 note 1 ns sckp cycle time t kcy1 1.8 v v dd = ev dd < 2.7 v 600 note 1 ns 4.0 v v dd = ev dd 5.5 v t kcy1 /2 ? 20 ns 2.7 v v dd = ev dd < 4.0 v t kcy1 /2 ? 35 ns sckp high-/low-level width t kh1 , t kl1 1.8 v v dd = ev dd < 2.7 v t kcy1 /2 ? 80 ns 4.0 v v dd = ev dd 5.5 v 70 ns 2.7 v v dd = ev dd < 4.0 v 100 ns sip setup time (to sckp ) note 2 t sik1 1.8 v v dd = ev dd < 2.7 v 190 ns sip hold time (from sckp ) note 3 t ksi1 30 ns delay time from sckp to sop output note 4 t kso1 c = 30 pf note 5 40 ns notes 1. the value must also be 4/f clk or more. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and c kpmn = 1. the sip set up time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpm n = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 5. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for sip and the no rmal output mode for sop and sckp by using the pimg and pomx registers. remarks 1. p: csi number (p = 00, 01, 10, 20), g: pim num ber (g = 1, 7), x: pom number (x = 1, 7, 8) 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 2)
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 904 jun 20, 2011 (2) serial interface: se rial array unit (3/18) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = avss = 0 v) (c) during communication at same potential (csi mode) (slave m ode, sckp... external clock input) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 6/f mck ns 16 mhz < f mck 8/f mck ns 2.7 v v dd < 4.0 v f mck 16 mhz 6/f mck ns 16 mhz < f mck 8/f mck ns sckp cycle time t kcy2 1.8 v v dd < 2.7 v f mck 16 mhz 6/f mck ns sckp high-/low-level width t kh2 , t kl2 t kcy2 /2 ns sip setup time (to sckp ) note 1 t sik2 80 ns sip hold time (from sckp ) note 2 t ksi2 1/f mck +50 ns 4.0 v v dd = ev dd 5.5 v 2/f mck +45 ns 2.7 v v dd = ev dd < 4.0 v 2/f mck +57 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note 4 1.8 v v dd = ev dd < 2.7 v 2/f mck +125 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and c kpmn = 1. the sip set up time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpm n = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for sip and sckp and the normal output mode for sop by using the pimg and pomx registers. remarks 1. p: csi number (p = 00, 01, 10, 20), g: pim num ber (g = 1, 7), x: pom number (x = 1, 7, 8) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of t he smrmn register. m: unit number (m = 0, 1), n: channel number (n = 0 to 2))
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 905 jun 20, 2011 (2) serial interface: se rial array unit (4/18) csi mode connection diagram (duri ng communication at same potential) 78k0r/lx3 microcontrollers user's device sckp sop sck si sip so csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1, 2 t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1, 2 t kh1, 2 t kl1, 2 t sik1, 2 t ksi1, 2 t kso1, 2 sckp remarks 1. p: csi number (p = 00, 01, 10, 20) 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 2)
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 906 jun 20, 2011 (2) serial interface: se rial array unit (5/18) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = avss = 0 v) (d) during communication at sam e potential (simplified i 2 c mode) parameter symbol conditions min. max. unit 2.7 v v dd = ev dd 5.5 v r b = 3 k , c b = 100 pf 400 khz sclr clock frequency f scl 1.8 v v dd = ev dd 5.5 v r b = 5 k , c b = 100 pf 300 khz 2.7 v v dd = ev dd 5.5 v r b = 3 k , c b = 100 pf 1200 ns hold time when sclr = ?l? t low 1.8 v v dd = ev dd 5.5 v r b = 5 k , c b = 100 pf 1500 ns 2.7v v dd = ev dd 5.5 v r b = 3 k , c b = 100 pf 1200 ns hold time when sclr = ?h? t high 1.8 v v dd = ev dd 5.5 v r b = 5 k , c b = 100 pf 1500 ns 2.7v v dd = ev dd 5.5 v r b = 3 k , c b = 100 pf 1/f mck +120 ns data setup time (reception) t su:dat 1.8 v v dd = ev dd 5.5 v r b = 5 k , c b = 100 pf 1/f mck +230 ns 2.7v v dd = ev dd 5.5 v r b = 3 k , c b = 100 pf 0 660 ns data hold time (transmission) t hd:dat 1.8 v v dd = ev dd 5.5 v r b = 5 k , c b = 100 pf 0 710 ns caution select the normal input buffer and the n-ch open drain output (v dd tolerance) mode for sdar and the normal output mode for sclr by usin g the pimg and pomx registers. remarks 1. r b [ ]:communication line (sdar) pull-up resistance, c b [f]: communication line (sclr, sdar) load capacitance 2. r: iic number (r = 10, 20), g: pim number (g = 1, 7), x: pom number (x = 1, 7, 8) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of t he smrmn register. m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 02, 10)
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 907 jun 20, 2011 (2) serial interface: se rial array unit (6/18) simplified i 2 c mode mode connection diagram (dur ing communication at same potential) 78k0r/lx3 microcontrollers user's device sdar sclr sda scl v dd r b simplified i 2 c mode serial transfer timing (dur ing communication at same potential) sdar t low 1/f scl t high t hd:dat sclr t su:dat remarks 1. r b [ ]:communication line (sdar) pull-up resistance, c b [f]: communication line (sclr, sdar) load capacitance 2. r: iic number (r = 10, 20)
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 908 jun 20, 2011 (2) serial interface: se rial array unit (7/18) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = avss = 0 v) (e) communication at different potential (2.5 v, 3 v) ( uart mode) (dedicated baud rate generator output) (1/2) parameter symbol conditions min. typ. max. unit f mck /6 bps 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v f clk = 20 mhz, f mck = f clk 3.3 mbps f mck /6 bps transfer rate reception 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v f clk = 20 mhz, f mck = f clk 3.3 mbps caution select the ttl input buffer for rxdq and the n-ch open drain output (v dd tolerance) mode for txdq by using the pimg and pomx registers. remarks 1. q: uart number (q = 0 to 3), g: pim number (g = 1, 7), x: pom number (x = 1, 7, 8) 2. v b [v]: communication line voltage 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of the smrmn register. m: unit number (m = 0, 1), n: channel number (n = 0, 2)) 4. v ih and v il below are observation points for the ac char acteristics of the serial array unit when communicating at different potentials in uart mode. 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v: v ih = 2.0 v, v il = 0.5 v
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 909 jun 20, 2011 (2) serial interface: se rial array unit (8/18) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = avss = 0 v) (e) communication at different potential (2.5 v, 3 v) ( uart mode) (dedicated baud rate generator output) (2/2) parameter symbol conditions min. typ. max. unit note 1 bps 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v f clk = 16.8 mhz, f mck = f clk , c b = 50 pf, r b = 1.4 k , v b = 2.7 v 2.8 note 2 mbps note 3 bps transfer rate transmission 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v f clk = 19.2 mhz, f mck = f clk , c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note 4 mbps notes 1. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 4.0 v v dd = ev dd 5.5 v and 2.7 v v b 4.0 v 1 maximum transfer rate = 2.2 { ? c b r b ln (1 ? v b )} 3 [bps] 1 2.2 transfer rate 2 ? { ? c b r b ln (1 ? v b )} baud rate error (theoretical value) = 1 100 [%] ( transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference between the transmission and reception sides. 2. this value as an example is calculated when the condit ions described in the ?conditions? column are met. refer to note 1 above to calculate the maximum tr ansfer rate under conditions of the customer. 3. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v v dd = ev dd < 4.0 v and 2.3 v v b < 2.7 v 1 maximum transfer rate = 2.0 { ? c b r b ln (1 ? v b )} 3 [bps] 1 2.0 transfer rate 2 ? { ? c b r b ln (1 ? v b )} baud rate error (theoretical value) = 1 100 [%] ( transfer rate ) number of transferred bits * this value is the theoretical va lue of the relative difference between the transmission and reception sides. 4. this value as an example is calculated when the condit ions described in the ?conditions? column are met. refer to note 3 above to calculate the maximum tr ansfer rate under conditions of the customer. caution select the ttl input buffer for rxdq and the n-ch open drain output (v dd tolerance) mode for txdq by using the pimg and pomx registers. (remarks are given on the next page.)
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 910 jun 20, 2011 (2) serial interface: se rial array unit (9/18) remarks 1. r b [ ]:communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage 2. q: uart number (q = 0 to 3) , g: pim number (g = 1, 7), x: pom number (x = 1, 7, 8) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of t he smrmn register. m: unit number (m = 0, 1), n: channel number (n = 0, 2)) 4. v oh and vo l below are observation points for the ac c haracteristics of the serial array unit when communicating at different potentials in uart mode. 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v: v oh = 2.2 v, vo l = 0.8 v 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v: v oh = 2.0 v, vo l = 0.5 v
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 911 jun 20, 2011 (2) serial interface: se rial array unit (10/18) uart mode connection diagram (communication at different potential) 78k0r/lx3 microcontrollers user's device txdq rxdq rx tx v b r b uart mode bit width (communication at different potential) (reference) txdq rxdq baud rate error tolerance baud rate error tolerance low-bit width high-/low-bit width high-bit width 1/transfer rate 1/transfer rate caution select the ttl input buffer for rxdq and the n-ch open drain output (v dd tolerance) mode for txdq by using the pimg and pomx registers. remarks 1. r b [ ]:communication line (txdq) pull-up resistance, v b [v]: communication line voltage 2. q: uart number (q = 0 to 3) , g: pim number (g = 1, 7), x: pom number (x = 1, 7, 8)
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 912 jun 20, 2011 (2) serial interface: se rial array unit (11/18) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = avss = 0 v) (f) communication at different potential (2.5 v, 3 v) (c si mode) (master mode, sckp ... internal clock output) (1/2) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 400 note 1 ns sckp cycle time t kcy1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 30 pf, r b = 2.7 k 800 note 1 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 75 ns sckp high-level width t kh1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 170 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k t kcy1 /2 ? 20 ns sckp low-level width t kl1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 35 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 150 ns sip setup time (to sckp ) note 2 t sik1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 30 pf, r b = 2.7 k 275 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 30 ns sip hold time (from sckp ) note 2 t ksi1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 30 pf, r b = 2.7 k 30 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 120 ns delay time from sckp to sop output note 2 t kso1 2.7 v v dd 4.0 v, 2.3 v v b < 2.7 v, c b = 30 pf, r b = 2.7 k 215 ns notes 1. the value must also be 4/f clk or more. 2. when dap0n = 0 and ckp0n = 0, or dap0n = 1 and ckp0n = 1. caution select the ttl input buffer for sip and the n-ch open drain output (v dd tolerance) mode for sop and sckp by using the pimg and pomx registers. remarks 1. p: csi number (p = 00, 01, 10, 20), g: pim number (g = 1, 7), x: pom number (x = 1, 7, 8) 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 2) 3. r b [ ]:communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sip, sop, sckp) load capacitance, v b [v]: communication line voltage 4. v ih and v il below are observation points for the ac characteristics of the serial array unit when communicating at different potentials in csi mode. 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v: v ih = 2.0 v, v il = 0.5 v
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 913 jun 20, 2011 (2) serial interface: se rial array unit (12/18) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = avss = 0 v) (f) communication at different potential (2.5 v, 3 v) (c si mode) (master mode, sckp ... internal clock output) (2/2) parameter symbol conditions min. typ. max. unit 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 70 ns sip setup time (to sckp ) note t sik1 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 30 pf, r b = 2.7 k 100 ns 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 30 ns sip hold time (from sckp ) note t ksi1 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 30 pf, r b = 2.7 k 30 ns 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 40 ns delay time from sckp to sop output note t kso1 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v, c b = 30 pf, r b = 2.7 k 40 ns note when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. csi mode connection diagram (communication at different potential) v b r b 78k0r/lx3 microcontrollers user's device sckp sop sck si sip so v b r b caution select the ttl input buffer for sip and the n-ch open drain output (v dd tolerance) mode for sop and sckp by using the pimg and pomx registers. remarks 1. p: csi number (p = 00, 01, 10, 20), g: pim number (g = 1, 7), x: pom number (x = 1, 7, 8) 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 2) 3. r b [ ]:communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sip, sop, sckp) load capacitance, v b [v]: communication line voltage 4. v ih and v il below are observation points for the ac char acteristics of the serial array unit when communicating at different potentials in csi mode. 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v: v ih = 2.0 v, v il = 0.5 v
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 914 jun 20, 2011 (2) serial interface: se rial array unit (13/18) csi mode serial transfer timing (communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp csi mode serial transfer timing (communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 sckp caution select the ttl input buffer for sip and the n-ch open drain output (v dd tolerance) mode for sop and sckp by using the pimg and pomx registers. remarks 1. p: csi number (p = 00, 01, 10, 20), g: pim number (g = 1, 7), x: pom number (x = 1, 7, 8) 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 2)
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 915 jun 20, 2011 (2) serial interface: se rial array unit (14/18) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = avss = 0 v) (g) communication at different potential (2.5 v, 3 v) (csi mode) (slave mode, sckp... external clock input) parameter symbol conditions min. typ. max. unit 13.6 mhz < f mck 10/f mck ns 6.8 mhz < f mck 13.6 mhz 8/f mck ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f mck 6.8 mhz 6/f mck ns 18.5 mhz < f mck 16/f mck ns 14.8 mhz < f mck 18.5 mhz 14/f mck ns 11.1 mhz < f mck 14.8 mhz 12/f mck ns 7.4 mhz < f mck 11.1 mhz 10/f mck ns 3.7 mhz < f mck 7.4 mhz 8/f mck ns sckp cycle time t kcy2 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v f mck 3.7 mhz 6/f mck ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v f kcy2 /2 ? 20 ns sckp high-/low-level width t kh2 , t kl2 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v f kcy2 /2 ? 35 ns sip setup time (to sckp ) note 1 t sik2 90 ns sip hold time (from sckp ) note 2 t ksi2 1/f mck + 50 ns 4.0 v v dd 5.5 v, 2.7 v v b 4.0 v, c b = 30 pf, r b = 1.4 k 2/f mck + 120 ns delay time from sckp to sop output note 3 t kso2 2.7 v v dd < 4.0 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 2/f mck + 230 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and c kpmn = 1. the sip set up time becomes ?to sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpm n = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. csi mode connection diagram (communication at different potential) 78k0r/lx3 microcontrollers user's device sckp sop sck si sip so v b r b (caution and remark are given on the next page.)
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 916 jun 20, 2011 (2) serial interface: se rial array unit (15/18) caution select the ttl input buffer for sip and sckp and the n-ch open drain output (v dd tolerance) mode for sop by using the pimg and pomx registers. remarks 1. p: csi number (p = 00, 01, 10, 20), g: pim number (g = 1, 7), x: pom number (x = 1, 7, 8) 2. r b [ ]:communication line (sop) pull-up resistance, c b [f]: communication line (sop, sckp) load capacitance, v b [v]: communication line voltage 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of t he smrmn register. m: unit number (m = 0, 1), n: channel number (n = 0 to 2)) 4. v ih and v il below are observation points for the ac characteristics of the serial array unit when communicating at different potentials in csi mode. 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v: v ih = 2.0 v, v il = 0.5 v
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 917 jun 20, 2011 (2) serial interface: se rial array unit (16/18) csi mode serial transfer timing (communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip input data output data sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp csi mode serial transfer timing (communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip input data output data sop t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 sckp caution select the ttl input buffer for sip and sckp and the n-ch open drain output (v dd tolerance) mode for sop by using the pimg and pomx registers. remarks 1. p: csi number (p = 00, 01, 10, 20), g: pim number (g = 1, 7), x: pom number (x = 1, 7, 8) 2. m: unit number (m = 0, 1), n: channel number (n = 0 to 2)
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 918 jun 20, 2011 (2) serial interface: se rial array unit (17/18) (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, v ss = ev ss = avss = 0 v) (h) communication at different potential (2.5 v, 3 v) (simplified i 2 c mode) parameter symbol conditions min. max. unit 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v, r b = 1.4 k , c b = 100 pf 400 khz sclr clock frequency f scl 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v, r b = 2.7 k , c b = 100 pf 400 khz 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v, r b = 1.4 k , c b = 100 pf 1275 ns hold time when sclr = ?l? t low 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v, r b = 2.7 k , c b = 100 pf, 1275 ns 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v, r b = 1.4 k , c b = 100 pf 655 ns hold time when sclr = ?h? t high 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v, r b = 2.7 k , c b = 100 pf 655 ns 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v, r b = 1.4 k , c b = 100 pf 1/f mck + 190 ns data setup time (reception) t su:dat 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v, r b = 2.7 k , c b = 100 pf 1/f mck + 190 ns 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v, r b = 1.4 k , c b = 100 pf 0 640 ns data hold time (transmission) t hd:dat 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v, r b = 2.7 k , c b = 100 pf 0 660 ns caution select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for sdar and the n-ch open drain output (v dd tolerance) mode for sclr by us ing the pimg and pomx registers. remarks 1. r b [ ]:communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage 2. r: iic number (r = 10, 20), g: pim number (g = 1, 7), x: pom number (x = 1, 7, 8) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of the smrmn register. m: unit number (m = 0, 1), n: channel number (n = 0, 2), mn = 02, 10) 4. v ih and v il below are observation points for the ac c haracteristics of the serial array unit when communicating at different potentials in simplified i 2 c mode mode. 4.0 v v dd = ev dd 5.5 v, 2.7 v v b 4.0 v: v ih = 2.2 v, v il = 0.8 v 2.7 v v dd = ev dd < 4.0 v, 2.3 v v b < 2.7 v: v ih = 2.0 v, v il = 0.5 v
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 919 jun 20, 2011 (2) serial interface: se rial array unit (18/18) simplified i 2 c mode connection diagram (communication at different potential) simplified i 2 c mode serial transfer timing (communication at different potential) sdar t low t high t hd:dat scr t su:dat 1/f scl caution select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for sdar and the n-ch open drain output (v dd tolerance) mode for sclr by us ing the pimg and pomx registers. remarks 1. r b [ ]:communication line (sdar, sclr) pull-up resistance, v b [v]: communication line voltage 2. r: iic number (r = 10, 20), g: pim number (g = 1, 7), x: pom number (x = 1, 7, 8) 78k0r/lx3 microcontrolles user's device sdar sclr sda scl v b r b v b r b
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 920 jun 20, 2011 (3) serial interface: iica (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = avss = 0 v) (a) iica standard mode high-speed mode parameter symbol conditions min. max. min. max. unit scl0 clock frequency f scl fast mode: f clk 3.5 mhz, standard mode: f clk 1 mhz 0 100 0 400 khz setup time of restart condition note 1 t su:sta 4.7 0.6 s hold time t hd:sta 4.0 0.6 s hold time when scl0 = ?l? t low 4.7 1.3 s hold time when scl0 = ?h? t high 4.0 0.6 s data setup time (reception) t su:dat 250 100 ns data hold time (transmission) note 2 t hd:dat 0 3.45 0 0.9 s setup time of stop condition t su:sto 4.0 0.6 s bus-free time t buf 4.7 1.3 s notes 1. the first clock pulse is generated after this per iod when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. remark f clk : cpu/peripheral hardware clock frequency iica serial transfer timing t low t buf t high t hd:sta stop condition start condition restart condition stop condition t su:dat t su:sta t su:sto t hd:sta t hd:dat scl0 sda0
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 921 jun 20, 2011 (4) serial interface: on-chip debug (uart) (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = avss = 0 v) (a) on-chip debug (uart) parameter symbol conditions min. typ. max. unit f clk /2 12 f clk /6 bps transfer rate flash memory programming mode (f clk = 20 mhz, 2.7 v v dd = ev dd, c b = 50 pf) 3.33 mbps 2.7 v v dd = ev dd 5.5 v 10 mhz tool1 output frequency f tool1 1.8 v v dd = ev dd < 2.7 v 2.5 mhz
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 922 jun 20, 2011 analog characteristics (1) 12-bit a/d converter ( pd78f150xa) (a) t a = 0 to 50 c, 1.8 v ad refp av dd0 , 2.3 v av dd0 v dd 3.6 v, v ss = ev ss = av ss = ad refm = 0 v parameter symbol conditions min. typ. max. unit resolution res 12 12 12 bit 2.3 v ad refp 3.6 v 2.0 6.0 lsb overall error note ainl 1.8 v ad refp < 2.3 v 3.0 6.0 lsb normal mode 1, normal mode 2 5 50 s conversion time t conv low voltage mode 6.25 50 s zero-scale error note e zs 2.0 4.0 lsb full-scale error note e fs 2.0 4.0 lsb integral non-linearity error note ile 2.0 lsb differential non-linearity error note dle 1.0 lsb reference voltage (high potential side) ad refp 1.8 av dd0 v analog input voltage v ain ad refm ad refp v reference supply current i ref 46 200 a (b) t a = ? 40 to +85 c , 1.8 v ad refp av dd0 , 1.8 v av dd0 v dd 5.5 v, v ss = ev ss = av ss = ad refm = 0 v parameter symbol conditions min. typ. max. unit resolution res 12 12 12 bit 3.6 v ad refp 5.5 v 2.0 10.0 lsb 2.3 v ad refp < 3.6 v 2.0 10.0 lsb overall error note ainl 1.8 v ad refp < 2.3 v 3.0 10.0 lsb normal mode 1, normal mode 2 5 50 s conversion time t conv low voltage mode 21 50 s zero-scale error note e zs 2.0 8.0 lsb full-scale error note e fs 2.0 8.0 lsb integral non-linearity error note ile 6.0 lsb differential non-linearity error note dle 2.0 lsb reference voltage (high potential side) ad refp 1.8 av dd0 v analog input voltage v ain ad refm ad refp v reference supply current i ref 46 220 a note excludes quantization error ( 1/2 lsb). remarks 1. ad refp is the input voltage from the av refp pin or the voltage generated by the voltage reference. 2. ad refm is the input voltage from the av refm pin or the grand potentia l of a/d converter.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 923 jun 20, 2011 (2) 10-bit a/d converter ( pd78f151xa) (a) t a = 40 to +85 c, 1.8 v ad ref av dd v dd = ev dd0 = ev dd1 5.5 v, v ss = ev ss = av ss = 0 v parameter symbol conditions min. typ. max. unit resolution res 10 10 10 bit overall error note ainl 0.4 %fsr normal mode 1, normal mode 2 5 50 s conversion time t conv low voltage mode 21 50 s zero-scale error note e zs 0.4 %fsr full-scale error note e fs 0.4 %fsr integral non-linearity error note ile 2.5 lsb differential non-linearity error note dle 1.5 lsb analog input voltage v ain av ss ad ref v note excludes quantization error ( 1/2 lsb). (3) operational amplifier ( pd78f150xa) (t a = ? 40 to +85 c, 2.3 v av dd0 v dd 5.5 v, v ss = ev ss =av ss = 0 v) parameter symbol conditions min. typ. max. unit common-mode input voltage v iamp av dd0 = 3.0 v 0 av dd0 ? 0.6 v input offset voltage v ioamp 10 mv maximum output voltage (high level) v ohamp av dd0 = 3.0 v/2.3 v, i source = ? 500 a av dd0 ? 0.2 v maximum output voltage (low level) v olamp av dd0 = 3.0 v/2.3 v, i source = 500 a 0.1 v open-loop gain av dd0 = 3.0 v 100 db gbw gbw av dd0 = 3.0 v 3 mhz input noise spectral density v namp av dd0 = 3.0 v, v in = av dd0 /2 60 z h / nv slew rate sr amp av dd0 = 3.0 v 2 v/ s turn on time t onamp 20 s (4) voltage reference ( pd78f150xa) (t a = ? 40 to +85 c, 2.3 v av dd0 v dd 5.5 v, v ss = ev ss =av ss = 0 v) parameter symbol conditions min. typ. max. unit vrgv = 0, 2.7 v av dd0 5.5 v, t a = 25 c 2.45 2.5 2.55 v output reference voltage v refout vrgv = 1, 2.3 v av dd0 5.5 v, t a = 25 c 1.96 2 2.04 v temperature coefficient 40 ppm/ c settling time 17 ms caution connect the v refout pin to gnd via a tantalum capacitor (cap acitance: 10 f 30 %, esr: 2 (max.), esl: 10 nh (max.)) and a ceramic capacitor (capacitance: 0.1 f 30 %, esr: 2 (max.), esl: 10 nh (max.)). remark the settling time of the vr circuit is the time requ ired until the reference voltage output voltage reaches the values above.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 924 jun 20, 2011 (5) d/a converter ( pd78f150xa) (a) t a = 0 to 50 c, 1.8 v da refp av dd1 , 2.3 v av dd1 = v dd 3.6 v, v ss = ev ss = av ss = 0 v parameter symbol conditions min. typ. max. unit resolution res 12 12 12 bit settling time t set 18 s off-set error e o 5 10 mv gain error e g 5 10 mv integral non-linearity error ile 2.0 4.0 lsb differential non-linearity error dle i source = i sink = 0 ma, 0.1 v anon av dd1 ? 0.1 v (n = 0, 1) 2.0 lsb 0 v anon 0.3 v or av dd1 ? 0.3 v anon av dd1 (n = 0, 1) 150 250 d/a output resistance value r o 0.3 v anon av dd1 ? 0.3 v (n = 0, 1) 5 10 output source current i source 0.1 ma output sink current i sink 0.3 v anon av dd1 ? 0.3 v (n = 0, 1) 0.1 ma (b) t a = ? 40 to +85 c, 1.8 v da refp av dd1 , 2.3 v av dd1 = v dd 5.5 v, v ss = ev ss = av ss = 0 v parameter symbol conditions min. typ. max. unit resolution res 12 12 12 bit settling time t set 18 s off-set error e o 5 20 mv gain error e g 5 20 mv integral non-linearity error ile 6.0 12.0 lsb differential non-linearity error dle i source = i sink = 0 ma, 0.1 v anon av dd1 ? 0.1 v (n = 0, 1) 8.0 lsb 0 v anon 0.3 v or av dd1 ? 0.3 v anon av dd1 (n = 0, 1) 150 250 d/a output resistance value r o 0.3 v anon av dd1 ? 0.3 v (n = 0, 1) 5 20 output source current i source 0.1 ma output sink current i sink 0.3 v anon av dd1 ? 0.3 v (n = 0, 1) 0.1 ma remarks 1. use the d/a converter under the condition of the output load capacit ance (c) = 50 pf (max.). 2. da refp is the input voltage from the av refp pin, the voltage generated by the voltage reference, or the input voltage from the av dd1 pin. it is selected as the positive reference voltage of the d/a converter.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 925 jun 20, 2011 lcd characteristics (1/4) (1) resistance division method (a) static display mode (t a = ? 40 to +85 c, v lcd (min.) v dd = ev dd 5.5 v, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd 2.0 v dd v lcd output resistor note (common) r odc i o = 5 a 40 k lcd output resistor note (segment) r ocs i o = 1 a 200 k (b) 1/2 bias method, 1/4 bias method (t a = ? 40 to +85 c, v lcd (min.) v dd = ev dd 5.5 v, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd 2.7 v dd v lcd output resistor note (common) r odc i o = 5 a 40 k lcd output resistor note (segment) r ocs i o = 1 a 200 k (c) 1/3 bias method (t a = ? 40 to +85 c, v lcd (min.) v dd = ev dd 5.5 v, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd 2.5 v dd v lcd output resistor note (common) r odc i o = 5 a 40 k lcd output resistor note (segment) r ocs i o = 1 a 200 k note the output resistor is a resist or connected between one of the v lc0 , v lc1 , v lc2 , v lc3 and v ss pins, and either of the seg and com pins.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 926 jun 20, 2011 lcd characteristics (2/4) (2) internal voltage boosting method (1/2) (a) 1/3 bias method (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit vlcd = 00h 1.67 1.75 1.83 v vlcd = 01h 1.62 1.70 1.78 v vlcd = 02h 1.57 1.65 1.73 v vlcd = 03h 1.52 1.60 1.68 v vlcd = 04h 1.47 1.55 1.63 v vlcd = 05h 1.42 1.50 1.58 v vlcd = 06h 1.37 1.45 1.53 v vlcd = 07h 1.32 1.40 1.48 v vlcd = 08h 1.27 1.35 1.43 v vlcd = 09h 1.22 1.30 1.375 v vlcd = 0ah 1.17 1.25 1.33 v vlcd = 0bh 1.12 1.20 1.28 v vlcd = 0ch 1.07 1.15 1.23 v vlcd = 0dh 1.02 1.10 1.18 v vlcd = 0eh 0.97 1.05 1.13 v vlcd = 0fh 0.92 1.00 1.08 v vlcd = 10h 0.87 0.95 1.03 v vlcd = 11h 0.82 0.90 0.98 v vlcd = 12h 0.77 0.85 0.93 v lcd output voltage variation range v lcd2 c1 to c4 note 1 = 0.47 f note 2 vlcd = 13h 0.72 0.80 0.88 v doubler output voltage v lcd1 c1 to c4 note 1 = 0.47 f 2 v lcd2 ? 0.1 2 v lcd2 2 v lcd2 v tripler output voltage v lcd0 c1 to c4 note 1 = 0.47 f 3 v lcd2 ? 0.15 3 v lcd2 3 v lcd2 v reference voltage setup time note 2 t vawait2 2 ms 500 ms voltage boost wait time note 3 t vawait1 v dd > v lc0 5 s lcd output resistor note 4 (common) r odc i o = 5 a 40 k lcd output resistor note 4 (segment) r ocs i o = 1 a 200 k notes 1. this is a capacitor that is connected between voltage pins used to drive the lcd. c1: a capacitor connected between caph and capl c2: a capacitor connected between v lc0 and gnd c3: a capacitor connected between v lc1 and gnd c4: a capacitor connected between v lc2 and gnd c1 = c2 = c3 = c4 = 0.47 pf 30 % 2. this is the required wait time from when the referenc e voltage is specified by using the lvcd register (or the register is reset to use the default value of the referenc e voltage) until voltage boosting is started (vlcon = 1). 3. this is the wait time from when voltage boosting is started (vlcon = 1) until display is enabled (lcdon = 1). 4. the output resistor is a resist or connected between one of the v lc0 , v lc1 , v lc2 and v ss pins, and either of the seg and com pins.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 927 jun 20, 2011 lcd characteristics (3/4) (2) internal voltage boosting method (2/2) (b) 1/4 bias method (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit vlcd = 00h note 5 1.67 1.75 1.83 v vlcd = 01h note 5 1.62 1.70 1.78 v vlcd = 02h note 5 1.57 1.65 1.73 v vlcd = 03h note 5 1.52 1.60 1.68 v vlcd = 04h note 5 1.47 1.55 1.63 v vlcd = 05h note 5 1.42 1.50 1.58 v vlcd = 06h note 5 1.37 1.45 1.53 v vlcd = 07h note 5 1.32 1.40 1.48 v vlcd = 08h note 5 1.27 1.35 1.43 v vlcd = 09h 1.22 1.30 1.375 v vlcd = 0ah 1.17 1.25 1.33 v vlcd = 0bh 1.12 1.20 1.28 v vlcd = 0ch 1.07 1.15 1.23 v vlcd = 0dh 1.02 1.10 1.18 v vlcd = 0eh 0.97 1.05 1.13 v vlcd = 0fh 0.92 1.00 1.08 v vlcd = 10h 0.87 0.95 1.03 v vlcd = 11h 0.82 0.90 0.98 v vlcd = 12h 0.77 0.85 0.93 v lcd output voltage variation range v lcd3 c1 to c5 note 1 = 0.47 f note 2 vlcd = 13h 0.72 0.80 0.88 v doubler output voltage v lcd2 c1 to c5 note 1 = 0.47 f 2 v lcd3 ? 0.08 2 v lcd3 2 v lcd3 v tripler output voltage v lcd1 c1 to c5 note 1 = 0.47 f 3 v lcd3 ? 0.12 3 v lcd3 3 v lcd3 v quadruply output voltage v lcd0 c1 to c5 note 1 = 0.47 f 4 v lcd3 ? 0.16 4 v lcd3 4 v lcd3 v reference voltage setup time note 2 t vawait2 2 ms 500 ms voltage boost wait time note 3 t vawait1 v dd > v lc0 5 s lcd output resistor note 4 (common) r odc i o = 5 a 40 k lcd output resistor note 4 (segment) r ocs i o = 1 a 200 k notes 1. this is a capacitor that is connected between voltage pins used to drive the lcd. c1: a capacitor connected between caph and capl c2: a capacitor connected between v lc0 and gnd c3: a capacitor connected between v lc1 and gnd c4: a capacitor connected between v lc2 and gnd c5: a capacitor connected between v lc3 and gnd c1 = c2 = c3 = c4 = c5 = 0.47 pf 30 % 2. this is the required wait time from when the referenc e voltage is specified by using the lvcd register (or the register is reset to use the default value of the referenc e voltage) until voltage boosting is started (vlcon = 1). 3. this is the wait time from when voltage boosting is started (vlcon = 1) until display is enabled (lcdon = 1). 4. the output resistor is a resist or connected between one of the v lc0 , v lc1 , v lc2 , v lc3 and v ss pins, and either of the seg and com pins. 5. these settings are prohibited because v lc0 > 5.5 v.
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 928 jun 20, 2011 lcd characteristics (4/4) (3) capacitor split method ? 1/3 bias method (t a = ? 40 to +85 c, 2.2 v v dd = ev dd 5.5 v, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v lc0 voltage v lc0 c1 to c4 = 0.47 f note 3 v dd v v lc1 voltage v lc1 c1 to c4 = 0.47 f note 3 2/3 v lc0 ? 0.1 2/3 v lc0 2/3 v lc0 +0.1 v v lc2 voltage v lc2 c1 to c4 = 0.47 f note 3 1/3 v lc0 ? 0.1 1/3 v lc0 1/3 v lc0 +0.1 v capacitor split wait time note 1 t vawait 100 ms lcd output resistor note 2 (common) r odc i o = 5 a 40 k lcd output resistor note 2 (segment) r ocs i o = 1 a 200 k notes 1. this is the wait time from when voltage bucking is started (vlcon = 1) until display is enabled (lcdon = 1). 2. the output resistor is a resistor connected between one of the v lc0 , v lc1 , v lc2 and v ss pins, and either of the seg and com pins. 3. this is a capacitor that is connected between voltage pins used to drive the lcd. c1: a capacitor connected between caph and capl c2: a capacitor connected between v lc0 and gnd c3: a capacitor connected between v lc1 and gnd c4: a capacitor connected between v lc2 and gnd c1 = c2 = c3 = c4 = 0.47 pf 30 %
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 929 jun 20, 2011 poc circuit characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit v por 1.52 1.61 1.70 v detection voltage v pdr 1.5 1.59 1.68 v power supply voltage rise inclination t pth change inclination of v dd : 0 v v por 0.5 v/ms minimum pulse width t pw when the voltage drops 200 s detection delay time 200 s poc circuit timing supply voltage (v dd ) time detection voltage v por (min.) detection voltage v por (typ.) detection voltage v por (max.) detection voltage v pdr (min.) detection voltage v pdr (typ.) detection voltage v pdr (max.) t pth t pw
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 930 jun 20, 2011 supply voltage rise time (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit maximum time to rise to 1.8 v (v dd (min.)) note (v dd : 0 v 1.8 v) t pup1 lvi default start function stopped is set (lvioff (option byte) = 1), when reset input is not used 3.6 ms maximum time to rise to 1.8 v (v dd (min.)) note (releasing reset input v dd : 1.8 v) t pup2 lvi default start function stopped is set (lvioff (option byte) = 1), when reset input is used 1.88 ms note make sure to raise the power s upply in a shorter time than this. supply voltage rise time timing ? when reset pin input is not used ? when reset pin input is used (when external reset is released by the reset pin, after poc has been released) 1.8 v 0 v poc i nternal signal t pup1 supply voltage (v dd ) time 1.8 v t pup2 0 v poc i nternal signal reset pin internal reset signal supply voltage (v dd ) time
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 931 jun 20, 2011 lvi circuit characteristics (t a = ? 40 to +85 c, v pdr v dd = ev dd 5.5 v, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v lvi0 4.12 4.22 4.32 v v lvi1 3.97 4.07 4.17 v v lvi2 3.82 3.92 4.02 v v lvi3 3.66 3.76 3.86 v v lvi4 3.51 3.61 3.71 v v lvi5 3.35 3.45 3.55 v v lvi6 3.20 3.30 3.40 v v lvi7 3.05 3.15 3.25 v v lvi8 2.89 2.99 3.09 v v lvi9 2.74 2.84 2.94 v v lvi10 2.58 2.68 2.78 v v lvi11 2.43 2.53 2.63 v v lvi12 2.28 2.38 2.48 v v lvi13 2.12 2.22 2.32 v v lvi14 1.97 2.07 2.17 v supply voltage level v lvi15 1.81 1.91 2.01 v external input pin note 1 v exlvi exlvi < v dd , 1.8 v v dd 5.5 v 1.11 1.21 1.31 v detection voltage power supply voltage on power application v puplvi when lvi default start function enabled is set 1.87 2.07 2.27 v minimum pulse width t lw 200 s detection delay time 200 s operation stabilization wait time note 2 t lwait 10 s notes 1. the exlvi/p120/intp0 pin is used. 2. time required from setting bit 7 (lvion) of the low- voltage detection register (lvim) to 1 to operation stabilization remark v lvi (n ? 1) > v lvin : n = 1 to 15 lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lw t lwait lvion 1
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 932 jun 20, 2011 data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.5 note 5.5 v note the value depends on the poc detection voltage. when the voltage drops, t he data is retained until a poc reset is effected, but data is not retai ned when a poc reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode
78k0r/lx3 chapter 31 electrical specifications r01uh0004ej0501 rev.5.01 933 jun 20, 2011 flash memory programming characteristics (t a = ? 40 to +85 c, 1.8 v v dd = ev dd 5.5 v, v ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v dd supply current i dd typ. = 10 mhz, max. = 20 mhz 6 20 ma when a flash memory programmer is used, and the libraries provided by renesas electronics are used retention: 15 years 1000 times number of rewrites per chip c erwr 1 erase + 1 write after erase = 1 rewrite note when the eeprom emulation libraries provided by renesas electronics are used retention :5 years 10000 times note when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite.
78k0r/lx3 chapter 32 package drawings r01uh0004ej0501 rev.5.01 934 jun 20, 2011 chapter 32 package drawings 32.1 78k0r/lf3 ? pd78f1500agc-gad-ax, 78f1501agc-g ad-ax, 78f1502agc-gad-ax, 78f1510agc-gad-ax, 78f1512agc-gad-ax s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 14.00 0.20 14.00 0.20 17.20 0.20 17.20 0.20 1.70 max. 0.125 0.075 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 0.825 0.825 l lp l1 0.80 0.886 0.15 1.60 0.20 p80gc-65-gad 3 + 5 ? 3 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end 80-pin plastic lqfp (14x14) 0.30 b 20 40 80 21 41 60 1 + 0.08 ? 0.04 61
78k0r/lx3 chapter 32 package drawings r01uh0004ej0501 rev.5.01 935 jun 20, 2011 ? pd78f1500agk-gak-ax, 78f1501agk-g ak-ax, 78f1502agk-gak-ax, 78f1510agk-gak-ax, 78f1512agk-gak-ax s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 0.20 12.00 0.20 14.00 0.20 14.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p80gk-50-gak 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.20 b 20 40 1 80 21 41 61 60 80-pin plastic lqfp (fine pitch) (12x12) + 0.07 ? 0.03
78k0r/lx3 chapter 32 package drawings r01uh0004ej0501 rev.5.01 936 jun 20, 2011 32.2 78k0r/lg3 ? pd78f1503agc-ueu-ax, 78f1504agc-u eu-ax, 78f1505agc-ueu-ax, 78f1513agc-ueu-ax, 78f1515agc-ueu-ax 100-pin plastic lqfp (fine pitch) (14x14) s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 (unit:mm) item dimensions d e hd he a a1 a2 a3 14.00 0.20 14.00 0.20 16.00 0.20 16.00 0.20 1.60 max. 0.10 0.05 1.40 + + + 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.00 1.00 l lp l1 0.50 0.60 0.15 1.00 0.20 p100gc-50-ueu-1 3 3 5 detail of lead end 0.20 0.07 0.075 0.025 0.03 b 25 50 1 100 26 51 75 76
78k0r/lx3 chapter 32 package drawings r01uh0004ej0501 rev.5.01 937 jun 20, 2011 32.3 78k0r/lh3 ? pd78f1506agf-gat-ax, 78f1507agf-g at-ax, 78f1508agf-gat-ax, 78f1516agf-gat-ax, 78f1518agf-gat-ax s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 (unit:mm) item dimensions d e hd he a a1 a2 a3 20.00 0.20 14.00 0.20 22.00 0.20 16.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 0.75 0.75 l lp l1 0.50 0.60 0.15 1.00 0.20 p128gf-50-gat detail of lead end b 38 64 1 128 39 65 102 103 128-pin plastic lqfp (fine pitch) (14x20) note each lead centerline is located within 0.08 mm of its true position at maximum material condition. 0.20 + 0.07 ? 0.03 3 + 5 ? 3 + 0.075 ? 0.025
78k0r/lx3 chapter 33 recommended soldering conditions r01uh0004ej0501 rev.5.01 938 jun 20, 2011 chapter 33 recommended soldering conditions these products should be soldered and mount ed under the following recommended conditions. for soldering methods and conditions other than those re commended below, please contact a renesas electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http:// www.renesas.com/prod/package/manual/index.html) table 33-1. surface mounting type soldering cond itions (1/2) (1) 80-pin plastic lqfp (fine pitch) (12 12) pd78f1500agk-gak-ax, 78f1501agk -gak-ax, 78f1502agk-gak-ax, 78f1510agk-gak-ax, 78f1512agk-gak-ax 100-pin plastic lqfp (fine pitch) (14x14) pd78f1503agc-ueu-ax, 78f1504agc-u eu-ax, 78f1505agc-ueu-ax, 78f1513agc-ueu-ax, 78f1515agc-ueu-ax 128-pin plastic lqfp (fine pitch) (14x20) pd78f1506agf-gat-ax, 78f1507agf-g at-ax, 78f1508agf-gat-ax, 78f1516agf-gat-ax, 78f1518agf-gat-ax soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) ir60-107-3 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution the 78k0r/lx3 microcontroller h as an on-chip debug function, whic h is provided for development and evaluation. do not use the on-chip debug functi on in products designate d for mass production, because the guaranteed number of re writable times of the flash memo ry may be exceeded when this function is used, and product relia bility therefore cannot be guarant eed. renesas electronics is not liable for problems occurring when th e on-chip debug function is used.
78k0r/lx3 chapter 33 recommended soldering conditions r01uh0004ej0501 rev.5.01 939 jun 20, 2011 table 33-1. surface mounting type soldering cond itions (2/2) (2) 80-pin plastic lqfp (14 14) pd78f1500agc-gad-ax, 78f1501agc-g ad-ax, 78f1502agc-gad-ax, 78f1510agc-gad-ax, 78f1512agc-gad-ax soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) ir60-107-3 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125c for 10 to 72 hours) ws60-107-1 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution the 78k0r/lx3 microcontroller h as an on-chip debug function, whic h is provided for development and evaluation. do not use the on-chip debug functi on in products designate d for mass production, because the guaranteed number of re writable times of the flash memo ry may be exceeded when this function is used, and product relia bility therefore cannot be guarant eed. renesas electronics is not liable for problems occurring when th e on-chip debug function is used.
78k0r/lx3 appendix a development tools r01uh0004ej0501 rev.5.01 940 jun 20, 2011 appendix a development tools the following development tools are available for the development of systems that employ the 78k0r/lx3 microcontrollers. figure a-1 shows the developm ent tool configuration.
78k0r/lx3 appendix a development tools r01uh0004ej0501 rev.5.01 941 jun 20, 2011 figure a-1. development tool configuration (1/2) (1) when using the in-circu it emulator qb-78k0rlx3 language processing software ? assembler package ? c compiler package ? device file note 1 debugging software ? integrated debugger note 3 ? system simulator note 4 host machine (pc or ews) usb interface cable note 3 qb-78k0rlx3 note 3 target system flash memory programmer note 3 ? software package ? project manager software package control software (windows only) note 2 power supply unit target connector emulation probe conversion adapter on-board programming off-board programming flash memory write adapter 78k0r/lx3 microcontrollers notes 1. download the device file for 78k0r/lx3 microcont rollers (df781508) from the download site for development tools (http://www2.renesa s.com/micro/en/ods/index.html). 2. the project manager pm+ is in cluded in the assembler package. the pm+ is only used for windows tm . 3. in-circuit emulator qb-78k0rlx3 is supplied with integrated debugger id78k0r-qb, on-chip debug emulator with programming function qb-mini2, and usb interface cable. any other products are sold separately. 4. sm+ for 78k0r (instruction simulation version) is included in the software package. sm+ for 78k0r/lx3 (instruction + peripheral simulation version) note 5 is not included. 5. under development
78k0r/lx3 appendix a development tools r01uh0004ej0501 rev.5.01 942 jun 20, 2011 figure a-1. development tool configuration (2/2) (2) when using the on-chip debug emulat or with programming function qb-mini2 host machine (pc or ews) usb interface cable note 3 qb-mini2 note 3 connection cable (16-pin cable) note 3 target connector target system ? software package ? project manager software package control software (windows only) note 2 language processing software ? assembler package ? c compiler package ? device file note1 debugging software ? integrated debugger note 1 ? system simulator note 4 notes 1. download the device file for 78k0r/lx3 microc ontrollers (df781508) and the integrated debugger id78k0r-qb from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). 2. the project manager pm+ is in cluded in the assembler package. the pm+ is only used for windows. 3. on-chip debug emulator qb-mini2 is supplied with u sb interface cable, connection cables (10-pin cable and 16-pin cable), and 78k0-ocd board. any other produc ts are sold separately. in addition, download the software for operating the qb-mini2 fr om the download site for minicube2 (http://www2.renesas.com/micro/en/developmen t/asia/minicube2/minicube2.html). 4. sm+ for 78k0r (instruction simulation version) is included in the software package. sm+ for 78k0r/lx3 (instruction + peripheral simulation version) note 5 is not included. 5. under development
78k0r/lx3 appendix a development tools r01uh0004ej0501 rev.5.01 943 jun 20, 2011 a.1 software package sp78k0r 78k0r microcontroller software package development tools (software) common to t he 78k0r microcontrollers are combined in this package. a.2 language processing software ra78k0r assembler package this assembler converts programs written in mnemonics into object codes executable with a microcontroller. this assembler is also provided with functi ons capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with a device file (df781508). this assembler package is a dos-based app lication. it can also be used in windows, however, by using the project manager (i ncluded in assembler package) on windows. cc78k0r c compiler package this compiler converts programs written in c language into object codes executable with a microcontroller. this compiler should be used in combination with an assembler package and device file. this c compiler package is a dos-based applic ation. it can also be used in windows, however, by using the project manager (i ncluded in assembler package) on windows. df781508 note device file this file contains information peculiar to the device. this device file should be used in comb ination with a tool (ra78k0r, cc78k0r, id78k0r-qb, and system simulator (sm+ for 78k0r and sm+ for 78k0r/lx3)). the corresponding os and host machine di ffer depending on the tool to be used. note the df781508 can be used in common with the ra 78k0r, cc78k0r, id78k0r-qb, and system simulator. download the df781508 from the download site for development tools (http://www2.renesas.com/micro/en/ods/).
78k0r/lx3 appendix a development tools r01uh0004ej0501 rev.5.01 944 jun 20, 2011 a.3 flash memory programming tools a.3.1 when using flash memory programmer pg-fp5 and fl-pr5 pg-fp5, fl-pr5 flash memory programmer flash memory programmer dedica ted to microcontrollers with on-chip flash memory. fa-78f1502gc-gad-rx, fa-78f1502gk-gak-rx, fa-78f1505gc-ueu-rx, fa-78f1508gf-gat-rx flash memory programming adapter flash memory programming adap ter used connected to the flash memory programmer for use. remarks 1. fl-pr5, fa-78f1502gc-gad-rx, fa-78f1502g k-gak-rx, fa-78f1505gc-ueu-rx, and fa- 78f1508gf-gat-rx are products of na ito densei machida mfg. co., ltd. tel: +81-42-750-4172 naito densei machida mfg. co., ltd. 2. use the latest version of the flash memory programming adapter. a.3.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this is a flash memory programmer dedicat ed to microcontrollers with on-chip flash memory. it is available also as on-chip debug emulator which serves to debug hardware and software when developing application systems using the 78k0r/lx3 microcontrollers. when using this as flash memory programmer, it should be used in combination with a connection cable (16-pin cable) and a usb interface cable that is used to connect the host machine. remark download the software for operating the qb-mi ni2 from the download site for minicube2 (http://www2.renesas.com/micro/en/developm ent/asia/minicube2/minicube2.html).
78k0r/lx3 appendix a development tools r01uh0004ej0501 rev.5.01 945 jun 20, 2011 a.4 debugging tools (hardware) a.4.1 when using in-circu it emulator qb-78k0rlx3 qb-78k0rlx3 in-circuit emulator this in-circuit emulator serves to debug har dware and software when developing application systems using the 78k0r/lx3 microcontrollers. it supports to the integrated debugger (id78k0r- qb). this emulator should be used in combinat ion with a power supply unit and emulation probe, and the usb is used to connect this emulator to the host machine. qb-144-ca-01 check pin adapter this check pin adapter is used in waveform monitoring using the oscilloscope, etc. qb-144-ep-02s emulation probe this emulation probe is flexible type and used to connect the in-circuit emulator and target system. qb-xxxx-ea-xxx note exchange adapter this exchange adapter is used to perform pin conver sion from the in-circuit emulator to target connector. qb-xxxx-ys-xxx note space adapter this space adapter is used to adjust the height bet ween the target system and in-circuit emulator. qb-xxxx-yq-xxx note yq connector this yq connector is used to connect the target connector and exchange adapter. qb-xxxx-hq-xxx note mount adapter this mount adapter is used to mount the target device with socket. qb-xxxx-nq-xxx note target connector this target connector is used to mount on the target system. note the part numbers of the exchange adapter, space adapter, yq connector, mount adapter, and target connector and the packages of the target device are described below. package exchange adapter space adapter yq connector mount adapter target connector 80-pin plastic lqfp (gc-gad type) qb-80gc- ea-09t qb-80gc- ys-01t qb-80gc- yq-01t qb-80gc- hq-01t qb-80gc- nq-01t 78k0r/lf3 80-pin plastic lqfp (gk-gak type) qb-80gk- ea-08t qb-80gk- ys-01t qb-80gk- yq-01t qb-80gk- hq-01t qb-80gk- nq-01t 78k0r/lg3 100-pin plastic lqfp (gc-ueu type) qb-100gc- ea-08t qb-100gc- ys-01t qb-100gc- yq-01t qb-100gc- hq-01t qb-100gc- nq-01t 78k0r/lh3 128-pin plastic lqfp (gf-gat type) qb-128gf- ea-01t qb-128gf- ys-01t qb-128gf- yq-01t qb-128gf- hq-01t qb-128gf- nq-01t remark 1. the qb-78k0rlx3 is supplied with an integrated debugger id78k0r-qb, usb interface cable, and on- chip debug emulator qb-mini2. when using the qb-mini2 download the software fo r operating the qb-mini2 from the download site for development tools (http://www2.re nesas.com/micro/en/ods/).
78k0r/lx3 appendix a development tools r01uh0004ej0501 rev.5.01 946 jun 20, 2011 remark 2. the packed contents differ depending on the part number, as follows. packed contents part number in-circuit emulator emulation probe exchange adapter yq connector target connector qb-78k0rlx3-zzz none qb-78k0rlx3-t80gc qb-80gk-ea-09t qb-80gc-yq-01t qb-80gc-nq-01t qb-78k0rlx3-t80gk qb-80gk-ea-08t qb-80gk-yq-01t qb-80gk-nq-01t qb-78k0rlx3-t100gc qb-100gc-ea-08t qb-100gc-yq-01t qb-100gc-nq-01t qb-78k0rlx3-t128gf qb-78k0rlx3 qb-144-ep-02s qb-128gf-ea-01t qb-128gf-yq-01t qb-128gf-nq-01t a.4.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this on-chip debug emulator serves to debug hardware and software when developing application systems using the 78k0r/lx3 microcon trollers. it is available also as flash memory programmer dedicated to microcontro llers with on-chip flash memory. when using this as on-chip debug emulator, it shou ld be used in combination with a connection cable (16-pin cable), and usb interface cable th at is used to connect the host machine. remark download the software for operating the qb-mi ni2 from the download site for minicube2 (http://www2.renesas.com/micro/en/developm ent/asia/minicube2/minicube2.html). a.5 debugging tools (software) id78k0r-qb integrated debugger note 1 this debugger supports the in-circuit emulat ors for the 78k0r microcontrollers. the id78k0r-qb is windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory di splay with the trace result. it should be used in combination with the device file (df781508). sm+ for 78k0r sm+ for 78k0r/lx3 note 2 system simulator system simulator is windows-based software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of system simulator allows the exec ution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development e fficiency and software quality. system simulator should be used in combination with the device file (df781508). the following two types of system simulators supporting the 78k0r/lx3 microcontrollers are available. ? sm+ for 78k0r (instruction simulation version) this can only simulate a cpu. it is included in the software package. ? sm+ for 78k0r/lx3 (instruction + peripheral simulation version) note 1 this can simulate a cpu and peripheral hardw are (ports, timers, serial interfaces, etc.). notes 1. download the id78k0r-qb from the download site for development tools (http://www2.renesas.com/micro/en/ods/). 2. under development
78k0r/lx3 appendix b register index r01uh0004ej0501 rev.5.01 947 jun 20, 2011 appendix b register index b.1 register index (in al phabetical order with respect to register names) a a/d converter mode register (adm) .............................................................................................. ............................. 391 a/d converter mode re gister 1 (adm1) ........................................................................................... ........................... 394 a/d port configuratio n register (adpc) ......................................................................................... ............. 193, 399, 429 alarm hour regist er (alarmwh) .................................................................................................. ............................. 359 alarm minute regist er (alarmwm) ................................................................................................ ........................... 359 alarm week regi ster (alarmww) .................................................................................................. ........................... 360 analog input channel specification re gister (ads).............................................................................. ........................ 398 analog reference voltage c ontrol regist er (advrc) .............................................................................. ............. 395, 435 b background event control register (bectl)...................................................................................... ......................... 839 bcd correction result register (bcdadj)........................................................................................ ........................... 854 c clock operation mode cont rol register (cmc) .................................................................................... ........................ 209 clock operation status c ontrol regist er (csc) .................................................................................. .......................... 211 clock output selection register 0 (cks0 )....................................................................................... ............................. 382 clock output selection register 1 (cks1 )....................................................................................... ............................. 382 d d/a conversion value setti ng register 0 (dacs0)................................................................................ ....................... 422 d/a conversion value setti ng register 1 (dacs1)................................................................................ ....................... 422 d/a conversion value setting register w0 (dacsw0) .............................................................................. .................. 422 d/a conversion value setting register w1 (dacsw1) .............................................................................. .................. 422 d/a converter mode register (dam) .............................................................................................. ............................. 421 day count regi ster (day) ....................................................................................................... .................................... 355 dma byte count r egister n (dbcn) ............................................................................................... .............................. 720 dma mode control r egister n (dmcn) ............................................................................................. ........................... 721 dma operation control register n (drcn )........................................................................................ ........................... 723 dma ram address regi ster n (dran).............................................................................................. .......................... 719 dma sfr address regi ster n (dsan).............................................................................................. ........................... 718 e 8-bit a/d conversion resu lt register (adcrh) ................................................................................... ................. 389, 397 external interrupt falling edg e enable regist er (e gn0) ......................................................................... ...................... 760 external interrupt falling edg e enable regist er (e gn1) ......................................................................... ...................... 760 external interrupt rising e dge enable regist er (e gp0) .......................................................................... ...................... 760 external interrupt rising e dge enable regist er (e gp1) .......................................................................... ...................... 760 h hour count regi ster (h our) ..................................................................................................... .................................. 354 i iica control regist er 0 ( iicctl0) .............................................................................................. .................................. 584
78k0r/lx3 appendix b register index r01uh0004ej0501 rev.5.01 948 jun 20, 2011 iica control regist er 1 (ii cclt1) .............................................................................................. .................................. 593 iica flag regist er (iicf) ...................................................................................................... ........................................ 591 iica high-level width setti ng register (iicwh) ................................................................................. ........................... 595 iica low-level width setti ng register (iicwl) .................................................................................. ............................ 595 iica shift regi ster ( iica) ..................................................................................................... ........................................ 581 iica status regi ster (iics) .................................................................................................... ...................................... 589 input switch contro l register (isc) ............................................................................................ ...........195, 283, 464, 674 interrupt mask flag re gister 0h (mk0h)......................................................................................... ............................. 752 interrupt mask flag re gister 0l (mk0l) ......................................................................................... .............................. 752 interrupt mask flag re gister 1h (mk1h)......................................................................................... ............................. 752 interrupt mask flag re gister 1l (mk1l) ......................................................................................... .............................. 752 interrupt mask flag re gister 2h (mk2h)......................................................................................... ............................. 752 interrupt mask flag re gister 2l (mk2l) ......................................................................................... .............................. 752 interrupt request flag register 0h (if0h)...................................................................................... ............................... 748 interrupt request flag register 0l (if 0l)...................................................................................... ................................ 748 interrupt request flag register 1h (if1h)...................................................................................... ............................... 748 interrupt request flag register 1l (if 1l)...................................................................................... ................................ 748 interrupt request flag register 2h (if2h)...................................................................................... ............................... 748 interrupt request flag register 2l (if 2l)...................................................................................... ................................ 748 k key return mode re gister (krm)................................................................................................. ................................ 772 l lcd boost level contro l register (vlcd) ........................................................................................ ............................ 670 lcd clock control r egister (l cdc0) ............................................................................................. .............................. 669 lcd display mode re gister (lcdm)............................................................................................... ............................. 667 lcd mode regi ster (l cdmd) ...................................................................................................... ............................... 667 low-voltage detection level select regist er (lvis)............................................................................. ......................... 808 low-voltage detecti on register (lvim).......................................................................................... .............................. 805 m minute count r egister (min) .................................................................................................... .................................... 354 month count regi ster (month) ................................................................................................... ............................... 357 multiplication/division control regi ster (mduc) ................................................................................ ........................... 713 multiplication/division data register a (mdah) ................................................................................. .......................... 710 multiplication/division data register a (mdal) ................................................................................. ........................... 710 multiplication/division data register b (mdbh) ................................................................................. .......................... 711 multiplication/division data register b (mdbl) ................................................................................. ........................... 711 multiplication/division data register c (mdch) ................................................................................. .......................... 712 multiplication/division data register c (m dcl)................................................................................. ........................... 712 n noise filter enable register 0 (nfen0)......................................................................................... ............................... 465 noise filter enable register 1 (nfen1)......................................................................................... ............................... 284 noise filter enable register 2 (nfen2)......................................................................................... ............................... 284 o operation speed mode c ontrol regist er (osmc) ................................................................................... ..................... 221
78k0r/lx3 appendix b register index r01uh0004ej0501 rev.5.01 949 jun 20, 2011 operational amplifier co ntrol regist er (oac) ................................................................................... ........................... 428 oscillation stabilization time c ounter status r egister (ostc).................................................................. ............ 212, 774 oscillation stabilization time select regi ster (osts) .......................................................................... ................. 214, 775 p peripheral enable register 0 (per 0)............................................................ 219, 262, 348, 390, 420, 427, 43 5, 447, 584 port function re gister (pfall) ................................................................................................. ........................... 194, 671 port input mode r egister 1 (pim1) .............................................................................................. ........................ 191, 466 port input mode r egister 7 (pim7) .............................................................................................. ........................ 191, 466 port mode regist er 0 (p m0) ..................................................................................................... ................................... 180 port mode regist er 1 (p m1) ..................................................................................................... ................... 180, 28 7, 468 port mode regist er 10 (p m10) ................................................................................................... ................................. 180 port mode regist er 11 (p m11) ................................................................................................... ................................. 180 port mode regist er 12 (p m12) ................................................................................................... ......................... 180, 809 port mode regist er 14 (p m14) ................................................................................................... ................................. 180 port mode regist er 15 (p m15) ................................................................................................... ................. 180, 40 0, 430 port mode regist er 2 (p m2) ..................................................................................................... ................... 180, 40 0, 430 port mode regist er 3 (p m3) ..................................................................................................... ............180, 287, 361, 384 port mode regist er 4 (p m4) ..................................................................................................... ................................... 180 port mode regist er 5 (p m5) ..................................................................................................... ................... 180, 28 7, 468 port mode regist er 6 (p m6) ..................................................................................................... ........................... 180, 595 port mode regist er 7 (p m7) ..................................................................................................... ........................... 180, 468 port mode regist er 8 (p m8) ..................................................................................................... ................... 180, 28 7, 468 port mode regist er 9 (p m9) ..................................................................................................... ................................... 180 port output mode re gister 1 (pom1) ............................................................................................. ..................... 192, 467 port output mode re gister 7 (pom7) ............................................................................................. ..................... 192, 467 port output mode re gister 8 (pom8) ............................................................................................. ..................... 192, 467 port regist er 0 (p0) ........................................................................................................... .......................................... 184 port regist er 1 (p1) ........................................................................................................... .......................................... 184 port register 10 (p10) ......................................................................................................... ........................................ 184 port register 11 (p11) ......................................................................................................... ........................................ 184 port register 12 (p12) ......................................................................................................... ........................................ 184 port register 13 (p13) ......................................................................................................... ........................................ 184 port register 14 (p14) ......................................................................................................... ........................................ 184 port register 15 (p15) ......................................................................................................... ........................................ 184 port regist er 2 (p2) ........................................................................................................... .......................................... 184 port regist er 3 (p3) ........................................................................................................... .......................................... 184 port regist er 4 (p4) ........................................................................................................... .......................................... 184 port regist er 5 (p5) ........................................................................................................... .......................................... 184 port regist er 6 (p6) ........................................................................................................... .......................................... 184 port regist er 7 (p7) ........................................................................................................... .......................................... 184 port regist er 8 (p8) ........................................................................................................... .......................................... 184 port regist er 9 (p9) ........................................................................................................... .......................................... 184 priority specification flag register 00h (pr00h) ............................................................................... .......................... 755 priority specification fl ag register 00l (pr 00l)............................................................................... ............................ 755 priority specification flag register 01h (pr01h) ............................................................................... .......................... 755 priority specification fl ag register 01l (pr 01l)............................................................................... ............................ 755
78k0r/lx3 appendix b register index r01uh0004ej0501 rev.5.01 950 jun 20, 2011 priority specification flag register 02h (pr02h) ............................................................................... .......................... 755 priority specification fl ag register 02l (pr 02l)............................................................................... ............................ 755 priority specification flag register 10h (pr10h) ............................................................................... .......................... 755 priority specification fl ag register 10l (pr 10l)............................................................................... ............................ 755 priority specification flag register 11h (pr11h) ............................................................................... .......................... 755 priority specification fl ag register 11l (pr 11l)............................................................................... ............................ 755 priority specification flag register 12h (pr12h) ............................................................................... .......................... 755 priority specification fl ag register 12l (pr 12l)............................................................................... ............................ 755 processor mode contro l register (pmc) .......................................................................................... ............................. 83 pull-up resistor opti on register 0 (pu0) ....................................................................................... ............................... 188 pull-up resistor opti on register 1 (pu1) ....................................................................................... ............................... 188 pull-up resistor opti on register 3 (pu3) ....................................................................................... ............................... 188 pull-up resistor opti on register 4 (pu4) ....................................................................................... ............................... 188 pull-up resistor opti on register 5 (pu5) ....................................................................................... ............................... 188 pull-up resistor opti on register 7 (pu7) ....................................................................................... ............................... 188 pull-up resistor opti on register 8 (pu8) ....................................................................................... ............................... 188 pull-up resistor opti on register 9 (pu9) ....................................................................................... ............................... 188 pull-up resistor opti on register 10 (pu 10) ..................................................................................... ............................. 188 pull-up resistor opti on register 12 (pu 12) ..................................................................................... ............................. 188 pull-up resistor opti on register 14 (pu 14) ..................................................................................... ............................. 188 r real-time counter contro l register 0 (rt cc0) ................................................................................... ......................... 348 real-time counter contro l register 1 (rt cc1) ................................................................................... ......................... 350 real-time counter contro l register 2 (rt cc2) ................................................................................... ......................... 352 regulator mode contro l register (rmc).......................................................................................... ............................ 827 reset control flag register (resf)............................................................................................. ................................. 797 s second count r egister (sec).................................................................................................... .................................. 353 segment enable regi ster (segen) ................................................................................................ ............................ 672 serial channel enable stat us register m (sem) .................................................................................. ........................ 458 serial channel start register m (ssm).......................................................................................... ............................... 459 serial channel stop register m (stm) ........................................................................................... .............................. 460 serial clock select register m (spsm) .......................................................................................... .............................. 447 serial communication operation setting register mn (scrmn) ..................................................................... .............. 451 serial data regi ster mn (sdrmn) ................................................................................................ ............................... 454 serial flag clear trigger register mn (sirmn) .................................................................................. ............................ 457 serial mode regist er mn (s mrmn) ................................................................................................ ............................. 449 serial output enable register m (soem)......................................................................................... ............................ 461 serial output level register m (solm) .......................................................................................... .............................. 463 serial output re gister m (som)................................................................................................. .................................. 462 serial status regi ster mn (ssrmn) .............................................................................................. ............................... 455 slave address r egister (sva) ................................................................................................... .................................. 581 sub-count regist er (rsu bc) ..................................................................................................... ................................. 353 successive approximati on register (sar) ........................................................................................ .......................... 388 system clock contro l register (ckc)............................................................................................ ............................... 216
78k0r/lx3 appendix b register index r01uh0004ej0501 rev.5.01 951 jun 20, 2011 t 10-bit a/d conversion resu lt register (adcr) ................................................................................... .................. 389, 397 timer channel enable stat us register m (tem) ................................................................................... ....................... 269 timer channel start register m (tsm)........................................................................................... .............................. 270 timer channel stop r egister m (ttm) ............................................................................................ ............................. 275 timer clock select register m (tpsm) ........................................................................................... ............................. 262 timer data regist er mn (tdrmn)................................................................................................. ............................... 260 timer input select register p (tisp) ........................................................................................... ................................. 276 timer mode register mn (tmrmn) ................................................................................................. ............................ 264 timer output enable re gister p (toep).......................................................................................... ............................. 278 timer output level r egister p (tolp)........................................................................................... ................................ 281 timer output mode re gister p (tomp) ............................................................................................ ............................ 282 timer output regi ster p (top) .................................................................................................. ................................... 279 timer status regi ster pq (tsrpq) ............................................................................................... ................................ 268 timer/counter regist er mn (tcrmn).............................................................................................. ............................. 258 12-bit a/d conversion resu lt register (adcr) ................................................................................... .................. 389, 396 20 mhz internal high-speed oscilla tion control regi ster (d scctl)............................................................... .............. 218 w watch error correcti on register (sub cud) ....................................................................................... ......................... 358 watchdog timer enable register (wdte).......................................................................................... .......................... 376 week count re gister (week) ..................................................................................................... ................................ 356 y year count regi ster ( year)..................................................................................................... ................................... 357
78k0r/lx3 appendix b register index r01uh0004ej0501 rev.5.01 952 jun 20, 2011 b.2 register index (in al phabetical order with respect to register symbol) a adcr: 12-bit a/d conversi on result regist er .................................................................................... .................. 389, 396 adcrh: 8-bit a/d conversi on result regist er.................................................................................... .................. 389, 397 adm: a/d converte r mode re gister............................................................................................... .............................. 391 adm1: a/d converter mode regi ster 1............................................................................................ ............................ 394 adpc: a/d port confi guration r egist er.......................................................................................... .............. 193, 399, 429 ads: analog input channel specificatio n regi ster ............................................................................... ........................ 398 advrc: analog reference voltage contro l regi ster ............................................................................... ............. 395, 435 alarmwh: alarm hour regi ster................................................................................................... .............................. 359 alarmwm: alarm minute r egister................................................................................................. ............................ 359 alarmww: alarm week register................................................................................................... ............................ 360 b bcdadj: bcd correcti on result regist er ......................................................................................... ........................... 854 bectl: background event control regist er ....................................................................................... ......................... 839 c ckc: system clock control re gister ............................................................................................. ............................... 216 cks0: clock output sele ction regi ster 0 ........................................................................................ ............................. 382 cks1: clock output sele ction regi ster 1 ........................................................................................ ............................. 382 cmc: clock operation m ode control register..................................................................................... ......................... 209 csc: clock operation stat us control register................................................................................... ........................... 211 d dacs0: d/a conversion va lue setting re gister 0 ................................................................................. ....................... 422 dacs1: d/a conversion va lue setting re gister 1 ................................................................................. ....................... 422 dacsw0: d/a conversion va lue setting re gister w0 ............................................................................... .................. 422 dacsw1: d/a conversion va lue setting re gister w1 ............................................................................... .................. 422 dam: d/a converte r mode re gister............................................................................................... .............................. 421 day: day coun t regi ster........................................................................................................ ..................................... 355 dbcn: dma byte c ount regist er n ................................................................................................ .............................. 720 dmcn: dma mode cont rol regist er n.............................................................................................. ............................ 721 dscctl: 20 mhz internal high-sp eed oscillation co ntrol re gister ............................................................... .............. 218 dran: dma ram addre ss register n ............................................................................................... .......................... 719 drcn: dma operation c ontrol regi ster n ......................................................................................... ........................... 723 dsan: dma sfr addre ss register n ............................................................................................... ........................... 718 e egn0: external interrupt fa lling edge enable r egist er .......................................................................... ...................... 760 egn1: external interrupt fa lling edge enable r egist er .......................................................................... ...................... 760 egp0: external interrupt ri sing edge enabl e regi ster ........................................................................... ...................... 760 egp1: external interrupt ri sing edge enabl e regi ster ........................................................................... ...................... 760 h hour: hour c ount regi ster ...................................................................................................... .................................. 354 i if0h: interrupt reques t flag regi ster 0h ....................................................................................... ............................... 748
78k0r/lx3 appendix b register index r01uh0004ej0501 rev.5.01 953 jun 20, 2011 if0l: interrupt reques t flag regi ster 0l ....................................................................................... ................................ 748 if1h: interrupt reques t flag regi ster 1h ....................................................................................... ............................... 748 if1l: interrupt reques t flag regi ster 1l ....................................................................................... ................................ 748 if2h: interrupt reques t flag regi ster 2h ....................................................................................... ............................... 748 if2l: interrupt reques t flag regi ster 2l ....................................................................................... ................................ 748 iica: iica shif t regi ster...................................................................................................... ......................................... 581 iicclt1: iica contro l register 1 ............................................................................................... .................................. 593 iicctl0: iica contro l register 0 ............................................................................................... .................................. 584 iicf: iica fl ag regi ster....................................................................................................... ......................................... 591 iics: iica stat us regi ster..................................................................................................... ....................................... 589 iicwh: iica high-level width setting register.................................................................................. ............................ 595 iicwl: iica low-level width setting register................................................................................... ............................. 595 isc: input switch control re gister............................................................................................. ............195, 283, 464, 674 k krm: key return mode re gister .................................................................................................. ................................ 772 l lcdc0: lcd clock control re gister.............................................................................................. ............................... 669 lcdm: lcd displa y mode re gister ................................................................................................ ............................. 667 lcdmd: lcd m ode regi ster ....................................................................................................... ............................... 667 lvim: low-voltage de tection r egist er ........................................................................................... .............................. 805 lvis: low-voltage detection level select regi ster .............................................................................. ......................... 808 m mdah: multiplication/divi sion data regi ster a.................................................................................. ........................... 710 mdal: multiplication/divi sion data regi ster a .................................................................................. ........................... 710 mdbh: multiplication/divi sion data regi ster b.................................................................................. ........................... 711 mdbl: multiplication/divi sion data regi ster b .................................................................................. ........................... 711 mdch: multiplication/divi sion data regi ster c .................................................................................. .......................... 712 mdcl: multiplication/divi sion data regi ster c .................................................................................. ........................... 712 mduc: multiplication/divi sion control register ................................................................................. ........................... 713 min: minute co unt regi ster ..................................................................................................... .................................... 354 mk0h: interrupt mask flag regist er 0h .......................................................................................... ............................. 752 mk0l: interrupt mask flag regist er 0l .......................................................................................... .............................. 752 mk1h: interrupt mask flag regist er 1h .......................................................................................... ............................. 752 mk1l: interrupt mask flag regist er 1l .......................................................................................... .............................. 752 mk2h: interrupt mask flag regist er 2h .......................................................................................... ............................. 752 mk2l: interrupt mask flag regist er 2l .......................................................................................... .............................. 752 month: month c ount register .................................................................................................... ............................... 357 n nfen0: noise filter enable regi ster 0 .......................................................................................... ............................... 465 nfen1: noise filter enable regi ster 1 .......................................................................................... ............................... 284 nfen2: noise filter enable regi ster 2 .......................................................................................... ............................... 284 o oac: operational amplif ier control regist er.................................................................................... ............................ 428 osmc: operation speed m ode control register .................................................................................... ..................... 221
78k0r/lx3 appendix b register index r01uh0004ej0501 rev.5.01 954 jun 20, 2011 ostc: oscillation stabilization ti me counter stat us regi ster ................................................................... ............ 212, 774 osts: oscillation stabilizatio n time select register ........................................................................... ................. 214, 775 p p0: port r egister 0 ............................................................................................................ .......................................... 184 p1: port r egister 1 ............................................................................................................ .......................................... 184 p2: port r egister 2 ............................................................................................................ .......................................... 184 p3: port r egister 3 ............................................................................................................ .......................................... 184 p4: port r egister 4 ............................................................................................................ .......................................... 184 p5: port r egister 5 ............................................................................................................ .......................................... 184 p6: port r egister 6 ............................................................................................................ .......................................... 184 p7: port r egister 7 ............................................................................................................ .......................................... 184 p8: port r egister 8 ............................................................................................................ .......................................... 184 p9: port r egister 9 ............................................................................................................ .......................................... 184 p10: port r egister 10 .......................................................................................................... ........................................ 184 p11: port r egister 11 .......................................................................................................... ........................................ 184 p12: port r egister 12 .......................................................................................................... ........................................ 184 p13: port r egister 13 .......................................................................................................... ........................................ 184 p14: port r egister 14 .......................................................................................................... ........................................ 184 p15: port r egister 15 .......................................................................................................... ........................................ 184 per0: peripheral enable register 0 .............................................................219, 26 2, 348, 390, 420, 427, 43 5, 447, 584 pfall: port f unction re gister .................................................................................................. ........................... 194, 671 pim1: port input mode regist er 1............................................................................................... ......................... 191, 466 pim7: port input mode regist er 7............................................................................................... ......................... 191, 466 pm0: port mode register 0 ...................................................................................................... ................................... 180 pm1: port mode register 1 ...................................................................................................... ................... 180, 28 7, 468 pm2: port mode register 2 ...................................................................................................... ................... 180, 40 0, 430 pm3: port mode register 3 ...................................................................................................... ............180, 287, 361, 384 pm4: port mode register 4 ...................................................................................................... ................................... 180 pm5: port mode register 5 ...................................................................................................... ................... 180, 28 7, 468 pm6: port mode register 6 ...................................................................................................... ........................... 180, 595 pm7: port mode register 7 ...................................................................................................... ........................... 180, 468 pm8: port mode register 8 ...................................................................................................... ................... 180, 28 7, 468 pm9: port mode register 9 ...................................................................................................... ................................... 180 pm10: port mode register 10 .................................................................................................... ................................. 180 pm11: port mode register 11 .................................................................................................... ................................. 180 pm12: port mode register 12 .................................................................................................... ......................... 180, 809 pm14: port mode register 14 .................................................................................................... ................................. 180 pm15: port mode register 15 .................................................................................................... ................. 180, 40 0, 430 pmc: processor mode control r egist er........................................................................................... .............................. 83 pom1: port output mode regist er 1.............................................................................................. ...................... 192, 467 pom7: port output mode regist er 7.............................................................................................. ...................... 192, 467 pom8: port output mode regist er 8.............................................................................................. ...................... 192, 467 pr00h: priority specificat ion flag regi ster 00h................................................................................ ........................... 755 pr00l: priority specific ation flag re gister 00l ................................................................................ ............................ 755 pr01h: priority specificat ion flag regi ster 01h................................................................................ ........................... 755 pr01l: priority specific ation flag re gister 01l ................................................................................ ............................ 755
78k0r/lx3 appendix b register index r01uh0004ej0501 rev.5.01 955 jun 20, 2011 pr02h: priority specificat ion flag regi ster 02h................................................................................ ........................... 755 pr02l: priority specific ation flag re gister 02l ................................................................................ ............................ 755 pr10h: priority specificat ion flag regi ster 10h................................................................................ ........................... 755 pr10l: priority specific ation flag re gister 10l ................................................................................ ............................ 755 pr11h: priority specificat ion flag regi ster 11h................................................................................ ........................... 755 pr11l: priority specific ation flag re gister 11l ................................................................................ ............................ 755 pr12h: priority specificat ion flag regi ster 12h................................................................................ ........................... 755 pr12l: priority specific ation flag re gister 12l ................................................................................ ............................ 755 pu0: pull-up resistor option regi ster 0........................................................................................ ................................ 188 pu1: pull-up resistor option regi ster 1........................................................................................ ................................ 188 pu3: pull-up resistor option regi ster 3........................................................................................ ................................ 188 pu4: pull-up resistor option regi ster 4........................................................................................ ................................ 188 pu5: pull-up resistor option regi ster 5........................................................................................ ................................ 188 pu7: pull-up resistor option regi ster 7........................................................................................ ................................ 188 pu8: pull-up resistor option regi ster 8........................................................................................ ................................ 188 pu9: pull-up resistor option regi ster 9........................................................................................ ................................ 188 pu10: pull-up resistor option regi ster 10...................................................................................... .............................. 188 pu12: pull-up resistor option regi ster 12...................................................................................... .............................. 188 pu14: pull-up resistor option regi ster 14...................................................................................... .............................. 188 r resf: reset contro l flag r egister .............................................................................................. ................................. 797 rmc: regulator mode control r egist er ........................................................................................... ............................ 827 rsubc : sub-c ount regi ster ..................................................................................................... ................................. 353 rtcc0: real-time counter control regi ster 0 .................................................................................... ......................... 348 rtcc1: real-time counter control regi ster 1 .................................................................................... ......................... 350 rtcc2: real-time counter control regi ster 2 .................................................................................... ......................... 352 s sar :successive approx imation re gister ......................................................................................... .......................... 388 scrmn: serial communication operation setting register mn ...................................................................... .............. 451 sdrmn: serial dat a regist er mn................................................................................................. ................................ 454 sec : second c ount regi ster .................................................................................................... .................................. 353 segen: segment ena ble regi ster................................................................................................. ............................. 672 sem: serial channel enabl e status r egister m................................................................................... ......................... 458 sirmn: serial flag clea r trigger r egister mn................................................................................... ............................. 457 smrmn: serial m ode regist er mn ................................................................................................. ............................. 449 soem: serial output en able regi ster m .......................................................................................... ............................ 461 solm: serial output level regi ster m........................................................................................... ............................... 463 som: serial out put regist er m .................................................................................................. .................................. 462 spsm: serial clock se lect register m........................................................................................... ............................... 447 ssm: serial channel start register m ........................................................................................... ............................... 459 ssrmn: serial stat us register mn ............................................................................................... ............................... 455 stm: serial channel stop regi ster m ............................................................................................ .............................. 460 subcud: watch error correction register........................................................................................ .......................... 358 sva: slave addr ess regi ster .................................................................................................... .................................. 581
78k0r/lx3 appendix b register index r01uh0004ej0501 rev.5.01 956 jun 20, 2011 t tcrmn: timer/count er register mn ............................................................................................... ............................. 258 tdrmn: timer dat a regist er mn .................................................................................................. ............................... 260 tem: timer channel enabl e status r egister m .................................................................................... ........................ 269 tisp: timer input se lect register p............................................................................................ .................................. 276 tmrmn: timer m ode regist er mn.................................................................................................. ............................. 264 toep: timer output enable regi ster p ........................................................................................... ............................. 278 tolp: timer output le vel register p ............................................................................................ ................................ 281 tomp:timer output mode regist er p .............................................................................................. ............................ 282 top: timer output register p ................................................................................................... ................................... 279 tpsm: timer clock se lect register m............................................................................................ .............................. 262 tsm: timer channel start register m ............................................................................................ .............................. 270 tsrpq: timer stat us regist er pq................................................................................................ ................................. 268 ttm: timer channel stop regist er m............................................................................................. .............................. 275 v vlcd: lcd boost leve l control regist er......................................................................................... ............................. 670 w wdte: watchdog timer enable r egist er ........................................................................................... .......................... 376 week : week c ount regi ster ..................................................................................................... ................................. 356 y year: year count regi ster ...................................................................................................... ................................... 357
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 957 jun 20, 2011 appendix c list of cautions this appendix lists the cautions described in this document. ?classification (hard/soft)? in the table is as follows. hard: cautions for microcontroller internal/external hardware soft: cautions for software such as register settings or programs (1/39) chapter classification function details of function cautions page on-chip debug function the 78k0r/lx3 microcontrollers have an on -chip debug function, which is provided for development and evaluation. do not us e the on-chip debug function in products designated for mass production, because th e guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. p.3 ? pp.4, 5 ? av ss , v ss make av ss the same potential as v ss . 7, 8, 10,11 pp.4, 5 ? chapter 1 hard outline regc connect the regc pin to v ss via a capacitor (0.47 to 1 f). 7, 8, 10,11 p00/caph, p01/capl, p02/v lc3 to use p00/caph, p01/capl, and p02/v lc3 as a general-purpose port, set bit 5 (mdset1) and bit 4 (mdset0) of lcd mode register (lcdmd) to ?0?, which is the same as their default status setting. p.43 ? p10/sck20/ scl20, p11/si20/rxd2/ sda20/intp6 to use p10/sck20/scl20 and p11/si20/rxd2/sda20/intp6 as a general-purpose port, note the serial array unit 1 setting. fo r details, refer to table 14-9 relationship between register settings and pins (channel 0 of unit 1: csi20, uart2 reception, iic20). p.45 ? p12/to02/so20 /txd2 to use p12/to02/so20/txd2 as a general- purpose port, set bit 2 (to02) of timer output register 0 (to0) and bit 2 (toe02) of timer output enable register 0 (toe0) to ?0?, which is the same as their default st atus setting. and as a general-purpose port, note the serial array unit 1 setting. for deta ils of serial array unit 1 setting, refer to table 14-9 relationship between register settings and pins (channel 0 of unit 1: csi20, uart2 reception, iic20). p.45 ? p13/to04/so10 /txd1 to use p13/to04/so10/txd1 as a general- purpose port, set bit 4 (to04) of timer output register 0 (to0) and bit 4 (toe04) of timer output enable register 0 (toe0) to ?0?, which is the same as their default st atus setting. and as a general-purpose port, note the serial array unit 0 setting. for deta ils of serial array unit 0 setting, refer to table 14-7 relationship between register settings and pins (channel 2 of unit 0: csi10, uart1 transmission, iic10). p.45 ? p14/si10/rxd1/ sda10/intp4, p15/sck10/ scl10/intp7 to use p14/si10/rxd1/sda10/intp4 and p15/sck10/scl10/intp7 as a general- purpose port, note the serial array unit 0 se tting. for details, refer to table 14-7 relationship between register settings and pins (channel 2 of unit 0: csi10, uart1 transmission, iic10). p.45 ? chapter 2 soft pin functions p16/to05/ti05/ intp10 to use p16/to05/ti05/intp10 as a general-purpose port, set bit 5 (to05) of timer output register 0 (to0) and bit 5 (toe05) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting. p.45 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 958 jun 20, 2011 (2/39) chapter classification function details of function cautions page soft p20/ani0/amp0- to p27/ani7/anp2o are set in the digital input (general-purpose port) mode after release of reset. p.46 ? hard p20/ani0/amp0- to p27/ani7/anp2o when using at least one port of ports p 20/ani0/amp0- to p27/ani7/anp2o as a digital port, set av dd0 to the same potential as ev dd or v dd . p.46 ? p30/to00/ti03/ rtc1hz/intp1 to use p30/to00/ti03/rtc1hz/intp1 as a general-purpose port, set bit 5 (rcloe1) of real-time counter control regi ster 0 (rtcc0), bit 0 (to00) of timer output register 0 (to0) and bit 0 (toe00) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting. p.48 ? p31/to03/ti00/ rtcdiv/rtccl/ pclbuz1/intp2 to use p31/to03/ti00/rtcdiv/rtccl/pclbuz1/intp2 as a general-purpose port, set bit 4 (rcloe0) of real-time counter c ontrol register 0 (rtc c0), bit 6 (rcloe2) of real-time counter control register 2 (rtcc2 ), bit 3 (to03) of timer output register 0 (to0), bit 3 (toe03) of timer output enable register 0 (toe0) and bit 7 of clock output select register 1 (cks1) to ?0?, which is the same as their default status setting. p.48 ? p32/to01/ti01/ intp5/pclbuz0 to use p32/to01/ti01/intp5/pclbuz0 as a general-purpose port, set bit 1 (to01) of timer output register 0 (to0), bit 1 (toe01) of timer output enable register 0 (toe0) and bit 7 of clock output select regist er 0 (cks0) to ?0?, which is the same as their default status setting. p.48 ? soft p33/to07/ti07/ intp3, p34/to06/ti06/ intp8 to use p33/to07/ti07/intp3 and p34/to06/ti06/intp8 as a general-purpose port, set bit 7, 6 (to07, to06) of timer output register 0 (to0), and bit 7, 6 (toe07, toe06) of timer output enable register 0 (toe 0) to ?0?, which is the same as their default status setting. p.48 ? hard p40/tool0 the function of the p40/tool0 pin varies as described in (a) to (c) below. in the case of (b) or (c), make the specified connection. (a) in normal operation mode and when on-ch ip debugging is disabled (ocdenset = 0) by an option byte (000c3h) => use this pin as a port pin (p40). (b) in normal operation mode and when on-chip debugging is enabled (ocdenset = 1) by an option byte (000c3h) => connect this pin to v dd via an external resistor, an d always input a high level to the pin before reset release. (c) when on-chip debug function is used, or in write mode of flash memory programmer => use this pin as tool0. directly connect this pin to the on-chip debug emulator or a flash memory programmer, or pull it up by connecting it to v dd via an external resistor. p.49 ? p60/scl0, p61/sda0 when using p60/scl0 and p61/sda0 as a general-purpose port, stop the operation of serial interface iica. p.50 ? p75/sck01/kr5, p76/si01/kr6, p77/so01/kr7 to use p75/sck01/kr5, p76/si01/kr6, and p77/so01/kr7, as a general-purpose port, note the serial array unit 0 setting. fo r details, refer to table 14-6 relationship between register settings and pins (channel 1 of unit 0: csi01, uart0 reception). p.51 ? chapter 2 soft pin functions p80/sck00/ intp11, p81/rxd0/si00/ intp9, p82/so00/txd0 to use p80/sck00/intp11, p81/rxd0/si00/intp9, and p82/so00/txd0, as a general-purpose port, note the serial array uni t 0 setting. for details, refer to table 14-5 relationship between register settings and pins (channel 0 of unit 0: csi00, uart0 reception). p.53 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 959 jun 20, 2011 (3/39) chapter classification function details of function cautions page hard p110/ano0, p111/ano1 when using at least one port of p110/ano0 and p111/ano1 as a digital port, set av dd1 to the same potential as ev dd or v dd . p.54 ? p121 to p124 the function setting on p121 to p124 is available only once after the reset release. the port once set for connection to an oscillator cannot be used as an input port unless the reset is performed. p.55 ? soft p150/ani8/amp2+ to p152/ani10 and p157/ani15/av refm are set in the digital input (general-purpose port) mode after release of reset. p.57 ? p150/ani8/ amp2+ to p152/ani10 and p157/ani15/ av refm when using at least one port of p150/ani8/amp2+ to p152/ani10 and p157/ani15/av refm as a digital port, set av dd0 to the same potential as ev dd or v dd . p.57 ? chapter 2 hard pin functions regc keep the wiring length as short as poss ible for the broken-line part in the above figure. p.58 ? set pmc only once during the initial settings prior to operating the dma controller. rewriting pmc other than during the initial settings is prohibited. p.83 ? after setting pmc, wait for at least one instruction and access the mirror area. p.83 ? pmc: processor mode control register when the pd78f1500a, 78f1503a, and 78f1506a (flash memory size: 64 kb) are used, be sure to set bit 0 (maa) of this register to 0. p.83 ? pp.83, ? it is prohibited to use the general-purpose register (ffee0h to ffeffh) space for fetching instructions or as a stack area. 89, 90 internal data memory space while using the self-programming function, the area of ffe20h to ffeffh cannot be used as a stack memory. pp.83, 89 ? sfr: special function register area do not access addresses to which sfrs are not assigned. pp.84, 93 ? memory space 2nd sfr: extended special function register do not access addresses to which 2nd sfrs are not assigned. pp.84, 99 ? chapter 3 soft processor registers sp: stack pointer since reset signal generation makes the sp c ontents undefined, be sure to initialize the sp before using the stack. p.89 ? p00/caph, p01/capl, p02/v lc3 to use p00/caph, p01/capl, and p02/v lc3 as a general-purpose port, set bit 5 (mdset1) and bit 4 (mdset0) of lcd mode register (lcdmd) to ?0?, which is the same as their default status setting. p.130 ? p10/sck20/ scl20, p11/si20/rxd2/ sda20/intp6 to use p10/sck20/scl20 and p11/si20/rxd2/sda20/intp6 as a general-purpose port, note the serial array unit 1 setting. fo r details, refer to table 14-9 relationship between register settings and pins (channel 0 of unit 1: csi20, uart2 reception, iic20). p.133 ? p12/to02/so20/ txd2 to use p12/to02/so20/txd2 as a general- purpose port, set bit 2 (to02) of timer output register 0 (to0) and bit 2 (toe02) of timer output enable register 0 (toe0) to ?0?, which is the same as their default st atus setting. and as a general-purpose port, note the serial array unit 1 setting. for deta ils of serial array unit 1 setting, refer to table 14-9 relationship between register settings and pins (channel 0 of unit 1: csi20, uart2 reception, iic20). p.133 ? chapter 4 soft port functions p13/to04/so10 /txd1 to use p13/to04/so10/txd1 as a general-p urpose port, set bit 4 (to04) of timer output register 0 (to0) and bit 4 (toe04) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting. and as a general-purpose port, note the serial array unit 0 setting. for deta ils of serial array unit 0 setting, refer to table 14-7 relationship between register settings and pins (channel 2 of unit 0: csi10, uart1 transmission, iic10) p.133 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 960 jun 20, 2011 (4/39) chapter classification function details of function cautions page p14/si10/rxd1/ sda10/intp4, p15/sck10/scl 10/intp7 to use p14/si10/rxd1/sda10/intp4 and p15/sck10/scl10/intp7 as a general- purpose port, note the serial array unit 0 setting. for details, refer to table 14-7 relationship between register settings and pins (channel 2 of unit 0: csi10, uart1 transmission, iic10) p.133 ? soft p16/to05/ti05/ intp10 to use p16/to05/ti05/intp10 as a general-purpose port, set bit 5 (to05) of timer output register 0 (to0) and bit 5 (toe05) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting. p.133 ? hard port 2 make the av dd0 pin the same potential as the ev dd or v dd pin when port 2 is used as a digital port. p.138 ? p30/to00/ti03/ rtc1hz/intp1 to use p30/to00/ti03/rtc1hz/intp1 as a general-purpose port, set bit 5 (rcloe1) of real-time counter control regi ster 0 (rtcc0), bit 0 (to00) of timer output register 0 (to0) and bit 0 (toe00) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting. p.142 ? p31/to03/ti00/ rtcdiv/rtccl/ pclbuz1/intp2 to use p31/to03/ti00/rtcdiv/rtccl/pclbuz1/intp2 as a general-purpose port, set bit 4 (rcloe0) of real-time counter cont rol register 0 (rtcc0), bit 6 (rcloe2) of real-time counter control register 2 (rtcc2), bit 3 (to03) of timer output register 0 (to0), bit 3 (toe03) of timer output enabl e register 0 (toe0) and bit 7 of clock output select register 1 (cks1) to ?0?, which is the same as their default status setting. p.142 ? p32/to01/ti01/ intp5/pclbuz0 to use p32/to01/ti01/intp5/pclbuz0 as a general-purpose port, set bit 1 (to01) of timer output register 0 (to0), bit 1 (toe01) of timer out put enable register 0 (toe0) and bit 7 of clock output select register 0 (cks0) to ?0?, which is the same as their default status setting. p.142 ? soft p33/to07/ti07/ intp3, p34/to06/ti06/i ntp8 to use p33/to07/ti07/intp3 and p34/to06/ti06/intp8 as a general-purpose port, set bit 7, 6 (to07, to06) of timer output register 0 (to0), and bit 7, 6 (toe07, toe06) of timer output enable register 0 (toe0) to ?0?, which is the same as their default status setting. p.142 ? hard p40, p41 when a tool is connected, the p40 pin cannot be used as a port pin. when the on-chip debug function is used, p 41 pin can be used as follows by the mode setting on the debugger. ? 1-line mode: can be used as a port (p41). ? 2-line mode: used as a tool1 pin and cannot be used as a port (p41). p.144 ? p60/scl0, p61/sda0 when using p60/scl0 and p61/sda0 as a general-purpose port, stop the operation of serial interface iica. p.150 ? p75/sck01/kr5, p76/si01/kr6, p77/so01/kr7 to use p75/sck01/kr5, p76/si01/kr6 and p77/so01/kr7, as a general-purpose port, note the serial array unit 0 setting. for details, refer to table 14-6 relationship between register settings and pins (channel 1 of unit 0: csi01, uart0 reception). p.151 ? chapter 4 soft port functions p80/sck00/ intp11, p81/rxd0/si00/ intp9, p82/so00/txd0 to use p80/sck00/intp11, p81/rxd0/si00/intp9 and p82/so00/txd0, as a general-purpose port, note the serial array uni t 0 setting. for details, refer to table 14-5 relationship between register settings and pins (channel 0 of unit 0: csi00, uart0 reception). p.156 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 961 jun 20, 2011 (5/39) chapter classification function details of function cautions page port 11 make the av dd1 pin the same potential as the ev dd or v dd pin when port 11 is used as a digital port. p.167 ? p121 to p124 the function setting on p121 to p124 is available only once after the reset release. the port once set for connection to an oscillator cannot be used as an input port unless the reset is performed. p.168 ? hard port 15 make the av dd0 pin the same potential as the ev dd or v dd pin when port 15 is used as a digital port. p.176 ? port mode register (78k0r/lf3) be sure to set bits 3 to 7 of pm0, bits 6, 7 of pm1, bit 7 of pm2, bits 4 to 7 of pm3, bits 2 to 7 of pm4, bits 3 to 7 of pm9, bits 1 to 7 of pm10, bits 2 to 7 of pm11, bits 1 to 7 of pm12, and bits 0 to 6 of pm15 to 1. p.181 ? port mode register (78k0r/lg3) be sure to set bits 3 to 7 of pm0, bit 7 of pm1, bits 5 to 7 of pm3, bits 2 to 7 of pm4, bits 2 to 7 of pm6, bits 3 to 7 of pm8, bits 1 to 7 of pm10, bits 2 to 7 of pm11, bits 1 to 7 of pm12, and bits 3 to 6 of pm15 to 1. p.182 ? port mode register (78k0r/lh3) be sure to set bits 3 to 7 of pm0, bits 5 to 7 of pm3, bits 2 to 7 of pm4, bits 2 to 7 of pm6, bits 3 to 7 of pm10, bits 2 to 7 of pm11, bits 1 to 7 of pm12, and bits 3 to 6 of pm15 to 1. p.183 ? set the channel used for a/d conversion to the input mode by using port mode registers 2 and 15 (pm2, pm15). p.193 ? adpc: a/d port configuration register do not set the pin that is set by adpc as digital i/o by analog input channel specification register (ads). p.193 ? pfall: port function register for 78k0r/lf3, bits 3 and 7 must be set to 0. for 78k0r/lg3 and 78k0r/lh3, bit 7 must be set to 0. p.195 ? isc: input switch control register be sure to clear bits 5 to 7 to ?0?. p.196 ? chapter 4 soft port functions 1-bit manipulation instruction for port register n (pn) when a 1-bit manipulation instruction is ex ecuted on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. p.205 ? cmc can be written only once after reset re lease, by an 8-bit memory manipulation instruction. p.210 ? after reset release, set cmc before x1 or xt1 oscillation is started as set by the clock operation status control register (csc). p.210 ? be sure to set amph to 1 if the x1 clock oscillation frequency exceeds 10 mhz. p.210 ? chapter 5 soft clock generator cmc: clock operation mode control register to use cmc with its initial value (00h), be sure to set it to 00h after releasing reset in order to prevent malfunction when a program loop occurs. p.210 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 962 jun 20, 2011 (6/39) chapter classification function details of function cautions page hard cmc: clock operation mode control register the xt1 oscillator is designed as a lo w-gain circuit for achieving low-power consumption. note the following points when designing the xt1 oscillator. ? the pins and circuit board include parasitic capacitance. therefore, confirm that there are no problems by performing oscillation evaluation on the circuit board to be actually used. ? when low-consumption oscillation or super-low-consumption oscillation is selected, lower power consumption than when selecting normal oscillation can be achieved. however, in this case, the xt1 oscillation margin is reduced, so perform sufficient oscillation evaluation of the resonator to be used for xt1 oscillation before using the resonator. ? keep the wiring length between the xt1 and xt2 pins and resonator as short as possible and parasitic capacit ance and wire resistance as sm all as possible. this is particularly important when super-low-c onsumption oscillation (amphs1 = 1) is selected. ? configure the circuit board by using mate rial with little parasitic capacitance and wire resistance. ? place a ground pattern that has the same potential as v ss (if possible) around the xt1 oscillator. ? do not cross the signal lines between the xt1 and xt2 pins and the resonator with other signal lines. do not route the signal lines near a signal line through which a high fluctuating current flows. ? moisture absorption by the circui t board and condensation on the board in a highly humid environment may cause the impedance between the xt1 and xt2 pins to drop and disable oscillation. when using the circuit board in such an environment, prevent the circuit board fr om absorbing moisture by taking measures such as coat ing the circuit board. ? coat the surface of the circuit board by using material that does not generate capacitance or leakage be tween the xt1 and xt2 pins. pp.210, 211 ? after reset release, set the clock opera tion mode control register (cmc) before starting x1 oscillation as set by mstop or xt1 oscillation as set by xtstop. p.211 ? to start x1 oscillation as set by mstop, ch eck the oscillation stabilization time of the x1 clock by using the oscillation stabilization time counter status register (ostc). p.212 ? do not stop the clock selected for th e cpu peripheral hardware clock (f clk ) with the csc register. p.212 ? csc: clock operation status control register the setting of the flags of the register to stop clock oscillation (invalidate the external clock input) and the condition before clock oscillation is to be stopped are as follows. p.212 ? after the above time has elapsed, the bits are set to 1 in order from most8 and remain 1. p.213 ? chapter 5 soft clock generator ostc: oscillation stabilization time counter status register the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. in the following cases, set the oscillation stabilization time of osts to the value greater than the count value which is to be checked by the ostc register after the oscillation starts. ? if the x1 clock starts oscillation while the internal high-speed oscillation clock or subsystem clock is being us ed as the cpu clock. ? if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock with the x1 clock oscillating. (note, therefore, that onl y the status up to the oscilla tion stabilization time set by osts is set to ostc after the stop mode is released.) p.213 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 963 jun 20, 2011 (7/39) chapter classification function details of function cautions page hard ostc: oscillation stabilization time counter status register the x1 clock oscillation stabilization wait ti me does not include the time until clock oscillation starts (?a? below). p.213 ? to set the stop mode when the x1 clock is used as the cpu clock, set the osts register before executing the stop instruction. p.214 ? setting the oscillation stabilization time to 20 s or less is prohibited. p.214 ? to change the setting of the osts register, be sure to confirm that the counting operation of the ostc register has been completed. p.214 ? do not change the value of the osts register during the x1 clock oscillation stabilization time. p.214 ? soft the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. in the following cases, set the oscillation stabilization time of osts to the value greater than the count value which is to be checked by the ostc register after the oscillation starts. ? if the x1 clock starts oscillation while the internal high-speed oscillation clock or subsystem clock is being us ed as the cpu clock. ? if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock with the x1 clock oscillating. (note, therefore, that onl y the status up to the oscilla tion stabilization time set by osts is set to ostc after the stop mode is released.) p.214 ? hard osts: oscillation stabilization time select register the x1 clock oscillation stabilization wait ti me does not include the time until clock oscillation starts (?a? below). p.214 ? soft the clock set by css, mcm0, sdiv, and mdiv2 to mdiv0 is supplied to the cpu and peripheral hardware. if the cpu clock is changed, therefore, the clock supplied to peripheral hardware (except the real-time counter, timer array unit (when f sub /2, f sub /4, the valid edge of ti0mn input, or the valid edge of intrtci is selected as the count clock), clock output/buzzer output, and watchdog timer) is also changed at the same time. consequently, stop each peripheral function when changing the cpu/peripheral operati ng hardware clock. p.216 ? ckc: system clock control register if the peripheral hardware clock is used as the subsystem clock, the operations of the a/d converter and iica are not guaranteed. for the operating characteristics of the peripheral hardware, refer to the chapters describing the various peripheral hardware as well as chapter 31 electrical specifications. p.216 ? hard 20 mhz internal oscillation can only be used if v dd 2.7 v. p.218 ? set seldsc when 100 s have elapsed after having set dscon with v dd 2.7 v. p.218 ? dscctl: 20 mhz internal high-speed oscillation control register the internal high-speed oscillator must be operated (hiostop = 0) when dscon = 1. p. 218 ? write ?1? to fsel before the following two operations. ? changing the clock prior to dividing f clk to a clock other than f ih . ? operating the dma controller. p.221 ? the cpu waits (140.5 clock (f clk )) when ?1? is written to the fsel bit. interrupt requests issued during a wait will be suspended. however, counting the oscillation stabilization time of f x can continue even while the cpu is waiting. p.221 ? to increase f clk to 10 mhz or higher, set fsel to ?1?, then change f clk after two or more clocks have elapsed. p.221 ? chapter 5 soft clock generator osmc: operation speed mode control register confirm that the clock is operating at 10 mhz or less before setting fsel = 0. p.221 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 964 jun 20, 2011 (8/39) chapter classification function details of function cautions page to shift to stop mode while v dd 2.7 v, set fsel = 0 after setting f clk to 10 mhz or less. p.221 ? the halt mode current when operating on the subsystem clock can be reduced by setting rtclpc to 1. however, the clock cannot be supplied to peripheral functions except the real-time counter in the subsystem clock halt mode. set bit 7 (rtcen) of per0 to 1 and bits 0 to 6 of per0 to 0 before setting the subsystem clock halt mode. p.221 ? once flpc has been set from 0 to 1, setting it back to 0 from 1 other than by reset is prohibited. p.221 ? soft clock generator osmc: operation speed mode control register when setting fsel to ?1?, do so while rmc = 00h. when setting flpc to ?1?, do so while rmc = 5ah. p.221 ? chapter 5 hard x1/xt1 oscillator ? when using the x1 oscillator and xt1 oscillator, wire as follows in the area enclosed by the broken lines in the figures 5-10 and 5-11 to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. note that the xt1 oscillator is designed as a low-gain circuit for achieving low-power consumption. note the following points when designing the xt1 oscillator. ? the pins and circuit board include parasitic capacitance. therefore, confirm that there are no problems by performing oscillation evaluation on the circuit board to be actually used. ? when low-consumption oscillation or super -low-consumption oscillation is selected, lower power consumption than when selecting normal oscillation can be achieved. however, in this case, the xt1 oscillation margin is reduced, so perform sufficient oscillation evaluation of the resonator to be used for xt1 oscillation before using the resonator. ? keep the wiring length between the xt1 and xt2 pins and resonator as short as possible and parasitic capacitance and wire re sistance as small as possible. this is particularly important when super-low-c onsumption oscillation (amphs1 = 1) is selected. ? configure the circuit board by using mate rial with little parasitic capacitance and wire resistance. ? place a ground pattern that has the same potential as v ss (if possible) around the xt1 oscillator. ? do not cross the signal lines between the xt1 and xt2 pins and the resonator with other signal lines. do not route the signal lines near a signal line through which a high fluctuating current flows. ? moisture absorption by the circuit boar d and condensation on the board in a highly humid environment may cause the impedance between the xt1 and xt2 pins to drop and disable oscillation. when using the circuit board in such an environment, prevent the circuit board from absorbing moisture by taking measures such as coating the circuit board. ? coat the surface of the circuit board by using material that does not generate capacitance or leakage betw een the xt1 and xt2 pins. p.223 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 965 jun 20, 2011 (9/39) chapter classification function details of function cautions page x1/xt1 oscillator ? when x2 and xt1 are wired in parallel, the crosstalk noise of x2 may increase with xt1, resulting in malfunctioning. p.225 ? internal high- speed oscillator ? to use the 1, 8, or 20 mhz internal high-speed oscillation clock, use the option byte to set the frequency in advance (for details, see chapter 26 option byte). also, the internal high-speed oscillator au tomatically starts oscillating after reset release. (if 8 mhz or 20 mhz is selected by using the option byte, the microcontroller operates using the 8 mhz internal high-speed oscillator.) to use the 20 mhz internal high-speed oscillator to operate the microcontr oller, oscillation is started by setting bit 0 (dscon) of the dscctl register to 1 with v dd 2.7 v. p.226 ? if the voltage rises with a slope of less than 0.5 v/ms (min.) from power application until the voltage reaches 1.8 v, input a low level to the reset pin from power application until the voltage reaches 1.8 v, or set the lvi default start function stopped by using the option byte (lvioff = 0) (see figure 5-14). by doing so, the cpu operates with the same timing as <2> and thereafter in figure 5-13 after reset release by the reset pin. p.229 ? when lvi default start function stopped is set (option byte: lvioff = 1) it is not necessary to wait for the oscillati on stabilization time when an external clock input from the exclk pin is used. p.229 ? a voltage stabilization time (about 2.12 to 5.84 ms) is required after the supply voltage reaches 1.61 v (typ.). if the time for the supply voltage to rise from 1.61 v (typ.) to 2.07 v (typ.) is shorter than the voltage stabilization time, reset processing is entered after the voltage stabilization time elapses. p.231 ? hard clock generator operation when power supply voltage is turned on when lvi default start function enabled is set (option byte: lvioff = 0) it is not necessary to wait for the oscillati on stabilization time when an external clock input from the exclk pin is used. p.231 ? x1/p121, x2/exclk/p122 the x1/p121 and x2/exclk/p122 pins are in the input port mode after a reset release. p.232 ? the cmc register can be written only once a fter reset release, by an 8-bit memory manipulation instruction. therefore, it is necessary to also set the value of the oscsels bit at the same time. for oscsels bit, see 5.6.3 example of controlling subsystem clock. p.232 ? x1 clock set the x1 clock after the supply voltage has reached the operable voltage of the clock to be used (see chapter 31 electrical specifications). p.232 ? the cmc register can be written only once a fter reset release, by an 8-bit memory manipulation instruction. therefore, it is necessary to also set the value of the oscsels bits at the same time. for oscsels bits, see 5.6.3 example of controlling subsystem clock. p.233 ? external main system clock set the external main system clock a fter the supply voltage has reached the operable voltage of the clock to be used (see chapter 31 electrical specifications). p.233 ? controlling high- speed system clock high-speed system clock be sure to confirm that mcs = 0 or cls = 1 when setting mstop to 1. in addition, stop peripheral hardware that is operating on the high-speed system clock. p.235 ? if switching the cpu/peripheral hardware cl ock from the high-sp eed system clock to the internal high-speed oscillation clock after restarting the internal high-speed oscillation clock, do so after 10 s or more have elapsed. if the switching is made immediately after t he internal high-speed oscillation clock is restarted, the accuracy of the internal high-speed oscillation cannot be guaranteed for 10 s. p.236 ? chapter 5 soft controlling internal high- speed oscillation clock internal high- speed oscillation clock be sure to confirm that mcs = 1 or cls = 1 when setting hiostop to 1. in addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock. p.237 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 966 jun 20, 2011 (10/39) chapter classification function details of function cautions page soft xt1/p123, xt2/p124 the xt1/p123 and xt2/p124 pins are in the input port mode after a reset release. p.237 ? hard when the subsystem clock is used as the cp u clock, the subsystem clock is also supplied to the peripheral hardware (except the real-time counter, timer array unit (when f sub /2, f sub /4, the valid edge of ti0mn input, or the valid edge of intrtci is selected as the count clock), clock output/buzzer output, and watchdog timer). at this time, the operations of the a/d converter and iica are not guaranteed. for the operating characteristics of the peripheral hardware, refer to the chapters describing the various peripheral hardware as well as chapter 31 electrical specifications. pp.237, 238 ? the cmc register can be written only once after reset release, by an 8-bit memory manipulation instruction. therefore, it is necessary to also set the value of the exclk and oscsel bits at the same time. for exclk and oscsel bits , see 5.6.1 (1) example of setting procedure when oscillating the x1 clock or 5.6.1 (2) example of setting procedure when using the external main system clock. p.238 ? be sure to confirm that cls = 0 when setting xtstop to 1. in addition, stop the peripheral hardware if it is operating on the subsystem clock. p.238 ? subsystem clock control subsystem clock the subsystem clock oscillation cannot be stopped using the stop instruction. p.238 ? pp.241 ? chapter 5 soft cpu clock status transition ? set the clock after the supply voltage has reached the operable voltage of the clock to be set (see chapter 31 electrical specifications). 242, 245 channel 5 of timer array unit 0 of the 78k0r/lf3 can be used only as an interval timer. p.251 ? channel 6 of timer array unit 0 of the 78k0r/lf3 can be used only as an interval timer, for pwm output (master channel), and for one-shot pulse output (master channel when software trigger start is selected). p.251 ? channels 0 to 3 of timer array unit 1 of the 78k0r/lf3 and 78k0r/lg3 can be used only as interval timers. p.251 ? ? channels 1, 5 to 7 of timer array unit 0 and channels 0 to 3 of timer array unit 1 cannot be used as frequency dividers. p.251 ? tcrmn: timer/counter register mn the count value is not captured to tdrmn even when tcrmn is read. p.255 ? tdrmn: timer data register mn tdrmn does not perform a capture operation ev en if a capture trigger is input, when it is set to the compare function. p.260 ? per0: peripheral enable register 0 when setting the timer array unit, be sure to se t taumen to 1 first. if taumen = 0, writing to a control register of the timer array unit is ignored, and all read values are default values. p.262 ? chapter 6 soft timer array unit tpsm: timer clock select register m be sure to clear bits 15 to 8 to ?0?. p.268 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 967 jun 20, 2011 (11/39) chapter classification function details of function cautions page be sure to clear bits 14, 13, 5, and 4 to ?0?. pp.264 to 266 ? channel 5 of timer array unit 0 and channel s 0 to 3 of timer array unit 1 of the 78k0r/lf3 can be set only to the interval mode. pp.266, 271 ? channel 6 of timer array unit 0 of the 78k0r /lf3 can be set only to the interval mode and one-count mode (when using as master). pp.266, 271 ? tmrmn: timer mode register mn channels 0 to 3 of timer array unit 1 of the 78k0r/lg3 can be set only to the interval mode. pp.266, 271 ? tsm: timer channel start register m be sure to clear bits 15 to 8 of ts0 and bits 15 to 4 of ts1 to ?0?. p.270 ? start timing (in interval timer mode) in the first cycle operation of count clock after writing tsmn, an error at a maximum of one clock is generated since count st art delays until count clock has been generated. when the information on count start timing is necessary, an interrupt can be generated at count start by setting mdmn0 = 1. p.272 ? start timing (in capture mode) in the first cycle operation of count clock a fter writing tspq, an error at a maximum of one clock is generated since count start del ays until count clock has been generated. when the information on count start timing is necessary, an interrupt can be generated at count start by setting mdpq0 = 1. p.273 ? start timing (in one-count mode and in capture & one-count mode) an input signal sampling error is generated since operation starts upon start trigger detection (the error is one count clock when tipq is used). pp.275, 276 ? ttm: timer channel stop register m be sure to clear bits 15 to 8 of tt0 and bits 15 to 4 of tt1 to ?0?. p.277 ? tisp: timer input select register p when the lin-bus communication function is used, select the input signal of the rxd3 pin by setting isc1 to 1 and tis07 = 0. p.279 ? for 78k0r/lf3, be sure to clear bits 15 to 8, 6 and 5 of toe0 to ?0?. p.279 ? for 78k0r/lg3, be sure to clear bits 15 to 8 of toe0 to ?0?. p.279 ? toep: timer output enable register p for 78k0r/lh3, be sure to clear bit 15 to 8 of toe0, bits 15 to 4 of toe1 to ?0?. p.279 ? for 78k0r/lf3, be sure to clear bits 15 to 8, 6 and 5 of to0 to ?0?. p.280 ? for 78k0r/lg3, be sure to clear bits 15 to 8 of to0 to ?0?. p.280 ? top: timer output register p for 78k0r/lh3, be sure to clear bit 15 to 8 of to0, bits 15 to 4 of to1 to ?0?. p.280 ? for 78k0r/lf3, be sure to clear bits 15 to 8, 6 and 5 of tol0 to ?0?. p.281 ? for 78k0r/lg3, be sure to clear bits 15 to 8 of tol0 to ?0?. p.281 ? tolp: timer output level register p for 78k0r/lh3, be sure to clear bit 15 to 8 of tol0, bits 15 to 4 of tol1 to ?0?. p.281 ? for 78k0r/lf3, be sure to clear bits 15 to 8, 6 and 5 of tom0 to ?0?. p.282 ? for 78k0r/lg3, be sure to clear bits 15 to 8 of tom0 to ?0?. p.282 ? chapter 6 soft timer array unit tomp: timer output mode register p for 78k0r/lh3, be sure to clear bit 15 to 8 of tom0, bits 15 to 4 of tom1 to ?0?. p.282 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 968 jun 20, 2011 (12/39) chapter classification function details of function cautions page isc: input switch control register be sure to clear bits 5 to 7 to ?0?. p.283 ? changing values set in registers top,toep, tolp, and tomp during timer operation since the timer operations (operations of tcrpq and tdrpq) are independent of the topq output circuit and changing the values set in top, toep, tolp, and tomp does not affect the timer operation, the values can be changed during timer operation. to output an expected waveform from the topq pin by timer operation, however, set top, toep, tolp, and tomp to the values stated in the register setting example of each operation. when the values set in toep, tolp, and to mp (except for top) are changed close to the timer interrupt (inttmpq), the waveform output to the topq pin may be different depending on whether the val ues are changed immediately before or immediately after the timer interrup t (inttmpq) signal generation timing. p.291 ? default level of topq pin and output level after timer operation start the following figure shows the topq pin output level transition when writing has been done in the state of toepq = 0 before port output is enabled and toepq = 1 is set after changing the default level. (a) when operation starts with tompq = 0 setting (toggle output) the setting of tolpq is invalid when tompq = 0. when the timer operation starts after setting the default level, the toggle signal is generated and the output level of topq pin is reversed. (b) when operation starts with tompq = 1 setting (combination operation mode (pwm output)) when tompq = 1, the active level is determined by tolpq setting. pp.291, 292 ? operation of topq pin in combination operation mode (tompq = 1) (a) when tolpq setting has been changed during timer operation when the tolpq setting has been changed during timer operation, the setting becomes valid at the generation timing of topq change condition. rewriting tolpq does not change the output level of topq. the following figure (figure 6-30) show s the operation when the value of tolpq has been changed during timer operation (tompq = 1) (b) set/reset timing to realize 0%/100% output at pwm output, the topq pin/topq set timing at master channel timer interrupt (inttmpq ) generation is delayed by 1 count clock by the slave channel time r interrupt (inttmqr). if the set condition and reset condition are generated at the same time, a higher priority is given to the latter. figure 6-31 shows the set/reset operating statuses where the master/slave channels are set as follows. pp.291, 293 ? chapter 6 soft timer array unit collective manipulation of topq bits when toepq = 1, even if the output by timer interrupt of each timer (inttmpq) contends with writing to topq, output is normally done to topq pin. p.295 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 969 jun 20, 2011 (13/39) chapter classification function details of function cautions page input pulse interval measurement the tipq pin input is sampled using the operating clock selected with the ckspq bit of the tmrpq register, so an error equal to the number of operating clocks occurs. p.315 ? operation of timer array unit as independent channel input signal high-/low-level width measurement the tipq pin input is sampled using the operating clock selected with the ckspq bit of the tmrpq register, so an error equal to the number of operating clocks occurs. p.319 ? pwm function to rewrite both tdrmn of the ma ster channel and tdrmp of the slave channel, a write access is necessary two times. the timing at which the values of tdrmn and tdrmp are loaded to tcrmn and tcrmp is upon occurrence of inttmmn of the master channel. thus, when rewriting is performed split before and after occurrence of inttmmn of the master channel, the tomp pin cannot output the expected waveform. to rewrite both tdrmn of the master and tdrmp of the slave, therefore, be sure to rewrite both the registers imm ediately after inttmmn is generated from the master channel. p.323 ? one-shot pulse output function the timing of loading of tdrmn of the master channel is different from that of tdrmp of the slave channel. if tdrmn and tdrmp are rewritten during operation, therefore, an illegal waveform is output. be sure to rewrite tdrmn and tdrmp after inttmmn of the channel to be rewritten is generated. p.330 ? chapter 6 soft operation of plural channels of timer array unit multiple pwm output function to rewrite both tdrmn of the master channel and tdrmp of the slave channel 1, write access is necessary at least twice. since the values of tdrmn and tdrmp are loaded to tcrmn and tcrmp after inttmmn is generated from the master channel, if rewriting is performed separat ely before and after generation of inttmmn from the master channel, the tomp pin cannot output the expected waveform. to rewrite both tdrmn of the master and tdrmp of the slave, be sure to rewrite both the registers immediately after inttmmn is generated from the master channel (this applies also to tdrmq of the slave channel 2). p.337 ? when using the real-time counter, first se t rtcen to 1, while oscillation of the subsystem clock (f sub ) is stable. if rtcen = 0, writing to a control register of the real- time counter is ignored, and, even if the regi ster is read, only the default value is read. p.348 ? per0: peripheral enable register 0 clock supply to peripheral fu nctions except the real-time counter can be stopped in the halt mode when operating on the subsys tem clock by setting rtclpc of the operation speed mode control register (osmc) to 1. in this case, set rtcen to 1 and bits 0 to 6 of per0 to 0. p.348 ? chapter 7 soft real-time counter rtcc0: real- time counter control register 0 if rcloe0 and rcloe1 are changed when rtce = 1, the last waveform of the 32.768 khz and 1 hz output signals may become short. p.349 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 970 jun 20, 2011 (14/39) chapter classification function details of function cautions page rtcc1: real- time counter control register 1 if writing is performed to the rtcc1 register with a 1-bit manipulation instruction, the rifg and wafg flags may be cleared. therefore, to perform writing to the rifg and wafg flags, be sure to use an 8-bit manipulation inst ruction. at this time, set 1 to the rifg and wafg flags to invalidate writing and not to clear the rifg and wafg flags during writing. when the value may be re written because the rifg and wafg flags are not being used, the rtcc1 register may be written by using a 1-bit manipulation instruction. p.351 ? soft change ict2, ict1, and ict0 when rinte = 0. p.352 ? when the output from rtcdiv pin is stopped, the output continues after a maximum of two clocks of f xt and enters the low level. while 512 hz is output, and when the output is stopped immediately after entering the high level, a pulse of at least one clock width of f sub may be generated. p.352 ? hard rtcc2: real- time counter control register 2 after the real-time counter starts operating, the output width of the rtcdiv pin may be shorter than as set during the first interval period. p.352 ? when a correction is made by using the subcud register, the value may become 8000h or more. p.353 ? this register is also cleared by reset effe cted by writing the second count register. p.353 ? rsubc: sub- count register the value read from this register is not guaranteed if it is read during operation, because a value that is changing is read. p.353 ? hour: hour count register bit 5 (hour20) of hour indicates am(0)/ pm(1) if ampm = 0 (if the 12-hour system is selected). p.354 ? week: week count register the value corresponding to the month count regi ster or the day count register is not stored in the week count register automati cally. after reset release, set the week count register as follow. p.356 ? alarmwm: alarm minute register set a decimal value of 00 to 59 to this register in bcd code. if a value outside the range is set, the alarm is not detected. p.359 ? set a decimal value of 00 to 23, or 01 to 12 and 21 to 32 to this register in bcd code. if a value outside the range is set, the alarm is not detected. p.359 ? alarmwh: alarm hour register bit 5 (wh20) of alarmwh indicates am(0)/pm(1) if ampm = 0 (if the 12-hour system is selected). p.359 ? chapter 7 soft real-time counter reading/writing real-time counter complete the series of operations of setting rwait to 1 to clearing rwait to 0 within 1 second. pp.364 , 365 ? if a value other than ?ach? is written to wdte , an internal reset signal is generated. p.376 ? if a 1-bit memory manipulation instruction is executed for wdte, an internal reset signal is generated. p.376 ? chapter 8 soft watchdog timer wdte: watchdog timer enable register the value read from wdte is 9ah/1ah (this differs from the written value (ach)). p.376 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 971 jun 20, 2011 (15/39) chapter classification function details of function cautions page when data is written to wdte for the first time after reset release, the watchdog timer is cleared in any timing regardless of the wi ndow open time, as long as the register is written before the overflow time, and t he watchdog timer starts counting again. p.377 ? if the watchdog timer is cleared by writing ?ach? to wdte, the actual overflow time may be different from the overflow time set by the option byte by up to 2/f il seconds. p.377 ? the watchdog timer can be cleared immediately before the count value overflows. p.377 ? the operation of the watchdog timer in the halt and stop modes differs as follows depending on the set value of bit 0 (wdstbyon) of the option byte (000c0h). (see the table on page 378.) if wdstbyon = 0, the watchdog timer resumes counting after the halt or stop mode is released. at this time, the c ounter is cleared to 0 and counting starts. when operating with the x1 oscillation clock after releasing the stop mode, the cpu starts operating after the oscillati on stabilization time has elapsed. therefore, if the period between the stop mode release and the watchdog timer overflow is short, an overflow occurs during the oscillation stabilization time, causing a reset. consequently, set the overflow time in consideration of the oscillation stabilization time when operating with the x1 oscillation clock and when the watchdog timer is to be cleared after the stop mode release by an interval interrupt. p.378 ? controlling operation the watchdog timer continues its operation during self-programming of the flash memory and eeprom emulation. during pr ocessing, the interrupt acknowledge time is delayed. set the overflow time and window size taking this delay into consideration. p.378 ? setting overflow time the watchdog timer continues its operation during self-programming of the flash memory and eeprom emulation. during processing, the interrupt acknowledge time is delayed. set the overflow time and window size taking this delay into consideration. p.378 ? when data is written to wdte for the firs t time after reset release, the watchdog timer is cleared in any ti ming regardless of the window open time, as long as the register is written before the overflow ti me, and the watchdog timer starts counting again. p.379 ? the watchdog timer continues its operation during self-programming of the flash memory and eeprom emulation. during processing, the interrupt acknowledge time is delayed. set the overflow time and window size taking this delay into consideration. p.379 ? chapter 8 soft watchdog timer setting window open period when bit 0 (wdstbyon) of the option by te (000c0h) = 0, the window open period is 100% regardless of the values of window1 and window0. p.379 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 972 jun 20, 2011 (16/39) chapter classification function details of function cautions page chapter 8 soft watchdog timer setting interval interrupt when operating with the x1 oscillation cloc k after releasing the stop mode, the cpu starts operating after the oscillation stabilization time has elapsed. therefore, if the period between the stop mode release and the watchdog timer overflow is short, an overflow occurs during the oscillation stabilization time, causing a reset. consequently, set the overflow time in consideration of the oscillation stabilization time when operating with the x1 oscillation clock and when the watchdog timer is to be cleared after the stop mode release by an interval interrupt. p.380 ? change the output clock after disab ling clock output (pcloen = 0). p.383 ? if the selected clock (f main or f sub ) stops during clock output (pcloen = 1), the output becomes undefined. p.383 ? chapter 9 soft clock output/ buzzer output controller cksn: clock output select registers n to shift to stop mode when the main system clock is selected (cseln = 0), set pcloen = 0 before executing the stop inst ruction. when the subsystem clock is selected (cseln = 1), pcloen = 1 can be set because the clock can be output in stop mode. p.383 ? per0: peripheral enable register 0 when setting the a/d converter, be sure to set adcen to 1 first. if adcen = 0, writing to a control register of the a/d conver ter is ignored, and, even if the register is read, only the default value is read. p.390 ? a/d conversion must be stopped before rewriting bits adscm, fr0 to fr2, lv1, and lv0 to values other than the identical data. p.392 ? adm: a/d converter mode register when using the a/d converter in normal mode 2 (lv1 = 0, lv0 = 1) or low voltage mode (lv1 = 1, lv0 = 0), enable the input gate voltage boost circuit for the a/d converter by using the analog reference voltage control register (advrc), and then set adce and adcs to 1. after the voltage boost circuit stabilization time (10 s) passes after the input gate voltage boost circuit for the a/d converter has been enabled, set adcs to 1. pp.392 , 393 ? adm1: a/d converter mode register 1 rewriting adm1 during a/d conversion is pr ohibited. rewrite it when conversion operation is stopped (adcs = 0). p.394 ? when using the a/d converter in normal mode 2 (lv1 = 0, lv0 = 1) or low voltage mode (lv1 = 1, lv0 = 0), enable the input gate voltage boost circuit for the a/d converter by using the analog reference voltage control register (advrc), and then set adce and adcs to 1. after the voltage boost circuit stabilization time (10 s) passes after the input gate voltage boost circuit for the a/d converter has been enabled, set adcs to 1. p.395 ? to use voltage reference output to the positive reference voltage of the a/d converter, be sure to set vron to 1 after setting vrsel to 1. p.396 ? advrc: analog reference voltage control register do not change the output voltage of the reference voltage by using vrgv during the voltage reference operation (vron = 1). p.396 ? adcr: 12-bit a/d conversion result register when writing to a/d converter mode register (adm), analog input channel specification register (ads), and a/d port c onfiguration register (adpc), the contents of adcr may become undefined. read the conversion result following conversion completion before writing to adm, ads, and adpc. using timing other than the above may cause an incorrect conversion result to be read. p.396 ? chapter 10 soft a/d converter adcrh: 8-bit a/d conversion result register when writing to a/d converter mode register (adm), analog input channel specification register (ads), and a/d port c onfiguration register (adpc), the contents of adcrh may become undefined. read the conversion result following conversion completion before writing to adm, ads, and adpc. using timing other than the above may cause an incorrect conversion result to be read. p.397 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 973 jun 20, 2011 (17/39) chapter classification function details of function cautions page be sure to clear bits 4 to 7 to ?0?. p.398 ? set a channel to be used for a/d conversion in the input mode by using port mode registers 2 and 15 (pm2, pm15). p.398 ? do not set the pin that is set by adpc as digital i/o by ads. p.398 ? ads: analog input channel specification register when using an operational amplifier n, the ou tput signal of an operational amplifier n can be used as an analog input. p.398 ? set a channel to be used for a/d conversion in the input mode by using port mode registers 2 and 15 (pm2, pm15). p.399 ? adpc: a/d port configuration register do not set the pin that is set by adpc as digital i/o by ads. p.399 ? if a pin is set as an analog input port, not t he pin level but ?0? is always read. p.400 ? pm2, pm15: port mode registers 2 and 15 when an operational amplifier is used, pins ampn+, ampn ? , and ampno are used, so the alternative analog input functions c annot be used. the operational amplifier output signals, however, can be used as analog inputs. p.401 ? make sure the period of <4> to <8> is 1 s or more. p.404 ? to use an operational amplifier output for an analog input, start operating the operational amplifier before setting the a/d conversion operation (see chapter 12 operational amplifier). furthermore, do not change the operational amplifier setting during the a/d conversion operation. p.404 ? to use an output voltage of the voltage reference for a positive reference voltage of the a/d converter, start operating the voltage reference before setting the a/d conversion operation (see chapter 13 voltage reference). furthermore, do not change the voltage reference setting during the a/d conversion operation. p.404 ? basic operations of a/d converter when using the a/d converter in normal mode 2 (lv1 = 0, lv0 = 1) or low voltage mode (lv1 = 1, lv0 = 0), enable the input gate voltage boost circuit for the a/d converter by using the analog reference voltage control register (advrc), and then set adce and adcs to 1. after the voltage boost circuit stabilization time (10 s) passes after the input gate voltage boost circuit for the a/d converter has been enabled, set adcs to 1. p.404 ? make sure the period of <4> to <8> is 1 s or more. p.411 ? <4> may be done between <5> and <7>. p.411 ? <4> can be omitted. however, ignore data of the first conversion after <8> in this case. p.411 ? the period from <9> to <13> differs from the conversion time set using bits 5 to 1 (fr2 to fr0, lv1, lv0) of adm. the pe riod from <12> to <13> is the conversion time set using fr2 to fr0, lv1, and lv0. p.411 ? to use an operational amplifier output for an analog input, start operating the operational amplifier before setting the a/d conversion operation (see chapter 12 operational amplifier). furthermore, do not change the operational amplifier setting during the a/d conversion operation. p.411 ? to use an output voltage of the voltage reference for a positive reference voltage of the a/d converter, start operating the voltage reference before setting the a/d conversion operation (see chapter 13 voltage reference). furthermore, do not change the voltage reference setting during the a/d conversion operation. p.411 ? chapter 10 soft a/d converter a/d conversion operation when using the a/d converter in normal mode 2 (lv1 = 0, lv0 = 1) or low voltage mode (lv1 = 1, lv0 = 0), enable the input gate voltage boost circuit for the a/d converter by using the analog reference voltage control register (advrc), and then set adce and adcs to 1. after the voltage boost circuit stabilization time (10 s) passes after the input gate voltage boost circuit for the a/d converter has been enabled, set adcs to 1. p.411 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 974 jun 20, 2011 (18/39) chapter classification function details of function cautions page soft operating current in stop mode shift to stop mode after stopping the a/d converter (by setting bit 7 (adcs) of the a/d converter mode register (adm) to 0). the operating current can be reduced by setting bit 0 (adce) of the a/d converter mode register (adm) to 0 at the same time. when using normal mode 2 (lv1 = 0, lv0 = 1) or low voltage mode (lv1 = 1, lv0 = 0), clear bit 1 (vrgv) and bit 0 (vron) of the analog reference voltage control register (advrc) to 0, and then shift to stop mode. to restart from the standby status, clear bit 0 (adif) of interrupt request flag register 1l (if1l) to 0 and start operation. p.414 ? hard input range of ani0 to ani10, ani15 observe the rated range of the ani0 to ani10, ani15 input voltage. if a voltage of av dd0 or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. p.414 ? conflict between a/d conversion result register (adcr, adcrh) write and adcr or adcrh read by instruction upon the end of conversion adcr or adcrh read has priority. after the read operation, the new conversion result is written to adcr or adcrh. p.414 ? soft conflicting operations conflict between adcr or adcrh write and a/d converter mode register (adm) write, analog input channel specification r egister (ads), or a/d port configuration register (adpc) write upon the end of conversion adm, ads, or adpc write has priority. adcr or adcrh write is not performed, nor is the conversion end interrupt signal (intad) generated. p.414 ? hard noise countermeasures to maintain the 12-bit resolution, attention must be paid to noise input to the av refp pin and pins ani0 to ani10, ani15. <1> connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. <2> the higher the output impedance of the analog input source, the greater the influence. to reduce the noise, connecting external c as shown in figure 10-28 is recommended. <3> do not switch these pins wi th other pins during conversion. <4> the accuracy is improved if the halt m ode is set immediately after the start of conversion. p.414 ? soft the analog input pins (ani0 to ani7) are also used as input port pins (p20 to p27). the analog input pins (ani8 to ani10, ani15) are also used as input port pins (p150 to p152, p157). when a/d conversion is performed with any of ani0 to ani10, and ani15 selected, do not access p20 to p27, p150 to p152, and p157 while conversion is in progress; otherwise the conversion resolution may be degraded. it is recommended to select pins used as p20 to p27, p150 to p152, and p157 starting with the ani0/p20 that is the furthest from av dd0 . p.415 ? if the pins adjacent to the pins currently used for a/d conversion are used as digital i/o port, the expected value of the a/d conversion may not be obtained due to coupling noise. therefore, make sure that digital pulses are not input to or output from the pins adjacent to t he pin undergoing a/d conversion. p.415 ? chapter 10 hard a/d converter ani0 to ani10, ani15 if any pin among pins of ports 2 and 15 is used as digital output port during a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. therefore, make sure that digital pulses are not output to pins of ports 2 and 15 during a/d conversion. p.415 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 975 jun 20, 2011 (19/39) chapter classification function details of function cautions page input impedance of ani0 to ani10, ani15 pins this a/d converter charges a sampling c apacitor for sampling during sampling time. therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flows during sampling. consequently, the input impedance fluctuates depending on whether sampling is in progress, and on the other states. to make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog input source to within 1 k , and to connect a capacitor of about 100 pf to the ani0 to ani10 and ani15 pins (see figure 10-28). p.415 ? hard av refp pin input impedance a series resistor string of several tens of k is connected between the av refp and av refm (or av ss ) pins. therefore, if the output impedance of the reference voltage supply is high, this will result in a series connection to the series resistor string between the av refp and av refm (or av ss ) pins, resulting in a large reference voltage (av ref ) error of a/d converter. p.416 ? interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the analog input channel specification register (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pre-c hange analog input may be set just before the ads rewrite. caution is therefore requir ed since, at this time, when adif is read immediately after the ads rewrite, adif is set despite the fact a/d conversion for the post-change analog input has not ended. when a/d conversion is stopped and then resumed, clear adif before the a/d conversion operation is resumed. p.416 ? conversion results just after a/d conversion start the first a/d conversion val ue immediately after a/d conversion starts may not fall within the rating range if the adcs bit is set to 1 within 1 s after the adce bit was set to 1, or if the adcs bit is set to 1 with the adce bit = 0. take measures such as polling the a/d conversion end interrupt request (intad) and removing the first conversion result. p.416 ? a/d conversion result register (adcr, adcrh) read operation when a write operation is performed to a/d converter mode register (adm), a/d converter mode register 1 (adm1), analog i nput channel specification register (ads), and a/d port configuration register (adpc), the contents of adcr and adcrh may become undefined. read the conversion re sult following conversion completion before writing to adm, adm1, ads, or adpc. using a timing other than the above may cause an incorrect conversion result to be read. p.417 ? internal equivalent circuit the equivalent circuit of the analog input block is shown below. (see figure 10-30.) p.417 ? chapter 10 soft a/d converter rewriting dacswn during a/d conversion rewriting dacswn (n = 0, 1) during a/ d conversion is prohibited when both the positive reference voltage of a/d converter (ad refp ) and the positive reference voltage of the d/a converter (da ref ) are the voltage reference output (v refout ) (vrsel = 1 and daref = 1). rewrite it when conversion operation is stopped (adcs = 0). p.417 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 976 jun 20, 2011 (20/39) chapter classification function details of function cautions page per0: peripheral enable register 0 when setting the d/a converter, be sure to set dacen to 1 first. if dacen = 0, writing to a control register of the d/a conver ter is ignored, and, even if the register is read, only the default value is read. p.420 ? dacsw0, dacsw1: d/a conversion value setting registers w0 and w1 rewriting dacswn during a/d conversion is prohibited when both the positive reference voltage of the a/d converter (ad refp ) and the positive reference voltage of the d/a converter (da ref ) are the voltage reference output (v refout ) (vrsel = 1 and daref = 1). rewrite it when conversion operation is stopped (adcs = 0). pp.422 , 424 ? operation of d/a converter even if 1, 0, and then 1 is set to the dacen bit, there is a wait after 1 is set for the last time. pp.423 , 424 ? operation in normal mode if the dacswn or dacsn register is rewritten during the settling time, d/a conversion is aborted and reconversion by using the rewritten values starts. p.423 ? make the interval between each generation of the inttm0m signal longer than the settling time. if an inttm0m signal is generated during the settling time, d/a conversion is aborted and reconversion starts. p.424 ? operation in real-time output mode even if the generation of the inttm0m signal and rewriting the dacswn or dacsn register conflict, the d/a conversion result is output. p.424 ? digital port i/o function, which is the alternate function of the ano0, ano1 pins the digital port i/o function, which is t he alternate function of the ano0 and ano1 pins, does not operate during d/a conversion. when the p11 register is read during d/a c onversion, 0 is read in input mode and the set value of the p11 register is read in output mode. if the digital output mode is set, no output data is output to pins. p.424 ? chapter 11 soft d/a converter operation of the d/a converter continues in the halt and stop mode the operation of the d/a converter continues in the halt and stop mode. to lower the power consumption, therefore, clear the dacen bit of the dam register to 0 (d/a conversion stop), and execute halt or stop instruction. p.424 ? per0: peripheral enable register 0 when setting operational amplifier, be sure to set adcen to 1 first. if adcen = 0, writing to a control register of operational am plifier is ignored, and, even if the register is read, only the default value is read. p.427 ? use the adpc register to specify as analog inputs the pins to be used with operational amplifiers. p.428 ? oac: operational amplifier control register when using as digital inputs the pins of ports 2 and 15, which are not used with operational amplifiers, when the operational amplifiers are used, make sure that the input levels are fixed. p.428 ? adpc: a/d port configuration register set pins to be used with operational amplif iers in the input mode by using port mode registers 2 and 15 (pm2, pm15). p.429 ? soft if a pin is set as an analog input port, not t he pin level but ?0? is always read. p.430 ? hard pm2, pm15: port mode registers 2 and 15 when an operational amplifier is used, ampn+, ampn ? , and ampno pins are used, so the alternative analog input functions c annot be used. the operational amplifier output signals, however, can be used as analog inputs. pp.431 , 432 ? chapter 12 soft operational amplifier single amp mode to use as an input of the a/d converter a voltage that has been amplified in single amplifier mode, enable operation in single amplifier mode before selecting an analog input channel by using the ads register. p.433 ? chapter 13 soft voltage reference per0: peripheral enable register 0 when setting voltage reference, be sure to set adcen to 1 first. if adcen = 0, writing to a control register of voltage refere nce is ignored, and, even if the register is read, only the default value is read. p.435 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 977 jun 20, 2011 (21/39) chapter classification function details of function cautions page during voltage reference operation, be sure to connect a tantalum capacitor (capacitance: 10 f 30 %, esr: 2 (max.), esl: 10 nh (max.)) and a ceramic capacitor (capacitance: 0.1 f 30 %, esr: 2 (max.), esl: 10 nh (max.)) to the v refout /av refp pin for stabilizing the reference voltage. furthermore, do not apply a voltage from the v refout /av refp pin during voltage reference operation. p.436 ? to use voltage reference output (v refout ) to the positive reference voltage of the a/d converter (ad refp ) and the positive reference voltage of the the d/a converter (da refp ), be sure to set vron to 1 after setting vrsel to 1. p.436 ? rewriting dacswn (n = 0, 1) during a/ d conversion is prohibited when both the positive reference voltage of the a/d converter (ad refp ) and the positive reference voltage fo the d/a converter (da refp ) are the voltage reference output (v refout ) (vrsel = 1 and daref = 1). rewrite it when conversion operation is stopped (adcs = 0). p.437 ? soft advrc: a/d reference voltage control register do not change the output voltage of the reference voltage by using vrgv during the voltage reference operation (vron = 1). p.437 ? chapter 13 hard voltage reference v refout pin the v refout output voltage can be used only as the positive reference voltage of the internal a/d and d/a converters of the microcontroller. do not connect an external circuit other than a tantalum capacitor (capacitance: 10 f 30 %, esr: 2 (max.), esl: 10 nh (max.)) and a cerami c capacitor (capacitance: 0.1 f 30 %, esr: 2 (max.), esl: 10 nh (max.)) to the v refout pin for stabilizing the reference voltage. p.437 ? sdrmn: lower 8 bits of the serial data register mn be sure to clear bit 8 to ?0?. p.445 ? when setting serial array unit m, be sure to set saumen to 1 first. if saumen = 0, writing to a control register of serial array unit m is ignored, and, even if the register is read, only the default value is read (except for input switch control register (isc), noise filter enable register (nfen0), port input mode register (pim1, pim7), port output mode register (pom1, pom7, pom8), port mode registers (pm1, pm5, pm7, pm8), and port registers (p1, p5, p7, p8)). p.447 ? per0: peripheral enable register 0 after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. p.447 ? be sure to clear bits 15 to 8 to ?0?. p.448 ? spsm: serial clock select register m after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. p.448 ? smrmn: serial mode register mn be sure to clear bits 13 to 9, 7, 4, and 3 to ?0?. be sure to set bit 5 to ?1?. p.449 ? pp.451 ? scrmn: serial communication operation setting register mn be sure to clear bits 3, 6, and 11 to ?0?. be sure to set bit 2 to ?1?. to 453 be sure to clear bit 8 to ?0?. p.454 ? setting sdrmn[15:9] = (0000000b, 0000001b) is prohibited when uart is used. p.454 ? chapter 14 soft configuration of serial array unit sdrmn: serial data register mn setting sdrmn[15:9] = 0000000b is prohibited when the simplified i 2 c is used. set sdrmn[15:9] to 0000001b or greater. p.454 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 978 jun 20, 2011 (22/39) chapter classification function details of function cautions page sirmn: serial flag clear trigger register mn be sure to clear bits 15 to 3 to ?0?. p.457 ? ssm: serial channel start register m be sure to clear bits 15 to 4 to ?0?. p.459 ? stm: serial channel stop register m be sure to clear bits 15 to 4 to ?0?. p.460 ? soem: serial output enable register m be sure to clear bits 15 to 3 of soe0, and bits 1 and 15 to 3 of soe1 to ?0?. p.461 ? som: serial output register m be sure to set bits 11 and 3 of so0, and bits 11 to 9, 3, and 1 of so1 to ?1?. and be sure to clear bits 15 to 12 and 7 to 4 of som to ?0?. p.462 ? solm: serial output level register m be sure to clear bits 15 to 3, 1 to ?0?. p.463 ? isc: input switch control register be sure to clear bits 7 to 5 to ?0?. p.464 ? configuration of serial array unit nfen0: noise filter enable register 0 be sure to clear bits 7, 5, 3, and 1 to ?0?. p.465 ? operation stop mode stopping the operation by units if saumen = 0, writing to a control register of serial array unit m is ignored, and, even if the register is read, only the def ault value is read (except for input switch control register (isc), noise filter enable register (nfen0), port input mode register (pim1, pim7), port output mode register (pom1, pom7, pom8), port mode registers (pm1, pm5, pm7, pm8), and port registers (p1, p5, p7, p8)). p.469 ? pp.475, ? master transmission after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. 479, 481 master transmission (in continuous transmission mode) the mdmn0 bit can be rewritten even during operation. however, rewrite it before transfer of the last bit is started, so that it will be rewritten before the transfer end interrupt of the last transmit data. p.480 ? master reception after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. pp.484, 487 ? pp.490, ? master transmission/ reception after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. 493, 494 chapter 14 soft 3-wire serial i/o (csi00, csi01, csi10, csi20) communication master transmission/ reception (in continuous transmission/ reception mode) the mdmn0 bit can be rewritten even during operation. however, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data. p.495 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 979 jun 20, 2011 (23/39) chapter classification function details of function cautions page pp.498, ? slave transmission after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. 502, 504 slave transmission (in continuous transmission mode) the mdmn0 bit can be rewritten even during operation. however, rewrite it before transfer of the last bit is started. p.503 ? slave reception after setting the saumen to 1, be su re to set the spsm register after 4 or more clocks have elapsed. pp.507, 510 ? pp.513, ? slave transmission/ reception after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. 517, 518 3-wire serial i/o (csi00, csi01, csi10, csi20) communication slave transmission/ reception (in continuous transmission/ reception mode) the mdmn0 bit can be rewritten even during operation. however, rewrite it before transfer of the last bit is started, so that it will be rewritten before the transfer end interrupt of the last transmit data. p.519 ? uart communication when using serial array units 0 and 1 as uarts, the channels of both the transmitting side (even-number channel) and the receiving side (odd-number channel) can be used only as uarts. p.522 ? pp.526, ? uart transmission after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. 530, 532 uart transmission (in continuous transmission mode) the mdmn0 bit can be rewritten even during operation. however, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data. p.531 ? for the uart reception, be sure to set sm rmr of channel r that is to be paired with channel n. pp.534, 535 ? uart reception after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. pp.536, 539 ? uart (uart0, uart1, uart2, uart3) communication calculating baud rate setting sdrmn [15:9] = (0000000b, 0000001b) is prohibited. p.548 ? address field transmission after setting the saumen to 1, be sure to set the spsm register after 4 or more clocks have elapsed. p.555 ? data reception ack is also output when the last dat a is received. communication is then completed by setting ?1? to the stmn bit to stop operation and generating a stop condition. p.564 ? chapter 14 soft simplified i 2 c (iic10, iic20) communi- cation calculating baud rate setting sdrmn [15:9] = 0000000b is prohibited. set sdrmn[15:9] to 0000001b or greater. p.566 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 980 jun 20, 2011 (24/39) chapter classification function details of function cautions page do not write data to iica during data transfer. p.581 ? write or read iica only during the wait per iod. accessing iica in a communication state other than during the wait period is pr ohibited. when the de vice serves as the master, however, iica can be written only on ce after the communication trigger bit (stt) is set to 1. p.581 ? iica: iica shift register when communication is reserved, write data to iica after the interrupt triggered by a stop condition is detected. p.581 ? per0: peripheral enable register 0 when setting serial interface iica, be sure to set iicaen to 1 first. if iicaen = 0, writing to a control register of serial interf ace iica is ignored, and, even if the register is read, only the default value is read. p.584 ? if the operation of i 2 c is enabled (iice = 1) when the scl0 line is at high level, the sda0 line is at low level, and dfc of the iicctl1 register is 1, a start condition will be inadvertently detected immediatel y. immediately after enabling i 2 c to operate (iice = 1), set lrel (1) by using a 1-bit memory manipulation instruction. p.585 ? iicctl0: iica control register 0 when bit 3 (trc) of the iica status register (iics) is set to 1, wrel is set to 1 during the ninth clock and wait is canceled, after which trc is cleared and the sda0 line is set to high impedance. release the wait performed while the trc bit is 1 (transmission status) by writing to the iica shift register. p.588 ? iics: iica status register reading the iics register while the addres s match wakeup function is enabled (wup = 1) in stop mode is prohibited. when the wup bit is changed from 1 to 0 (wakeup operation is stopped), regardless of the intiica interrupt request, the change in status is not reflected until the next start c ondition or stop condition is detected. to use the wakeup function, therefore, enabl e (spie = 1) the interrupt generated by detecting a stop condition and read the iics register after the interrupt has been detected. p.589 ? write to stcen only when the operation is stopped (iice = 0). p.592 ? as the bus release status (iicbsy = 0) is recognized regardless of the actual bus status when stcen = 1, when generating the first start condition (stt = 1), it is necessary to verify that no third party co mmunications are in progress in order to prevent such communications from being destroyed. p.592 ? iicf: iica flag register write to iicrsv only when the operation is stopped (iice = 0). p.592 ? setting iicwl and iicwh on slave side note the minimum f clk operation frequency when setti ng the transfer clock. the minimum f clk operation frequency for serial inte rface iica is determined according to the mode. fast mode: f clk = 3.5 mhz (min.) standard mode: f clk = 1 mhz (min.) p.597 ? canceling wait if a processing to cancel a wait state executed when wup (bit 7 of iica control register 1 (iicctl1)) = 1, the wait state will not be canceled. p.604 ? when stcen (bit 1 of iica flag register (iicf)) = 0 immediately after i 2 c operation is enabled (iice = 1), the bus communication status (iicbsy = 1) is recognized regardless of the actual bus status. when changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop c ondition to release the bus, then perform master device communication. when using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). use the following sequence for generating a stop condition. <1> set iica control register 1 (iicctl1). <2> set bit 7 (iice) of iica control register 0 (iicctl0) to 1. <3> set bit 0 (spt) of iicctl0 to 1. p.616 ? chapter 15 soft serial interface iica when stcen = 1 immediately after i 2 c operation is enabled (iice = 1), the bus released status (iicbsy = 0) is recognized regardless of the actual bus status. to generate the first start condition (stt = 1), it is necessary to confirm t hat the bus has been released, so as to not disturb other communications. p.616 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 981 jun 20, 2011 (25/39) chapter classification function details of function cautions page if other i 2 c communications are already in progress if i 2 c operation is enabled and the device partic ipates in communication already in progress when the sda0 pin is low and the scl0 pin is high, the macro of i 2 c recognizes that the sda0 pin has gone low (detects a start condition). if the value on the bus at this time can be recognized as an extension code, ack is returned, but this interferes with other i 2 c communications. to avoid this, start i 2 c in the following sequence. <1> clear bit 4 (spie) of iicctl0 to 0 to disable generation of an interrupt request signal (intiica) when the stop condition is detected. <2> set bit 7 (iice) of iicctl0 to 1 to enable the operation of i 2 c. <3> wait for detection of the start condition. <4> set bit 6 (lrel) of iicctl0 to 1 before ack is returned (4 to 80 clocks after setting iice to 1), to forcibly disable detection. p.616 ? stt, spt: bits 1, 0 of iica control register 0 (iicctl0) setting stt and spt (bits 1 and 0 of iicctl0) again after they are set and before they are cleared to 0 is prohibited. p.616 ? chapter 15 soft serial interface iica reserving transmission when transmission is reserved, set spie (bit 4 of iictl0) to 1 so that an interrupt request is generated when the stop condition is detected. transfer is started when communication data is written to iica after t he interrupt request is generated. unless the interrupt is generated when the stop condition is detected, the device stops in the wait state because the interrupt request is not generated when communication is started. however, it is not necessary to set spie to 1 when msts (bit 7 of iics) is detected by software. p.616 ? lcdmd: lcd mode register bits 0 to 3, 6 and 7 must be set to 0. p.667 ? when lcd display is not performed or necessary, set scoc and vlcon to 0, in order to reduce power consumption. p.668 ? when the external resistance division method has been set (mdset1 = mdset0 = 0), do not set vlcon to 1. p.668 ? set blon and lcdsel to 0 when 8 has been selected as the number of time slices for the display mode. p.668 ? chapter 16 soft lcd controller/d river lcdm: lcd display mode register to use the internal voltage boosting method, specify the reference voltage by using the vlcd register (or perform a reset to use the default value of the reference voltage), wait for the reference voltage setup time (2 ms (min.)), and then set vlcon to 1. p.668 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 982 jun 20, 2011 (26/39) chapter classification function details of function cautions page lcdm: lcd display mode register to manipulate vlcon when using the internal voltage boosting method or capacitor split method, follow the procedure below. a. to stop the operation of the voltage boosti ng/capacitor split circ uit after switching display status from on to off: 1) set to display off status by setting lcdon = 0. 2) disable outputs of all the segment buffers and common buffers by setting scoc = 0. 3) stop the operation of the voltage boosti ng/capacitor split circuit by setting v lcon = 0. b. to stop the operation of the voltage boos ting/capacitor split circuit during display on status: setting prohibited. be sure to stop the operation of the voltage boosting/capacitor split circui t after setting display off. c. to set display on from stop status of the voltage boosting/capacitor split circuit: 1) start the operation of the voltage boos ting/capacitor split circuit by setting vlcon = 1, then wait for the voltage boosting/capacitor split wait time (see chapter 31 electrical specifications). 2) set all the segment buffers and common buffers to non-display output status by setting scoc = 1. 3) set display on by setting lcdon = 1. p.669 ? bits 3, 6, and 7 must be set to 0. p.670 ? lcdc0: lcd clock control register 0 set the lcd clock (lcdcl) to no more than 512 hz when the internal voltage boost method has been set. p.670 ? the vlcd setting is valid only when the voltage boost circuit is operating. p.671 ? bits 5 to 7 must be set to 0. p.671 ? be sure to change the vlcd value after having stopped the operation of the voltage boost circuit (vlcon = 0). p.671 ? these values above may change after device evaluation. p.671 ? vlcd: lcd boost level control register to use the internal voltage boosting method, specify the reference voltage by using the vlcd register (or perform a reset to use the default value of the reference voltage), wait for the reference voltage setup time (2 ms (min.)), and then set vlcon to 1. p.671 ? pfall: port function register for 78k0r/lf3, bits 3 and 7 must be set to 0. for 78k0r/lg3 and 78k0r/lh3, bit 7 must be set to 0. p.672 ? segen can be written only once after reset release. p.673 ? chapter 16 soft lcd controller/d river segen: segment enable register for 78k0r/lf3, bits 1 to 7 must be set to 0. for 78k0r/lg3, bits 2 to 7 must be set to 0. for 78k0r/lh3, bits 5 to 7 must be set to 0. p.673 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 983 jun 20, 2011 (27/39) chapter classification function details of function cautions page isc: input switch control register be sure to clear bits 5 to 7 to ?0?. p.674 ? internal voltage boosting method when stopping the operation of the voltage boost circuit circuit, be sure to set scoc and lcdon to 0 before setting vlcon to 0. p.679 ? capacitor spli t method when stopping the operation of the capacitor split circuit, be sure to set scoc and lcdon to 0 before setting vlcon to 0. p.680 ? external resistance division method to stabilize the potential of the v lc0 to v lc3 pins, it is recommended to connect a capacitor of about 0.1 f between each of the pins from v lc0 to v lc3 and the gnd pin as needed. pp.703 ,704 ? chapter 16 soft lcd controller/d river selection of lcd display data when the lcd display data memory is used when the number of time slices is eight, lcd display data (a-pattern, b-pattern, or blinking display) cannot be selected. p.706 ? do not rewrite the mdah and mdal values during division operation processing (while the multiplication/division control r egister (mduc) is 81h). the operation will be executed in this case, but the operation result will be an undefined value. p.711 ? mdah, mdal: multiplication/divi sion data register a the mdah and mdal values read duri ng division operation processing (while mduc is 81h) will not be guaranteed. p.711 ? do not rewrite the mdbh and mdbl values during division operation processing (while the multiplication/division contro l register (mduc) is 81h). the operation result will be an undefined value. p.711 ? mdbl, mdbh: multiplication/divi sion data register b do not set mdbh and mdbl to 0000h in the division mode. if they are set, the operation result will be an undefined value. p.711 ? mdcl, mdch: multiplication/divi sion data register c the mdch and mdcl values read during divi sion operation processing (while the multiplication/division control register (mduc) is 81h) will not be guaranteed. p.712 ? do not rewrite divmode during operation processing (while divst is 1). if it is rewritten, the operation result will be an undefined value. p.713 ? chapter 17 soft multiplier/d ivider mduc: multiplication/divi sion control register divst cannot be cleared (0) by using so ftware during division operation processing (while divst is 1). p.713 ? be sure to clear bits 15 to 10 to ?0?. p.720 ? dbcn: dma byte count register n if the general-purpose register is specified or the internal ram space is exceeded as a result of continuous transfer, the general- purpose register or sfr space are written or read, resulting in loss of data in these spaces. be sure to set the number of times of transfer that is within the internal ram space. p.720 ? the dstn flag is automatically cleared to 0 when a dma transfer is completed. writing the denn flag is enabled only when dstn = 0. when a dma transfer is terminated without waiting for generation of the interrupt (intdman) of dman, therefore, set dstn to 0 and then denn to 0 (for details, refer to 18.5.7 forced termination by software). p.723 ? drcn: dma operation control register n when the fsel bit of the osmc register has been set to 1, do not enable (denn = 1) dma operation for at least three clocks after the setting. p.723 ? holding dma transfer pending by dwaitn when dma transfer is held pending while using both dma channels, be sure to held the dma transfer pending for both channels (b y setting dwait0 and dwait1 to 1). if the dma transfer of one channel is executed while that of the other channel is held pending, dma transfer might not be held pending for the latter channel. p.735 ? chapter 18 soft dma controller forced termination of dma transfer in example 3, the system is not required to wait two clock cycles after the dwaitn bit is set to 1. in addition, the system does not have to wait two clock cycles after clearing the dstn bit to 0, because more than two clock cycles elapse from when the dstn bit is cleared to 0 to when the denn bit is cleared to 0. p.737 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 984 jun 20, 2011 (28/39) chapter classification function details of function cautions page soft priority during dma transfer, a request from the other dma channel is held pending even if generated. the pending dma transfer is started after the ongoing dma transfer is completed. if two dma requests are generated at the same time, however, dma channel 0 takes priority over dma channel 1. if a dma request and an interrupt request are generated at the same time, the dma transfer takes precedence, and then interrupt servicing is executed. p.738 ? hard response time the response time of dma tran sfer is as follows. (see table 18-2.) p.738 ? operation in standby mode the dma controller operates as follows in t he standby mode. (see table 18-3.) p.739 ? dma pending instruction even if a dma request is generated, dma tr ansfer is held pending immediately after the following instructions. ? call !addr16 ? call $!addr20 ? call !!addr20 ? call rp ? callt [addr5] ? brk ? bit manipulation instructions for register s if0l, if0h, if1l, if1h, if2l, if2h, mk0l, mk0h, mk1l, mk1h, mk2l, mk2h, pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, pr12h and psw each. p.739 ? chapter 18 soft dma controller operation if address in general-purpose register area or other than those of internal ram area is specified the address indicated by dra0n is incremented during dma transfer. if the address is incremented to an address in the general -purpose register area or exceeds the area of the internal ram, the following operation is performed. z in mode of transfer from sfr to ram the data of that address is lost. z in mode of transfer from ram to sfr undefined data is transferred to sfr. in either case, malfunctioning may occur or damage may be done to the system. therefore, make sure that the address is within the internal ram area other than the general-purpose register area. p.739 ? chapter 19 soft interrupt functions if0l, if0h, if1l, if1h, if2l, if2h: interrupt request flag registers when operating a timer, serial interface, or a/d converter after standby release, operate it once after clearing the interrupt r equest flag. an interrupt request flag may be set by noise. p.748 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 985 jun 20, 2011 (29/39) chapter classification function details of function cautions page when manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (clr1). w hen describing in c language, use a bit manipulation instruction such as ?if0l.0 = 0;? or ?_asm(?clr1 if0l, 0?);? because the compiled assembler must be a 1-bit me mory manipulation instruction (clr1). if a program is described in c language using an 8-bit memory manipulation instruction such as ?if0l &= 0xfe;? and compiled, it becomes the assembler of three instructions. mov a, if0l and a, #0feh mov if0l, a in this case, even if the request flag of another bit of the same interrupt request flag register (if0l) is set to 1 at the timing between ?mov a, if0l? and ?mov if0l, a?, the flag is cleared to 0 at ?mov if0l, a?. th erefore, care must be exercised when using an 8-bit memory manipulation instruction in c language. p.748 ? be sure to clear bits 5, 6 of if0h, bit 3 of if 1l, bit 3 of if1h, bits 5 to 7 of if2l, bits 0, 6, 7 of if2h to 0. (78k0r/lf3) p.749 ? be sure to clear bit 3 of if1h, bits 6, 7 of if2h to 0. (78k0r/lg3) p.750 ? if0l, if0h, if1l, if1h, if2l, if2h: interrupt request flag registers be sure to clear bits 6, 7 of if2h to 0. (78k0r/lh3) p.751 ? be sure to set bits 5, 6 of mk0h, bit 3 of mk1l, bit 3 of mk1h, bits 5 to 7 of mk2l, bits 0, 6, 7 of mk2h to 1. (78k0r/lf3) p.752 ? be sure to set bit 3 of mk1h, bits 6, 7 of mk2h to 1. (78k0r/lg3) p.753 ? mk0l, mk0h, mk1l, mk1h, mk2l, mk2h: interrupt mask flag registers be sure to set bits 6, 7 of mk2h to 1. (78k0r/lh3) p.754 ? be sure to set bits 5, 6 of pr00h and pr10h, bit 3 of pr01l and pr11l to 1. (78k0r/lf3) p.755 ? be sure to set bit 3 of pr01h and pr11h, bits 5 to 7 of pr02l and pr12l, bits 0, 6, 7 of pr02h and pr12h to 1. (78k0r/lf3) p.756 ? be sure to set bit 3 of pr01h and pr11h, bits 6, 7 of pr02h and pr12h to 1. (78k0r/lg3) p.757 ? pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, pr12h: priority specification flag registers be sure to set bits 6, 7 of pr02h and pr12h to 1. (78k0r/lh3) p.758 ? egp0, egp1: external interrupt rising edge enable registers, egn0, egn1: external interrupt falling edge enable registers select the port mode by clearing egpn and egnn to 0 because an edge may be detected when the external interrupt func tion is switched to the port function. p.762 ? chapter 19 soft interrupt functions software interrupt request acknowledgment do not use the reti instruction for restoring from the software interrupt. p.766 ? brk instruction the brk instruction is not one of the above-listed interrupt request hold instructions. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared. therefore, even if a maskable interrupt request is generated during execution of the brk instruction, the interrupt request is not acknowledged. p.770 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 986 jun 20, 2011 (30/39) chapter classification function details of function cautions page if any of the krm0 to krm7 bits used is set to 1, set bits 0 to 7 (pu70 to pu77) of the corresponding pull-up resistor register 7 (pu7) to 1. p.772 ? an interrupt will be generated if the target bit of the krm register is set while a low level is being input to the key interrupt input pin. to ignore this interrupt, set the krm register after disabling interrupt serv icing by using the interrupt mask flag. afterward, clear the interrupt request fl ag and enable interrupt servicing after waiting for the key interrupt input low-level width (250 ns or more). p.772 ? chapter 20 soft key interrupt function krm: key return mode register the bits not used in the key interrup t mode can be used as normal ports. p.772 ? the stop mode can be used only when the cpu is operating on the main system clock. the stop mode cannot be set while the cpu operates with the subsystem clock. the halt mode can be used when the cpu is operating on either the main system clock or the subsystem clock. p.773 ? when shifting to the stop mode, be sure to stop the peripheral hardware operation operating with main system clock bef ore executing stop instruction. p.773 ? the following sequence is recommended for operating current reduction of the a/d converter when the standby function is used: first clear bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0 to stop the a/d conversion operation, and then execute the stop instruction. p.773 ? it can be selected by the option byte whether the internal low-speed oscillator continues oscillating or stops in the halt or stop mode. for details, see chapter 26 option byte. p.773 ? ? the stop instruction cannot be executed when the cpu operates on the 20 mhz internal high-speed oscillation clock. be su re to execute the stop instruction after shifting to internal high-speed oscillation clock operation. p.773 ? after the above time has elapsed, the bits are set to 1 in order from most8 and remain 1. p.774 ? soft the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. p.774 ? hard ostc: oscillation stabilization time counter status register the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). p.774 ? to set the stop mode when the x1 clock is used as the cpu clock, set osts before executing the stop instruction. p.775 ? setting the oscillation stabilization time to 20 s or less is prohibited. p.775 ? before changing the setting of the osts regi ster, confirm that the count operation of the ostc register is completed. p.775 ? do not change the value of the osts register during the x1 clock oscillation stabilization time. p.775 ? chapter 21 soft standby function osts: oscillation stabilization time select register the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the stop mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc after stop mode is released. p.775 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 987 jun 20, 2011 (31/39) chapter classification function details of function cautions page hard osts: oscillation stabilization time select register the x1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (?a? below). p.775 ? because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if se t. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (osts) has elapsed. p.782 ? the stop instruction cannot be executed when the cpu operates on the 20 mhz internal high-speed oscillation clock. be su re to execute the stop instruction after shifting to internal high-speed oscillation clock operation. pp.782 , 784 ? to use the peripheral hardware that stops operation in the stop mode, and the peripheral hardware for which the clock that stops oscillating in the stop mode after the stop mode is released, restart the peripheral hardware. p.784 ? to stop the internal low-speed oscillation clock in the stop mode, use an option byte to stop the watchdog timer operation in the halt/stop mode (bit 0 (wdstbyon) of 000c0h = 0), and then execute the stop instruction. p.784 ? chapter 21 soft standby function stop mode to shorten oscillation stabilization time after the stop mode is released when the cpu operates with the high-speed system cl ock (x1 oscillation), temporarily switch the cpu clock to the internal high-speed oscillation clock before the next execution of the stop instruction. before changi ng the cpu clock from the internal high- speed oscillation clock to the high-speed system clock (x1 oscillation) after the stop mode is released, check the oscillation stabilization time with the oscillation stabilization time counter status register (ostc). p.784 ? for an external reset, input a low level for 10 s or more to the reset pin (to perform an external reset upon power application, a low level of at least 10 s must be continued during the period in which the supply voltage is within the operating range (v dd 1.8 v)). p.788 ? during reset input, the x1 clock, xt1 clock, internal high-speed oscillation clock, and internal low-speed oscillation clock stop osc illating. external main system clock input becomes invalid. p.788 ? when the stop mode is released by a reset, the ram contents in the stop mode are held during reset input. p.788 ? hard ? when reset is effected, port pin p140 is set to low-level output and other port pins become high-impedance, because each sfr and 2nd sfr are initialized. p.788 ? block diagram of reset function an lvi circuit internal reset doe s not reset the lvi circuit. p.790 ? watchdog timer overflow a watchdog timer internal reset resets the watchdog timer. p.790 ? do not read data by a 1-bit memory manipulation instruction. p.797 ? do not make a judgment based on only the read value of the resf register 8-bit data, because bits other than trap, wdrf, and lvirf become undefined. p.797 ? chapter 22 soft reset function resf: reset control flag register when the lvi default start function (bit 0 (lvioff) of 000c1h = 0) is used, lvirf flag may become 1 from the beginning depending on the power-on waveform. p.797 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 988 jun 20, 2011 (32/39) chapter classification function details of function cautions page if the low-voltage detector (lvi) is set to on by an option byte by default, the reset signal is not released until the supply voltage (v dd ) exceeds 2.07 v 0.2 v. pp.798, 799 ? ? if an internal reset signal is generated in the poc circuit, the reset control flag register (resf) is cleared to 00h. p.798 ? timing of generation of internal reset signal (lvioff = 1) set the low-voltage detector by software after the reset status is released (see chapter 24 low-voltage detector). p.800 ? timing of generation of internal reset signal (lvioff = 0) set the low-voltage detector by software after the reset status is released (see chapter 24 low-voltage detector). p.801 ? chapter 23 soft power-on- clear circuit cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v por , v pdr ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. p.802 ? soft to stop lvi, be sure to clear (0) lvio n by using a 1-bit memory manipulation instruction. p.807 ? hard input voltage from external input pin (exlvi) must be exlvi < v dd . p.807 ? lvim: low- voltage detection register when lvi is used in interrupt mode (lvimd = 0) and lvisel is set to 0, an interrupt request signal (intlvi) that disables lvi operation (clear s lvion) when the supply voltage (v dd ) is less than or equal to the detection voltage (v lvi ) (if lvisel = 1, input voltage of external input pin (exlvi) is le ss than or equal to the detection voltage (v exlvi )) is generated and lviif may be set to 1. p.807 ? be sure to clear bits 4 to 7 to ?0?. p.808 ? change the lvis value with either of the following methods. ? when changing the value after stopping lvi <1> stop lvi (lvion = 0). <2> change the lvis register. <3> set to the mode used as an interrupt (lvimd = 0). <4> mask lvi interrupts (lvimk = 1). <5> enable lvi operation (lvion = 1). <6> before cancelling the lvi interrupt mask (lvimk = 0), clear it with software because an lviif flag may be set when lvi operation is enabled. ? when changing the value after setting to the mode used as an interrupt (lvimd = 0) <1> mask lvi interrupts (lvimk = 1). <2> set to the mode used as an interrupt (lvimd = 0). <3> change the lvis register. <4> before cancelling the lvi interrupt mask (lvimk = 0), clear it with software because an lviif flag may be set when the lvis register is changed. p.809 ? chapter 24 soft low- voltage detector lvis: low- voltage detection level select register when an input voltage from the external input pin (exlvi) is detected, the detection voltage (v exlvi ) is fixed. therefore, setti ng of lvis is not necessary. p.809 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 989 jun 20, 2011 (33/39) chapter classification function details of function cautions page be sure to execute <1>. when lvimk = 0, an interrupt may occur immediately after the processing in <4>. p.811 ? used as reset (when detecting level of supply voltage (v dd )) (lvioff = 1) if supply voltage (v dd ) detection voltage (v lvi ) when lvimd is set to 1, an internal reset signal is not generated. p.811 ? used as reset (when detecting level of supply voltage (v dd )) (lvioff = 0) even when the lvi default start function is used, if it is set to lvi operation prohibition by the software, it operates as follows: ? does not perform low-voltage detection during lvion = 0. ? if a reset is generated while lvion = 0, lvion will be re-set to 1 when the cpu starts after reset release. there is a period when low-voltage detection cannot be performed normally, however, when a reset occurs due to wdt and illegal instruction execution. this is due to the fact that while the pulse width detected by lvi must be 200 s max., lvion = 1 is set upon reset occurrence, and the cpu starts operating without waiting for the lvi stabilization time. p.812 ? be sure to execute <1>. when lvimk = 0, an interrupt may occur immediately after the processing in <3>. p.813 ? soft if input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.)) when lvimd is set to 1, an internal reset signal is not generated. p.813 ? hard used as reset (when detecting level of input voltage from external input pin (exlvi)) input voltage from external input pin (exlvi) must be exlvi < v dd . p.813 ? even when the lvi default start function is used, if it is set to lvi operation prohibition by the software, it operates as follows: ? does not perform low-voltage detection during lvion = 0. ? if a reset is generated while lvion = 0, lvion will be re-set to 1 when the cpu starts after reset release. there is a period when low-voltage detection cannot be performed normally, however, when a reset occurs due to wdt and illegal instruction execution. this is due to the fact that while the pulse width detected by lvi must be 200 s max., lvion = 1 is set upon reset occurrence, and the cpu starts operating without waiting for the lvi stabilization time. p.819 ? soft used as interrupt (when detecting level of supply voltage (v dd )) (lvioff = 0) when the lvi default start function (bit 0 (lvioff) of 000c1h = 0) is used, the lvirf flag may become 1 from the beginning due to the power-on waveform. for details of resf, see chapter 22 reset function. p.819 ? chapter 24 hard low- voltage detector used as interrupt (when detecting level of input voltage from external input pin (exlvi)) input voltage from the external input pin (exlvi) must be exlvi < v dd . p.821 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 990 jun 20, 2011 (34/39) chapter classification function details of function cautions page soft in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. operation example 1: when used as reset the system may be repeatedly reset and released from the reset status. the time from reset release through microcontroller operation start can be set arbitrarily by the following action. after releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports (see figure 24-11). operation example 2: when used as interrupt interrupt requests may be generated frequently. take the following action. confirm that ?supply voltage (v dd ) detection voltage (v lvi )? when detecting the falling edge of v dd , or ?supply voltage (v dd ) < detection voltage (v lvi )? when detecting the rising edge of v dd , in the servicing routine of the lvi interrupt by using bit 0 (lvif) of the low-voltage detection register (lvim). clear bit 1 (lviif) of interrupt request flag register 0l (if0l) to 0. for a system with a long supply voltage fl uctuation period near the lvi detection voltage, take the above action after waiti ng for the supply voltage fluctuation time. pp.823 to 825 ? chapter 24 hard low- voltage detector cautions for low- voltage detector there is some delay from the time supply voltage (v dd ) < lvi detection voltage (v lvi ) until the time lvi reset has been generated. in the same way, there is also some delay from the time lvi detection voltage (v lvi ) supply voltage (v dd ) until the time lvi reset has been released (see figure 24-12 ) . p.825 ? the rmc register can be rewritten only in the low-power consumption mode (refer to table 25-1). in other words, rewrite this register during cpu operation with the subsystem clock (f xt ) while the high-speed system clock (f mx ), the high-speed internal oscillation clock, and the 20 mhz internal high-speed oscillation clock (f ih20 ) are both stopped. p.827 ? when using the setting fixed to the low consumption current mode, the rmc register can be used in the following cases. f clk 1 mhz and external oscillator (x1 clock (f x ), external main system clock (f ex )) stop.. f clk 1 mhz, f x /f ex 5 mhz and the internal high-speed oscillator stop. both the internal high-speed oscillator and external oscillator (f x /f ex 5 mhz) stop or either one stops. p.827 ? chapter 25 soft regulator rmc: regulator mode control register in low-power consumption mode, use the regulator with f clk fixed to 1 mhz when executing self programming. p.828 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 991 jun 20, 2011 (35/39) chapter classification function details of function cautions page chapter 25 soft regulator rmc: regulator mode control register a wait is required to change the operation speed mode control register (osmc) after changing the rmc register. wait for 2 ms by software when setting to low-power consumption mode and 10 s when setting to normal power mode, as described in the procedure shown below. ? when setting to low-power consumption mode <1> select a frequency of 1 mhz for f clk . <2> set rmc to 5ah (set the regulator to low-power consumption mode). <3> wait for 2 ms. <4> set flpc and fsel of osmc to 1 and 0, respectively. ? when setting to normal power mode <1> set rmc to 00h (set the regulator to normal power mode). <2> wait for 10 s. <3> change flpc and fsel of osmc. <4> change the f clk frequency. p.828 ? 000c2h/010c2h be sure to set ffh to 000c2h (000c2h/010c2h when the boot swap operation is used). p.829 ? 000c0h/010c0h set the same value as 000c0h to 010c0h when the boot swap operation is used because 000c0h is replaced by 010c0h. p.829 ? 000c1h/010c1h set the same value as 000c1h to 010c1h when the boot swap operation is used because 000c1h is replaced by 010c1h. p.829 ? 000c2h/010c2h set ffh to 010c2h when the boot swap operation is used because 000c2h is replaced by 010c2h. p.829 ? 000c3h/010c3h set the same value as 000c3h to 010c3h when the boot swap operation is used because 000c3h is replaced by 010c3h. p.830 ? 000c0h/010c0h the watchdog timer continues its oper ation during self-programming of the flash memory and eeprom emulation. during processing, the interrupt acknowledge time is delayed. set the overflow time and window size taking this delay into consideration. p.831 ? be sure to set bits 7 to 3 to ?1?. p.832 ? 000c1h/010c1h even when the lvi default start function is used, if it is set to lvi operation prohibition by the software, it operates as follows: ? does not perform low-voltage detection during lvion = 0. ? if a reset is generated while lvion = 0, lvion will be re-set to 1 when the cpu starts after reset release. there is a period when low-voltage detection cannot be performed normally, however, when a reset occurs due to wdt and illegal instruction execution. this is due to the fact that while the pulse width detected by lvi must be 200 s max., lvion = 1 is set upon reset occurrence, and the cpu starts operating without waiting for the lvi stabilization time. p.832 ? 000c3h/010c3h bits 7 and 0 (ocdenset and ocde rsd) can only be specified a value. be sure to set 000010b to bits 6 to 1. p.832 ? chapter 26 soft option byte setting of option byte to specify the option byte by using assembly language, use opt_byte as the relocation attribute name of the cseg pseudo instruction. to specify the option byte to 010c0h to 010c3h in order to use the boot swap function, use the relocation attribute at to specify an absolute address. p.833 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 992 jun 20, 2011 (36/39) chapter classification function details of function cautions page after the security setting for the batch erase is set, erasure cannot be performed for the device. in addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be written, because the erase command is disabled. p.843 ? security settings if a security setting that rewrites boot cluster 0 has been applied, boot cluster 0 of that device will not be rewritten, and the ent ire flash memory of the device will not be erased in batch. p.843 ? hard the self-programming function cannot be used when the cpu operates with the subsystem clock. p.845 ? in the self-programming mode, call the self-programming start library (flashstart). p.845 ? to prohibit an interrupt during self-programming, in the same way as in the normal operation mode, execute the self-programming library in the state where the ie flag is cleared (0) by the di instruction. to enable an interrupt, clear (0) the interrupt mask flag to accept in the state where the ie flag is set (1) by the ei instruction, and then execute the self-programming library. p.845 ? in low-power-consumption mode, use the regulator with f clk fixed to 1 mhz when executing self programming. for details of the low-power-consumption mode, see chapter 25 regulator. p.845 ? flash memory programming by self- programming disable dma operation (denn = 0) during t he execution of self programming library functions. p.845 ? chapter 27 soft flash memory flash shield window function if the rewrite-prohibited area of the boot cl uster 0 overlaps with the flash shield window range, prohibition to rewrite the boot cluster 0 takes priority. p.849 ? chapter 28 hard on-chip debug function connecting qb- mini2 to 78k0r/lx3 the 78k0r/lx3 microcontrollers have an on -chip debug function, which is provided for development and evaluation. do not us e the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. p.851 ? addition the value read from the bcdadj r egister varies depending on the value of the a register when it is read and those of the cy and ac flags. therefore, execute the instruction <3> after the instruction <2> instead of executing any other instructions. to perform bcd correction in the interrupt enabled state, saving and restoring the a register is required within the interrupt function. psw (cy flag and ac flag) is restored by the reti instruction. p.855 ? chapter 29 soft bcd correction circuit subtraction the value read from the bcdadj register varies depending on the value of the a register when it is read and those of the cy and ac flags. therefore, execute the instruction <3> after the instruction <2> instead of executing any other instructions. to perform bcd correction in the interrupt enabled state, saving and restoring the a register is required within the interrupt function. psw (cy flag and ac flag) is restored by the reti instruction. p.856 ? chapter 30 soft instruction set prefix instruction set the es register value with mov es, a, etc., before executing the prefix instruction. p.859 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 993 jun 20, 2011 (37/39) chapter classification function details of function cautions page the 78k0r/lx3 microcontrollers have an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. p.877 ? ? the pins mounted depend on the product. refe r to 1.3 pin configuration (top view) and chapter 2 pin functions. p.877 ? pp.878 ? product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is , the absolute maximum ratings are rated values at which the product is on t he verge of suffering physical damage, and therefore the product must be used under c onditions that ensure that the absolute maximum ratings are not exceeded. to 880 absolute maximum ratings the value of the current that can be run per pin must satisfy the value of the current per pin and the total value of the currents of all pins. pp.879 ? p.880 ? when using the x1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal li ne through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. p.880 ? x1 oscillator characteristics since the cpu is started by the internal high-speed oscillation clock after a reset release, check the x1 clock oscillation stabilization time using the oscillation stabilization time counter status register (ostc) by the user. determine the oscillation stabilization time of the ostc register and oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. p.881 ? when using the xt1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adv erse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal li ne through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. p.881 ? xt1 oscillator characteristics the xt1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfuncti on due to noise than the x1 oscillator. particular care is therefore required with the wiring method when the xt1 clock is used. chapter 31 hard electrical specifications recommended oscillator circuit constants the oscillator constants shown above are re ference values based on evaluation in a specific environment by the resonator manufacturer. if it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circui t. the oscillation voltage and oscillation frequency only indicate the oscillator characteristic. use the 78k0r/lx3 so that the internal operation conditions are within the specifications of the dc and ac characteristics. pp.882 , 883 ?
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 994 jun 20, 2011 (38/39) chapter classification function details of function cautions page pp.885, ? p10 to p15, p75, p77, p80 and p82 do not output high level in n-ch open-drain mode. 890 hard dc characteristics the maximum value of v ih of pins p10 to p15, p75, p77, p80 and p82 is v dd , even in the n-ch open-drain mode. p.887 ? minimum instruction execution time during main system clock operation when v dd < 2.25 v and fsel = 1, it is prohibited to release stop mode during f ex operation or f ih operation (this must not be performed even if the frequency is divided. the stop mode may be released during f x operation.). p.898 ? during communication at same potential (uart mode) (dedicated baud rate generator output) select the normal input buffer for rxdq and the normal output mode for txdq by using the pimg and pomx registers. p.902 ? during communication at same potential (csi mode) (master mode, sckp... internal clock output) select the normal input buffer for sip and the normal output mode for sop and sckp by using the pimg and pomx registers. p.903 ? during communication at same potential (csi mode) (slave mode, sckp... external clock input) select the normal input buffer for sip and sckp and the normal output mode for sop by using the pimg and pomx registers. p.904 ? during communication at same potential (simplified i 2 c mode) select the normal input buffer and the n-ch open drain output (v dd tolerance) mode for sdar and the normal output mode for sclr by using the pimg and pomx registers. p.906 ? pp.908, ? chapter 31 soft electrical specifications during communication at different potential (2.5 v, 3 v) (uart mode) (dedicated baud rate generator output) select the ttl input buffer for rxdq and the n-ch open drain output (v dd tolerance) mode for txdq by using the pimg and pomx registers. 909, 911
78k0r/lx3 appendix c list of cautions r01uh0004ej0501 rev.5.01 995 jun 20, 2011 (39/39) chapter classification function details of function cautions page pp.912 ? during communication at different potential (2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) select the ttl input buffer for sip and the n-ch open drain output (v dd tolerance) mode for sop and sckp by using the pimg and pomx registers. to 914 pp.916, ? during communication at different potential (2.5 v, 3 v) (csi mode) (slave mode, sckp... external clock input) select the ttl input buffer for sip and sckp and the n-ch open drain output (v dd tolerance) mode for sop by using the pimg and pomx registers. 917 soft during communication at different potential (2.5 v, 3 v) (simplified i 2 c mode) select the ttl input buffer and the n-ch open drain output (v dd tolerance) mode for sdar and the n-ch open drain output (v dd tolerance) mode for sclr by using the pimg and pomx registers. pp.918, 919 ? chapter 31 hard electrical specifications vr circuit connect the v refout pin to gnd via a tantalum capacitor (capacitance: 10 f 30 %, esr: 2 (max.), esl: 10 nh (max.)) and a ceramic capacitor (capacitance: 0.1 f 30 %, esr: 2 (max.), esl: 10 nh (max.)). p.923 ? chapter 33 hard recommended soldering condition ? the pd78f1500a to 78f1508a have an on-c hip debug function, which is provided for development and evaluation. do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. pp.938, 939 ?
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 996 jun 20, 2011 appendix d revision history d.1 major revisions in this edition (1/3) remark ?classification? in the above table classifies revisions as follows. (a): error correction, (b): addition/change of specif ications, (c): addition/change of description or note, (d): addition/change of package, part number, or man agement division, (e): a ddition/change of related documents page description classification major revisions in rev.5.01 chapter 3 cpu architecture p.95 deletion of note of analog reference voltage control register (advrc) (a) chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) p.387, 395 change of the selectable bit in analog referenc e voltage control register (advrc) for pd78f151xa to only the vrgv bit (a) chapter 23 power-on-clear circuit throughout deletion of note of preliminary values (c) chapter 24 low-voltage detector throughout deletion of note of preliminary values (c) major revisions in rev.5.00 throughout ? addition of 78f1510a and 78f1512a to 78k0r/lf3 product series (d) ? addition of 78f1513a and 78f1515a to 78k0r/lg3 product series (d) ? addition of 78f1516a and 78f1518a to 78k0r/lh3 product series (d) chapter 1 outline p.2 addition of 10-bit resolu tion a/d conversion ( pd78f151xa only) addition of ( pd78f150xa only) to 12-bit resolution a/d conversion, 12-bit resolution d/a converter, operational amplifier, and on -chip voltage reference (2.0 v/2.5v) (d) pp.4 to 5, 7 to 8, 10 to 11 separation of (1) pd78f150xa and (2) pd78f151xa from each pin configuration (d) pp.6, 9, 12 addition of av ref , av dd , and ev dd1 to each pin identification (d) pp.13 to 18 separation of (1) pd78f150xa and (2) pd78f151xa from each block diagram (d) pp.19 to 22 separation of (1) pd78f150xa and (2) pd78f151xa in 1.5 outline of functions (d) chapter 2 pin functions pp.23, 62 addition of av dd and ev dd1 (d) pp.24 to 26, 29 to 32, 35 to 38, 42 to 44, 47 to 56, 60 to 63, 65, 66, 68 addition of notes (d) pp.43 to 44, 47 to 56 literal change of 78k0r/lf3 series; from 78f1500a and 78f1502a to 78f15x0a and 78f15x2a literal change of 78k0r/lg3 series; from 78f1503a and 78f1505a to 78f15x3a and 78f15x5a literal change of 78k0r/lh3 series; from 78f1506a and 78f1508a to 78f15x6a and 78f15x8a (d) p.46 addition of pd78f151xa to table in 2.2.3 p20 to p27 (d) p.54 addition of pd78f151xa to table in 2.2.12 p110 to p111 (d) p.57 addition of pd78f151xa to table in 2.2.16 p150 to p152, p157 (d) p.58 addition of ( pd78f150xa only) to 2. 2. 20 v refout /av refp addition of 2.2.21 av ref ( pd78f151xa only) (d)
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 997 jun 20, 2011 (2/3) remark ?classification? in the above table classifies revisions as follows. (a): error correction, (b): addition/change of specif ications, (c): addition/change of description or note, (d): addition/change of package, part number, or man agement division, (e): a ddition/change of related documents page description classification chapter 3 cpu architecture (continuation) p.59 addition of ( pd78f150xa only) to (1) av dd0 and (2) av dd1 addition of (3) av dd ( pd78f151xa only) and (4) ev dd1 ( pd78f151xa only) (d) p.69 addition of type 5 (d) chapter 3 cpu architecture p.74 addition of 78f1510a, 78f1513a, and 78f1516 to figure 3-1. memory map (d) p.76 addition of 78f1512a, 78f1515a, and 78f1518a to figure 3-3. memory map (d) p.78 addition of 78f1510a, 78f1513a, 78f1516 and 78f1512a, 78f1515a, 78f1518a to remark below table 3-1. correspondence between address values and block numbers in flash memory (d) p.79 addition of 78f1510a, 78f1513a, 78f1516 and 78f1512a, 78f1515a, 78f1518a to table 3-2. internal rom capacity (d) p.81 addition of 78f1510a, 78f1513a, 78f1516 and 78f1512a, 78f1515a, 78f1518a to 3.1.2 mirror area (d) p.82 addition of 78f1510a, 78f1513a, and 78f1516 to example 1 and 78f1512a, 78f1515a, and 78f1518a to example 2 (d) p.83 addition of 78f1510a, 78f1513a, 78f1516 and 78f1512a, 78f1515a, and 78f1518a to table 3- 4. internal ram capacity (d) p.85 addition of 78f1510a, 78f1513a, and 78f1516a to figure 3-5. correspondence between data memory and addressing (d) p.87 addition of 78f1512a, 78f1515a, and 78f1518a to figure 3-7. correspondence between data memory and addressing (d) pp.94 to 95 addition of note to table 3-5. sfr list (d) chapter 4 port functions p.121 addition of av dd and ev dd1 (d) pp.122 to 128 addition of notes (d) p.138 addition of pd78f151xa to table in 4.2.3 port 2 (d) p.167 addition of pd78f151xa to table in 4.2.12 port 11 (d) p.176 addition of pd78f151xa to table in 4.2.16 port 15 (d) chapter 10 12-bit a/d converter ( pd78f150xa), 10-bit a/d converter ( pd78f151xa) p.385 change of chapter title addition of pd78f151xa to table addition of description of 10-bit resoluti on to 10.1 function of a/d converter (d) p.387 addition of figure 10 ? 2. block diagram of 10-bit a/d converter ( pd78f151xa) (d) p.389 addition of 10-bit conversi on result register to (6) addition of av dd to (9) addition of av ref to (13) (d) p.390 addition of 10-bit conver sion result register to 10.3 registers used in a/d converter (d) p.395 addition of ( pd78f150xa only) to (4) analog reference voltage control register (advrc) (d) p.396 addition of ( pd78f150xa only) to (5) 12-bit a/d conversion result register (adcr) (d) p.397 addition of ( pd78f150xa only) to (6) 10-bit a/d conversion result register (adcr) (d) p.412 change of value of 1lsb in 10.5 (1) resolution (a)
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 998 jun 20, 2011 (3/3) remark ?classification? in the above table classifies revisions as follows. (a): error correction, (b): addition/change of specif ications, (c): addition/change of description or note, (d): addition/change of package, part number, or man agement division, (e): a ddition/change of related documents page description classification chapter 11 d/a converter ( pd78f150xa only) p.418 addition of ( pd78f150xa only) to chapter title (d) chapter 12 operational amplifier ( pd78f150xa only) p.425 addition of ( pd78f150xa only) to chapter title (d) chapter 13 voltage reference ( pd78f150xa only) p.434 addition of ( pd78f150xa only) to chapter title (d) chapter 31 electrical specifications throughout addition of specifications of av dd , ev dd1 , and av ref (d) pp.892, 893 addition of amphs1 = 1 to conditions of supply current when f sub = 32.768 khz (b) p.894 separation of pd78f150xa and pd78f151xa in p110, p111 of i adc conditions (d) p.922 addition of ( pd78f150xa only) to (1) 12-bit a/d converter (d) p.923 addition of ( pd78f150xa only) to (2) 10-bit a/d converter addition of ( pd78f150xa only) to (3) operational amplifier addition of ( pd78f150xa only) to (4) voltage reference (d) p.924 addition of ( pd78f150xa only) to (5) d/a converter (d) chapter 32 package drawings pp.934, 935 addition of 78f1510agc-gad-ax and 78f1512agc -gad-ax to 78k0r/lf3 product series (d) p.936 addition of 78f1513agc-ueu-ax and 78f1515agc-ueu-ax to 78k0r/lf3 product series (d) p.937 addition of 78f1516agf-gat-ax and 78f1518agf -gat-ax to 78k0r/lh3 product series (d) chapter 33 recommended soldering conditions p.938 addition of 78f1510agc-gad-ax and 78f1512agc-gad-ax to 80 pins addition of 78f1513agc-ueu-ax and 78f1515agc-ueu-ax to 100 pins addition of 78f1516agf-gat-ax and 78f1518agf-gat-ax to 128 pins change of caution: from ? pd78f1503a to 78f1508a? to 78k0r/lx3 (d) p.939 addition of 78f1510agc-gad-ax and 78f1512a gc-gad-ax to 80 pins (14 x14) change of caution: from ? pd78f1503a to 78f1508a? to 78k0r/lx3 (d)
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 999 jun 20, 2011 d.2 revision history of preceding editions here is the revision history of the preceding editi ons. chapter indicates the chapter of each edition. (1/14) edition description chapter modification of regulator output voltage of normal power mode addition of timer array unit 1 throughout modification of related documents introduction addition of 1.1 features modification of 1.3.3 78k0r/lh3 modification of 1.4.1 78k0r/lf3, 1.4.2 78k0r/lg3, and 1.4.3 78k0r/lh3 modification of 1.5 outline of functions chapter 1 outline modification of 2.1.3 78k0r/lh3 addition of 2.2 description of pin functions modification of 2.3 pin i/o circuits and recommended connection of unused pins chapter 2 pin functions modification of table 3-3 vector table modification of 3.2.4 special function registers (sfrs) modification of 3.2.5 extended special function registers (2nd sfrs: 2nd special function registers) chapter 3 cpu architecture modification of table 4-4 port functions (78k0r/lh3) modification of 4.2 port configuration addition of (7) port function register (pfall) and (8) input switch control register (isc) to 4.3 registers controlling port function addition of 4.5 settings of port mode register and output latch when using alternate function chapter 4 port functions modification of figure 5-1 block diagram of clock generator modification of figure 5-2 format of clock operation mode control register (cmc) addition of note 2 and modification of caution 1 in figure 5-6. format of system clock control register (ckc) modification of table 5-3 relationship between cpu clock and minimum instruction execution time modification of figure 5-7 format of peripheral enable register 0 (per0) modification of figure 5-8 format of operation speed mode control register (osmc) modification of caution 1 in figure 5-9 example of external circuit of x1 oscillator and figure 5-10 example of external circuit of xt1 oscillator (crystal oscillation) modification of figure 5-12 clock generator operation when power supply voltage is turned on (when lvi default start function stopped is set (option byte: lvioff = 1)) and figure 5-13 clock generator operation when power supply voltage is turned on (when lvi default start function enabled is set (option byte: lvioff = 0)) 2nd edition modification of 5.6.1 example of controlling high-speed system clock , 5.6.2 example of controlling internal high-speed oscillation clock , and 5.6.3 example of controlling subsystem clock chapter 5 clock generator
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 1000 jun 20, 2011 (2/14) edition description chapter modification of table 5-5 changing cpu clock modification of table 5-6 maximum time required for main system clock switchover, f subc ? f subc , table 5-7 maximum number of clocks required in f mainc ? f mainc (changing the division ratio) , f subc ? f subc (changing the division ratio) , and table 5-9 maximum number of clocks required in f mainc ? f subc chapter 5 clock generator (continuation) addition of chapter chapter 6 timer array unit modification of table 7-1 configuration of real-time counter modification of figure 7-1 block diagram of real-time counter modification of figure 7-2 format of peripheral enable register 0 (per0) modification of figure 7-3 format of real-time counter control register 0 (rtcc0) modification of figure 7-4 format of real-time counter control register 1 (rtcc1) addition of caution 3 to figure 7-5 format of real-time counter control register 2 (rtcc2) modification of (7) minute count register (min) to (9) day count register (day) modification of (11) month count register (month) to (13) watch error correction register (subcud) addition of (17) port mode register 3 (pm3) modification of note 2 in figure 7-19 procedure for starting operation of real- time counter addition of 7.4.2 shifting to stop mode after starting operation addition of 7.4.8 example of watch error correction of real-time counter chapter 7 real- time counter modification of figure 10-1 block diagram of a/d converter modification of figure 10-3 format of peripheral enable register 0 (per0) addition of note 1 to figure 10-4 format of a/d converter mode register (adm) addition of table 10-2 a/d conversion time selection modification of (4) analog reference voltage control register (advrc) modification of figure 10-10 format of 8-bit a/d conversion result register (adcrh) modification of table 10-4. setting functions of ani0/amp0-/p20, ani2/amp0+/p22, ani3/amp1-/p23, ani5/amp1+/p25, ani6/amp2-/p26, and ani8/amp2+/p150 pins , table 10-5. setting functions of ani1/amp0o/p21, ani4/amp1o/p24, and ani7/amp2o/p27 pins , and table 10-7. setting functions of ani15/av refm/ p157 pin addition of (12) rewriting dacswn during a/d conversion to 10.6 cautions for a/d converter chapter 10 a/d converter modification of figure 11-1 block diagram of d/a converter modification of figure 11-2 format of peripheral enable register 0 (per0) modification of remark in figure 11-3 format of d/a converter mode register (dam) addition of caution to figure 11-4 format of d/a conversion value setting registers w0 and w1 (dacsw0, dacsw1) addition of <1> to 11.4.1 operation in normal mode and 11.4.2 operation in real- time output mode 2nd edition addition of (3) to 11.5 cautions for d/a converter chapter 11 d/a converter
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 1001 jun 20, 2011 (3/14) edition description chapter modification of table 12-1 configuration of operational amplifiers addition of (1) peripheral enable register 0 (per0) modification of table 12-2 setting functions of ani0/amp0-/p20, ani2/amp0+/p22, ani3/amp1-/p23, ani5/amp1+/p25, ani6/amp2-/p26, and ani8/amp2+/p150 pins table 12-3 setting functions of ani1/amp0o/p21, ani4/amp1o/p24, and ani7/amp2o/p27 pins, and table 12-5 setting functions of ani15/av refm /p157 pin addition of <1> to 12.4.1 single amp mode chapter 12 operational amplifier modification of table 13-1 configuration of voltage reference modification of figure 13-1 block diagram of voltage reference addition of (1) peripheral enable register 0 (per0) modification of (2) a/d reference voltage control register (advrc) modification of 13.4.1 reference voltage output mode chapter 13 voltage reference modification of figure 14-4 format of peripheral enable register 0 (per0) modification of caution 2 in figure 14-5 format of serial clock select register m (spsm) modification of figure 14-22 peripheral enable register 0 (per0) setting when stopping the operation by units modification of caution in figure 14-25 initial setting procedure for master transmission modification of caution in figure 14-29 flowchart of master transmission (in single-transmission mode) modification of caution in figure 14-31 flowchart of master transmission (in continuous transmission mode) modification of caution in figure 14-33 initial setting procedure for master reception modification of caution in figure 14-37 flowchart of master reception (in single- reception mode) modification of caution in figure 14-39 initial setting procedure for master transmission/reception modification of caution in figure 14-43 flowchart of master transmission/reception (in single- transmission/reception mode) modification of caution in figure 14-45 flowchart of master transmission/reception (in continuous transmission/reception mode) modification of caution in figure 14-47 initial setting procedure for slave transmission modification of caution in figure 14-51 flowchart of slave transmission (in single-transmission mode) modification of caution in figure 14-53 flowchart of slave transmission (in continuous transmission mode) modification of caution in figure 14-55 initial setting procedure for slave reception modification of caution in figure 14-59 flowchart of slave reception (in single- reception mode) modification of caution in figure 14-61 initial setting procedure for slave transmission/reception 2nd edition modification of caution in figure 14-65 flowchart of slave transmission/reception (in single- transmission/reception mode) chapter 14 serial array unit
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 1002 jun 20, 2011 (4/14) edition description chapter modification of caution in figure 14-67 flowchart of slave transmission/reception (in continuous transmission/reception mode) modification of caution in figure 14-69 initial setting procedure for uart transmission modification of caution in figure 14-73 flowchart of uart transmission (in single-transmission mode) modification of caution in figure 14-75 flowchart of uart transmission (in continuous transmission mode) modification of caution in figure 14-77 initial setting procedure for uart reception modification of caution in figure 14-81 flowchart of uart reception modification of caution in figure 14-89 initial setting procedure for address field transmission chapter 14 serial array unit (continuation) modification of figure 15-5 format of peripheral enable register 0 (per0) addition of 15.4.2 setting transfer clock by using iicwl and iicwh registers addition of caution to 15.5.7 canceling wait modification of table 15-3 bit definitions of main extension code modification of figure 15-23 flow when setting wup = 0 upon address match (including extension code reception) to figure 15-25 when operating as slave device after releasing stop mode other than by intiica (when not required to operate as master device) modification of figure 15-33 example of master to slave communication and figure 15-34 example of slave to master communication chapter 15 serial interface iica modification of figure 16-1 block diagram of lcd controller/driver modification of figure 16-5 format of lcd boost level control register (vlcd) addition of caution 1 to figure 16-7 format of segment enable register (segen) modification of figure 16-33 examples of lcd drive power connections (internal voltage boosting method) chapter 16 lcd controller/driver modification of figure 17-4 format of multiplication/division data register c (mdch, mdcl) chapter 17 multiplier/divider modification of table 18-2 response time of dma transfer chapter 18 dma controller modification of maskable interrupts modification of table 19-1 interrupt source list modification of figure 19-1 basic configuration of interrupt function modification of table 19-2 flags corresponding to interrupt request sources modification of figure 19-2 format of interrupt request flag registers (if0l, if0h, if1l, if1h, if2l, if2h) (78k0r/lf3) to figure 19-4 format of interrupt request flag registers (if0l, if0h, if1l, if1h, if2l, if2h) (78k0r/lh3) modification of figure 19-5 format of interrupt mask flag registers (mk0l, mk0h, mk1l, mk1h, mk2l, mk2h) (78k0r/lf3) to figure 19-7 format of interrupt mask flag registers (mk0l, mk0h, mk1l, mk1h, mk2l, mk2h) (78k0r/lh3) 2nd edition modification of figure 19-8 format of priori ty specification flag registers (pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, pr12h) (78k0r/lf3) to figure 19-10 format of priority specification flag registers (pr00l, pr00h, pr01l, pr01h, pr02l, pr02h, pr10l, pr10h, pr11l, pr11h, pr12l, pr12h) (78k0r/lh3) chapter 19 interrupt functions
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 1003 jun 20, 2011 (5/14) edition description chapter modification of caution 2 in figure 20-2 format of key return mode register (krm) chapter 20 key interrupt function addition of table 21-1 operating statuses in halt mode (3/3) modification of note in figure 21-3 halt mode release by interrupt request generation modification of figure 21-4 halt mode release by reset modification of figure 21-5 operation timing when stop mode is released (when unmasked interrupt request is generated) modification of figure 21-6 stop mode release by interrupt request generation modification of figure 21-7 stop mode release by reset chapter 21 standby function modification of figure 22-2 timing of reset by reset input to figure 22-4 timing of reset in stop mode by reset input modification of table 22-1 operation statuses during reset period modification of table 22-2 hardware statuses after reset acknowledgment chapter 22 reset function modification of figure 23-2 timing of generation of internal reset signal by power-on-clear circuit and low-voltage detector chapter 23 power- on-clear circuit modification of caution 1 in figure 24-2 format of low-voltage detection register (lvim) modification of 24.4.1 when used as reset ? when stopping operation modification of 24.4.2 when used as interrupt ? when stopping operation chapter 24 low- voltage detector modification of cautions 1, 2 in figure 25-1 format of regulator mode control register (rmc) chapter 25 regulator modification of caution 4 in 27.8 flash memory programming by self- programming chapter 27 flash memory absolute maximum ratings ? modification of output voltage (v o4 ), output current, high (i oh3 ), output current, low (i ol3 ) dc characteristics ? modification of output current, high (i oh2 ), output current, low (i ol2 ), output voltage, high (v oh2 ), output voltage, low (v ol2 ), supply current (i dd2 ), a/d converter operating current (i adc ), operational amplifier operating current (i amp ), voltage reference operating current (i vr ), lcd operating current (i lcd2 , i lcd3 ) (1) basic operation in ac characteristics ? modification of instruction cycle ? addition of note ? modification of minimum instruction execution time during main system clock operation (fsel = 0, rmc = 00h) to minimum instruction execution time during self programming mode (rmc = 00h) ? addition of minimum instruction execution time during self programming mode (rmc = 5ah) 2nd edition (2) serial interface: serial array unit in ac characteristics ? modification of (d) data hold time (transmission) in during communication at same potential (simplified i 2 c mode) ? modification of (h) data hold time (transmission) in communication at different potential (2.5 v, 3 v) (simplified i 2 c mode) chapter 31 electrical specifications (target)
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 1004 jun 20, 2011 (6/14) edition description chapter (3) serial interface: iica in ac characteristics ? modification of table (3) voltage reference in analog characteristics ? addition of remark (4) d/a converter in analog characteristics ? addition of gain error (eg) (2) internal voltage boosting method in lcd characteristics ? modification of lcd output voltage variation range (3) capacitor split method in lcd characteristics ? modification of v lc0 voltage chapter 31 electrical specifications (target) (continuation) addition of chapter appendix a development tools 2nd edition addition of chapter appendix b revision history df781508, qb-78k0rlx3: under development under mass production throughout addition of qb-programmer programming gui operation user?s manual to related documents introduction modification of 1.1 features chapter 1 outline modification of 2.2.21 reset and 2.2.22 regc chapter 2 pin functions addition of note 1 to figure 3-1 memory map ( pd78f1500, 78f1503, 78f1506) addition of note 1 to figure 3-2 memory map ( pd78f1501, 78f1504, 78f1507) addition of note 1 to and modification of figure 3-3 memory map ( pd78f1502, 78f1505, 78f1508) modification of description in 3.1.1 (1) vector table area modification of 3.1.2 mirror area modification of description in and addition of cautions 1, 2 to 3.1.3 internal data memory space modification of figure 3-7 correspondence between data memory and addressing ( pd78f1502, 78f1505, 78f1508) addition of cautions 2, 3 to 3.2.1 (3) stack pointer (sp) chapter 3 cpu architecture modification of figure 4-1 block diagram of p00 and p01 modification of figure 4-2 block diagram of p02 chapter 4 port functions modification of figure 5-6 format of system clock control register (ckc) modification of <2> in 5.6.2 (2) example of setting procedure when using internal high-speed oscillation clock as cpu/peripheral hardware clock modification of table 5-4 cpu clock transition and sfr register setting examples modification of table 5-8 maximum number of clocks required in f ih ? f mx and table 5-9 maximum number of clocks required in f mainc ? f subc chapter 5 clock generator modification of note 1 in figure 6-6 format of timer clock select register m (tpsm) modification of figure 6-7 format of timer mode register mn (tmrmn) (1/4) addition of description of event counter mode to table 6-4 operations from count operation enabled state to tcrmn count start 3rd edition addition of description to 6.4.3 (1) changing values set in registers top,toep,tolp, and tomp during timer operation chapter 6 timer array unit
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 1005 jun 20, 2011 (7/14) edition description chapter addition of description to 6.7.1 operation as interval timer/square wave output modification of figure 6-37 block diagram of operation as interval timer/square wave output addition of (2) when the timer input (tipq pin input, f sub /4, f sub /2 or intrtci) is selected as count clock to figure 6-39 example of set contents of registers during operation as interval timer/square wave output modification of figure 6-40 operation procedure of interval timer/square wave output function (1/2) chapter 6 timer array unit modification of caution in figure 7-3 format of real-time counter control register 0 (rtcc0) addition of description to 7.3 (8) hour count register (hour) addition of description to figure 7-14 format of watch error correction register (subcud) modification of figure 7-26 512 hz or 16.384 khz output setting procedure chapter 7 real- time counter addition of caution 3 to figure 9-2 format of clock output select register n (cksn) modification of remark in 9.4.1 operation as output pin modification of figure 9-4 remote control output application example chapter 9 clock output/buzzer output controller addition of notes 2, 3 to and modification of cautions 1, 2 in figure 10-4 format of a/d converter mode register (adm) modification of table 10-2 a/d conversion time selection modification of description in 10.3 (4) analog reference voltage control register (advrc) modification of figure 10-8 format of analog reference voltage control register (advrc) addition of <3> to and modification of <8> and caution 4 in 10.4.1 basic operations of a/d converter modification of figure 10-16 software trigger mode (continuous conversion mode) modification of figure 10-17 software trigger mode (single conversion mode) modification of <2> in 10.4.3 (3) timer trigger mode (continuous conversion mode) modification of figure 10-18 timer trigger mode (continuous conversion mode) modification of <2> in and addition of <5> to 10.4.3 (4) timer trigger mode (single conversion mode) modification of figure 10-19 timer trigger mode (single conversion mode) addition of <3> to and modification of <8>, <11> and caution 7 in setting methods of 10.4.3 a/d converter operation modes modification of 10.6 (1) operating current in stop mode and (12) rewriting dacswn during a/d conversion chapter 10 a/d converter modification of figure 11-1 block diagram of d/a converter addition of note 1 to and modification of note 2 and remark in figure 11-3 format of d/a converter mode register (dam) modification of caution in figure 11-4 format of d/a conversion value setting registers w0 and w1 (dacsw0, dacsw1) modification of <3> , <6> in and addition of cautions 1, 2 to 11.4.1 operation in normal mode modification of <3> , <6> , <9> in and addition of cautions 1 to 3 to 11.4.2 operation in real-time output mode 3rd edition modification of (3) in 11.5 cautions for d/a converter chapter 11 d/a converter
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 1006 jun 20, 2011 (8/14) edition description chapter addition of <5> to 12.4.1 single amp mode chapter 12 operational amplifier modification of figure 13-1 block diagram of voltage reference modification of description in 13.3 (2) analog reference voltage control register (advrc) modification of figure 13-3 format of analog reference voltage control register (advrc) modification of <2> to <5> in 13.4.1 reference voltage output mode addition of 13.5 cautions for voltage reference chapter 13 voltage reference addition of note to 14.1.3 simplified i 2 c (iic10, iic20) modification of figure 14-1 block diagram of serial array unit 0 modification of figure 14-2 block diagram of serial array unit 1 modification of note 2 in figure 14-5 format of serial clock select register m (spsm) modification of descri ption of and addition of note to figure 14-7 format of serial communication operation setting register mn (scrmn) (1/3) addition of caution 3 to figure 14-8 format of serial data register mn (sdrmn) addition of note to figure 14-9 format of serial status register mn (ssrmn) modification of figure 14-10 format of serial flag clear trigger register mn (sirmn) modification of figure 14-26 procedure for stopping master transmission modification of figure 14-27 procedure for resuming master transmission modification of figure 14-28 timing chart of master transmission (in single- transmission mode) modification of figure 14-30 timing chart of master transmission (in continuous transmission mode) modification of figure 14-31 flowchart of master transmission (in continuous transmission mode) modification of figure 14-36 timing chart of master reception (in single- reception mode) modification of figure 14-40 procedure for stopping master transmission/reception modification of figure 14-41 procedure for resuming master transmission/reception modification of figure 14-42 timing chart of master transmission/reception (in single-transmission/reception mode) modification of figure 14-44 timing chart of master transmission/reception (in continuous transmission/reception mode) modification of figure 14-45 flowchart of master transmission/reception (in continuous transmission/reception mode) modification of 14.5.4 slave transmission and note 1 modification of figure 14-48 procedure for stopping slave transmission modification of figure 14-49 procedure for resuming slave transmission modification of figure 14-50 timing chart of slave transmission (in single- transmission mode) 3rd edition modification of figure 14-52 timing chart of slave transmission (in continuous transmission mode) chapter 14 serial array unit
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 1007 jun 20, 2011 (9/14) edition description chapter modification of figure 14-53 flowchart of slave transmission (in continuous transmission mode) modification of 14.5.5 slave reception and note 1 modification of figure 14-57 procedure for resuming slave reception modification of figure 14-58 timing chart of slave reception (in single- reception mode) modification of 14.5.6 slave transmission/reception and note 1 modification of figure 14-62 procedure for stopping slave transmission/reception modification of figure 14-63 procedure for resuming slave transmission/reception modification of figure 14-64 timing chart of slave transmission/reception (in single-transmission/reception mode) modification of figure 14-66 timing chart of slave transmission/reception (in continuous transmission/reception mode) modification of figure 14-67 flowchart of slave transmission/reception (in continuous transmission/reception mode) modification of note 2 in table 14-2 selection of operation clock addition of caution to 14.6 operation of uart (uart0, uart1, uart2, uart3) communication modification of figure 14-70 procedure for stopping uart transmission modification of figure 14-72 timing chart of uart transmission (in single- transmission mode) modification of figure 14-74 timing chart of uart transmission (in continuous transmission mode) modification and addition of description in 14.6.2 uart reception addition of description of figure 14-76 example of contents of registers for uart reception of uart (uart0, uart1, uart2, uart3) modification of figure 14-80 timing chart of uart reception modification of the transfer data length in 14.6.3 lin transmission modification of note 2 in figure 14-82 transmission operation of lin modification of the transfer data length in 14.6.4 lin reception modification of note 2 in table 14-3 selection of operation clock addition of note to 14.7 operation of simplified i 2 c (iic10, iic20) communication addition of note, remark and the description of the transfer rate to 14.7.1 address field transmission modification of figure 14-89 initial setting procedure for address field transmission modification of figure 14-90 timing chart of address field transmission addition of note, remark and the description of the transfer rate to 14.7.2 data transmission modification of figure 14-93 timing chart of data transmission addition of note, remark and the description of the transfer rate to 14.7.3 data reception modification of figure 14-96 timing chart of data reception 3rd edition modification of figure 14-97 flowchart of data reception chapter 14 serial array unit (continuation)
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 1008 jun 20, 2011 (10/14) edition description chapter modification of and addition of note to figure 14-98 timing chart of stop condition generation addition of caution to 14.7.5 calculating transfer rate modification of note 2 in table 14-4 selection of operation clock chapter 14 serial array unit (continuation) addition of caution 3 to figure 15-3 format of iica shift register (iica) modification of description in 15.2 (2) slave address register (sva) modification of description in figure 15-4 format of slave address register (sva) addition of note 3 to and modification of caution in figure 15-6 format of iica control register 0 (iicctl0) (1/4) addition of description to figure 15-6 format of iica control register 0 (iicctl0) (2/4) modification of description in figure 15-6 format of iica control register 0 (iicctl0) (3/4) addition of description to figure 15-9 format of iica control register 1 (iicctl1) (1/2) modification of 15.4.2 (1) setting transfer clock on master side modification of figure 15-23 flow when setting wup = 0 upon address match (including extension code reception) modification of figure 15-24 when operating as master device after releasing stop mode other than by intiica and deletion of figure 15-25 when operating as slave device after releasing stop mode other than by intiica (when not required to operate as master device) in old edition modification of 15.5.14 (1) when communication reservation function is enabled (bit 0 (iicrsv) of iica flag register (iicf) = 0) modification of note 1 in figure 15-27 communication reservation protocol modification of note in figure 15-29 master operation in multi-master system (2/3) chapter 15 serial interface iica modification of figure 16-1 block diagram of lcd controller/driver addition of caution 4 to and modification of caution 5 in figure 16-3 format of lcd display mode register modification of figure 16-4 format of lcd clock control register addition of caution 5 to and modification of figure 16-5 format of lcd boost level control register (vlcd) addition of <8> to 16.5 (2) internal voltage boosting method addition of caution to figure 16-31 examples of lcd drive power connections (external resistance division method) chapter 16 lcd controller/driver modification of description in 19.2 interrupt sources and configuration chapter 19 interrupt functions modification of table 21-2 operating statuses in stop mode chapter 21 standby function modification of caution 1 modification of figure 22-1 block diagram of reset function modification of table 22-1 operation statuses during reset period modification of table 22-2 hardware statuses after reset acknowledgment modification of 22.1 register for confirming reset source 3rd edition modification of and addition of caution 2 to figure 22-5 format of reset control flag register (resf) chapter 22 reset function
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 1009 jun 20, 2011 (11/14) edition description chapter modification of figure 23-1 block diagram of power-on-clear circuit chapter 23 power- on-clear circuit modification of note 4 in figure 24-2 format of low-voltage detection register (lvim) 24.4.1 (1) when detecting level of supply voltage (v dd ) ? modification of <5> in (a) when lvi default start function stopped is set (lvioff = 1) 24.4.1 (2) when detecting level of input voltage from external input pin (exlvi) ? modification of <4> 24.4.2 (1) when detecting level of supply voltage (v dd ) ? modification of <5> in (a) when lvi default start function stopped is set (lvioff = 1) 24.4.2 (2) when detecting level of input voltage from external input pin (exlvi) ? modification of <4> modification of figure 24-12 delay from the time lvi reset source is generated until the time lvi reset has been generated or released chapter 24 low- voltage detector modification of 25.1 regulator overview addition of caution 1, 4 to figure 25-1 format of regulator mode control register (rmc) chapter 25 regulator addition of 26.4 setting of option byte chapter 26 option byte modification of 27.4.5 regc pin addition of caution 5 to 27.8 flash memory programming by self-programming modification of 27.8.2 flash shield window function chapter 27 flash memory modification of chapter chapter 31 electrical specifications (target) addition of chapter appendix b register index addition of chapter appendix c list of cautions 3rd edition addition of d.2 revision history of preceding editions appendix d revision history change url of renesas electronics website change product names to a version ( pd78f150xa) deletion of target from the capacitance value of the capacitor connected to the regc pin change names of a/d conversion modes ? conversion mode 1 normal mode 1 ? conversion mode 2 normal mode 2 ? conversion mode 3 low voltage mode addition of description of 20 mhz internal high-speed oscillation clock oscillator throughout change of 1.2 ordering information 4th edition change the value of vectored interrupt sources of 78k0r/lf3 chapter 1 outline
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 1010 jun 20, 2011 (12/14) edition description chapter change of description of the wait time of the fsel change of 5.4.3 internal high-speed oscillator change of figure 5-13. clock generator operation when power supply voltage is turned on (when lvi default start function stopped is set (option byte: lvioff = 1)) and figure 5-14. clock generator operation when power supply voltage is turned on (when lvi default start function enabled is set (option byte: lvioff = 0)) change of 5.6.5 cpu clock status transition diagram change of 5.6.6 condition before changing cpu clock and processing after changing cpu clock chapter 5 clock generator change of 8.4.3 setting window open period of watchdog timer chapter 8 watchdog timer deletion of tbd from operation stabilization time 1 s of a/d voltage comparator change of voltage boost circuit stabilization time (tbd) to (10 s) addition of note 4 to table 10-2. a/d conversion time selection deletion of tbd from the output impedance within 1 k of the analog input source change of table 10-8. resistance and capacitance values of equivalent circuit (reference values) chapter 10 a/d converter change of wait time to 20 s or more and deletion of tbd from the settling time (18 s (max.)) chapter 11 d/a converter change of turn-on time (tbd) to 20 s (max.) chapter 12 operational amplifier change of caution 3 of figure 14-8. format of serial data register mn (sdrmn) change of caution of 14.7.5 calculating transfer rate chapter 14 serial array unit addition of description to caution of figure 15-6. format of iica control register 0 (iicctl0) (4/4) addition of description to note of figure 15-7. format of iica status register (iics) (2/3) addition of note to figure 15-9. format of iica control register 1 (iicctl1) (1/2) change of 15.4.2 setting transfer clock by using iicwl and iicwh registers 4th edition change of 15.6 timing charts chapter 15 serial interface iica
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 1011 jun 20, 2011 (13/14) edition description chapter addition of example of calculation of lcd frame frequency to (c) and (d) of figure 16-13. common signal waveforms (2/2) change of caution of figure 16-31. examples of lcd drive power connections (external resistance division method) change the capacitance value of external capacitors to 0.47 f 30% in 16.8.2 internal voltage boosting method and 16.8.3 capacitor split method chapter 16 lcd controller/ driver addition of note to figure 18-4. format of dma mode control register n (dmcn) (1/2) change of description of figure 18-7. example of setting for csi consecutive transmission addition of 18.5.2 csi master reception and 18.5.3 csi transmission/reception change of 18.5.6 holding dma transfer pending by dwaitn and addition of caution change of 18.5.7 forced termination by software change of 18.6 cautions on using dma controller chapter 18 dma controller change value of maskable interrupts of 78k0r/lf3 chapter 19 interrupt functions change of figure 26-1. format of user option byte (000c0h/010c0h) (1/2) change of 26.4 setting of option byte chapter 26 option byte addition of figure 27-3. example of wiring adapter for flash memory writing ( pd78f1508a) addition of 27.9 creating rom code to place order for previously written product chapter 27 flash memory change of examples 2 in 29.3 bcd correction circuit operation chapter 29 bcd correction circuit change of table 30-5. operation list chapter 30 instruction set deletion of (target) change of analog output voltage, output current, high, and output current, low in absolute maximum ratings (t a = 25 c) change of internal oscillator characteristics addition of recommended oscillator circuit constants change of output voltage, low (v ol2 ), supply current, and operating current of dc characteristics change of caution of (1) basic operation (3/6) in ac characteristics change of (b) during communication at same potential (csi mode) (master mode, sckp... internal clock output) of (2) serial interface: serial array unit (2/18) and addition of note 1 change of (c) during communication at same potential (csi mode) (slave mode, sckp... external clock input) of (2) serial interface: serial array unit (3/18) change of (d) during communication at same potential (simplified i 2 c mode) of (2) serial interface: serial array unit (5/18) 4th edition change of (f) communication at different potential (2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (1/2) of (2) serial interface: serial array unit (11/18) and addition of note 1 chapter 31 electrical specifications
78k0r/lx3 appendix d revision history r01uh0004ej0501 rev.5.01 1012 jun 20, 2011 (14/14) edition description chapter change of (f) communication at different potential (2.5 v, 3 v) (csi mode) (master mode, sckp... internal clock output) (2/2) of (2) serial interface: serial array unit (12/18) change of (g) communication at different potential (2.5 v, 3 v) (csi mode) (slave mode, sckp... external clock input) of (2) serial interface: serial array unit (14/18) change of (h) communication at different potential (2.5 v, 3 v) (simplified i 2 c mode) of (2) serial interface: serial array unit (17/18) change of analog characteristics chapter 31 electrical specifications (continuation) addition of chapter chapter 33 recommended soldering conditions 4th edition addition of part number of flash memory programming adapter appendix a development tools
78k0r/lx3 user?s manual: hardware publication date: rev.0.01 apr 30, 2008 rev.5.01 jun 20, 2011 published by: renesas electronics corporation
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